JP2000163462A - Method for designing semiconductor integrated circuit and record medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a timing violation without increasing a design TAT(turn- around time) and to provide the designing method for a semiconductor integrated circuit which can be highly integrated. SOLUTION: The structures of all logic circuits shown in a logic diagram are retrieved and only flip-flops are selected out of them; and only logical connection places of flip-flop direct connection structures where a following flip-flop 12 is connected directly to a precedent flip-flop 11 are selected and only logical connection places where the fan-out number of the precedent flip- flop 11 is less than a specific number (n) are selected as logical connection places where a timing violation is possibly caused. Then a delay circuit is inserted into a logical connection place to correct the logic diagram. For example, logical connection places where the flip-flop direct connection structure is constituted and the fan-out number of the precedent flip-flop 11 is less than the specific number (n) are selected and a delay circuit 14 is inserted into a data signal line DL as the output of the precedent flip-flop 11.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for designing a semiconductor integrated circuit and a computer-readable recording medium on which a program for causing a computer system to execute the method is recorded.

[0002]

2. Description of the Related Art Among LSIs classified as digital integrated circuits, in a logic LSI design flow, which is a generic term for all integrated circuits except for memory devices, the order of specification design → function design → logic design → circuit design → layout design Each design process is performed.

In the specification design, the feasibility of elements such as the specific use of the logic LSI, price, target performance, built-in functions, and compatibility with conventional products is examined, and external specifications are considered while considering the consistency between the elements. Put together. In the functional design, we first created a functional block diagram expressing the concept of data flow and control together with the main hardware, and then described all functions in detail using a hardware description language based on the functional block diagram. A detailed function description is created, and then the detailed function description is applied to a function simulator to perform function verification.

In the logical design, a functional block diagram and detailed function description are converted into specific hardware to create a logical diagram. In the layout design, first, create a circuit diagram by making a circuit design that embodies the logic expressed in the logic diagram to a level at which pattern design is possible, and then perform a pattern design based on the circuit diagram. To create
Subsequently, based on the pattern diagram, a mask for embodying each element constituting the circuit diagram and the wiring connecting the elements on the semiconductor substrate is created.

[0005]

In an actual logic LSI formed on a semiconductor substrate, wiring delay occurs due to wiring resistance, wiring capacitance, load capacitance, and the like, and the data delay and clock delay occur due to the wiring delay. There is. For example, when a propagation time difference (clock skew) occurs between clocks input to a plurality of related flip-flops, a normal synchronization operation of each flip-flop is disturbed and a data hold violation may occur.

As described above, when a data delay or a clock delay occurs, a timing violation that hinders the clock synchronization operation of the logic circuit occurs, and the detailed function description created by the function design is not satisfied. Can not be realized. Therefore, the following method has been used to prevent timing violation.

Method of Performing Timing Analysis After Layout Design First, actual wiring delay is determined after layout design, and timing analysis is performed based on the wiring delay.
Find the layout part that is causing the timing violation. Next, the logic design is performed again in consideration of the layout portion, and the logic is changed so as to satisfy the timing. Subsequently, a layout design is performed again based on the changed logic.

In this method, a timing violation in the first layout design is solved in the second layout design, but a new timing violation may occur in the second layout design. for that reason,
Until the timing violation is completely resolved, it is necessary to repeatedly perform logic design and layout design.
(Turn Around Time) increases.

Method of Performing Timing Analysis During Logic Design In logic design, it is predicted that a timing analysis will occur by estimating a wiring delay that will actually occur after layout and performing a timing analysis based on the wiring delay. A logical connection is searched for and a delay circuit (delay cell, buffer, etc.) is inserted into the logical connection so as to satisfy the timing.

This method is generally executed on logic synthesis software, and various types of logic synthesis software are sold on the market. Therefore, the method can be performed relatively easily.
However, in this method, since timing analysis is performed based on the predicted wiring delay, there is a problem that it is not always possible to deal with an actual wiring delay, and it is difficult to reliably prevent a timing violation.

In addition, when a delay circuit is inserted into all of the logical connection points where a timing violation is predicted to occur (ie, when a delay circuit is inserted in consideration of the worst case of a timing violation), the predicted wiring delay or Depending on the logical structure, a delay circuit is inserted at a logical connection point where a timing violation does not actually occur, and the number of logic circuits (the number of gates) increases by the unnecessary delay circuit, thereby increasing the circuit scale. Because of the increase, there is a problem that high integration of the logic LSI is hindered.

As described above, the conventional methods for preventing timing violations have problems. In addition, in order to perform timing analysis, the timing simulator is operated after inputting logical information into the timing simulator, so that in addition to the time required for the operation,
Since it takes time and effort to input logical information, there is a problem that the design TAT increases.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a method of designing a semiconductor integrated circuit capable of preventing a timing violation and increasing the degree of integration without increasing the design TAT. Is to provide. Another object of the present invention is to provide a computer-readable recording medium on which a program for causing a computer system to execute the method for designing a semiconductor integrated circuit is recorded.

[0014]

According to the first aspect of the present invention, there is provided a semiconductor integrated circuit having the structure of all logic circuits and all connection information between the logic circuits. And a second process of extracting a logical connection point that may cause a timing violation by referring to a preset condition based on an analysis result of the first process. The gist of the present invention is a method of designing a semiconductor integrated circuit including: a third process of performing a logic change for preventing a timing violation of a logical connection portion extracted in the second process.

Therefore, according to the present invention, in order to prevent a timing violation by correcting a logic design without performing a timing analysis, it is possible to avoid all the problems of the method for preventing a timing violation described above. Since the time and effort required for timing analysis are not required, the design TAT
Can be shortened. Further, according to the present invention, unnecessary logic changes are not performed, so that it is possible to suppress an increase in circuit scale due to the logic changes, and to achieve high integration of the logic LSI.

According to a second aspect of the present invention, in the method of designing a semiconductor integrated circuit according to the first aspect, the logic change for preventing a timing violation in the third process is performed by the second process. By inserting a delay circuit into the data signal line which is the logical connection point extracted in the above processing, the data propagation time from the preceding logic circuit to the next logic circuit may be delayed.

According to a third aspect of the present invention, in the method of designing a semiconductor integrated circuit according to the first or second aspect, the logic change for preventing a timing violation in the third processing is performed. By inserting a delay circuit into the clock signal line connected to the clock input terminal of the logic circuit at the preceding stage of the logical connection point extracted at the second processing, the clock propagation time to the logic circuit at the preceding stage is delayed. You may make it do.

According to a fourth aspect of the present invention, in the method of designing a semiconductor integrated circuit according to any one of the first to third aspects, the condition set in advance in the second processing is set. Alternatively, the number of fan-outs of the logic circuit at the preceding stage of the logical connection location that may cause a timing violation may be used.

Then, as in the invention according to claim 5,
The method for designing a semiconductor integrated circuit according to claim 4,
The data propagation time from the preceding logic circuit to the next logic circuit or the clock propagation time to the preceding logic circuit may be delayed in accordance with the fanout number.

According to a sixth aspect of the present invention, in the method of designing a semiconductor integrated circuit according to any one of the first to third aspects, the condition set in advance in the second processing is set. Alternatively, the number of inter-stage logic circuits connected in series between the logic circuit at the preceding stage and the logic circuit at the next stage of the logical connection location that may cause a timing violation may be used.

And, as in the invention according to claim 7,
The method for designing a semiconductor integrated circuit according to claim 6,
The data propagation time from the preceding logic circuit to the next logic circuit or the clock propagation time to the preceding logic circuit may be delayed according to the number of the interstage logic circuits.

According to another aspect of the present invention, in the method for designing a semiconductor integrated circuit according to any one of the first to third aspects, the condition set in advance in the second processing is set. Alternatively, a logical connection point where the preceding logic circuit and the next logic circuit are directly connected may be extracted as a logical connection point that may cause a timing violation.

This is a direct connection type logical connection point where the previous stage logic circuit is directly connected to the next stage logic circuit, and an interstage logic circuit is connected between the previous stage logic circuit and the next stage logic circuit. This is because the possibility of a timing violation (particularly, a data hold violation) is extremely high as compared with the case of the first embodiment. Then, it is only necessary to determine the presence or absence of an interstage logic circuit to determine whether or not the logical connection portion is a direct connection type logical connection portion. Therefore, the operation of extracting the logical connection portion in the second process is very simple. Yes, and can be easily implemented.

According to a ninth aspect of the present invention, in the method of designing a semiconductor integrated circuit according to any one of the first to eighth aspects, a logic change is made to a logic diagram created by logic design. By doing so, the logic diagram may be modified. According to a tenth aspect of the present invention, in the method of designing a semiconductor integrated circuit according to any one of the first to eighth aspects, a logic change is performed on a circuit diagram or a pattern diagram in a layout design. Thus, the circuit diagram or the pattern diagram may be modified.

Next, an eleventh aspect of the present invention is directed to a computer-readable storage medium storing a program for causing a computer system to execute the semiconductor integrated circuit designing method according to any one of the first to tenth aspects. It provides a possible recording medium. That is, the function of executing the invention described in any one of claims 1 to 10 can be provided as a program executed by a computer system. In the case of such a program, for example, semiconductor memory, hard disk, floppy disk, data card (IC card, magnetic card, etc.), optical disk (CD-ROM, DVD, etc.), magneto-optical disk (MD
Etc.), a phase change disk, a magnetic tape, or another computer-readable recording medium, and can be used by loading it into a computer system and activating it as necessary. In addition, ROM and backup RA
The above program may be recorded as M on a computer-readable recording medium, and the ROM or the backup RAM may be incorporated in a computer system and used.

[0026]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a flowchart illustrating a method for designing a semiconductor integrated circuit according to the present embodiment.

The function of executing the method of designing a semiconductor integrated circuit according to the present embodiment can be provided as a program executed by a computer system. Such programs are stored in various computer-readable recording media (for example, semiconductor memory, hard disk, floppy (registered trademark) disk, data card (IC card, magnetic card, etc.), optical disk (CD-ROM, D-ROM).
VD, etc.), a magneto-optical disk (MD, etc.), a phase change disk, a magnetic tape, etc.), and can be used by loading it into a computer system as necessary and starting up. Alternatively, the program may be recorded in a ROM or a backup RAM as a computer-readable recording medium, and the ROM or the backup RAM may be incorporated in a computer system and used.

In the design flow of the logic LSI of the present embodiment, similarly to the conventional case, each design process is performed in the order of specification design → function design → logic design, and a logic diagram is created by logic design. Then, the flowchart shown in FIG. 1 is executed. First, in step (hereinafter, referred to as S) 1000, data of a logic diagram created by logic design is input.

Next, in S2000, the structures (net information) of all the logic circuits shown in the logic diagram and all the connection information (number of fan-outs) between the logic circuits are analyzed. Next, in S3000, based on the analysis result in S2000, by referring to preset conditions, a logical connection portion (net) that may cause a timing violation is extracted.

Here, examples of the structure of the logic circuit are shown in FIGS. In the example shown in FIG. 2A, only one flip-flop 12 in the next stage is directly connected to the flip-flop 11 in the previous stage. In the example shown in FIG. 2B, M inverters 13 (M is a positive integer) are connected in series between the flip-flops 11 and 12 as an interstage logic circuit.

In the example shown in FIG. 3A, the flip-flop 12 in the next stage is 1
And the next stage flip-flop 12
In parallel, (N-1) (N is a positive integer) various logic circuits 15 are directly connected to the flip-flop 11 in the preceding stage. That is, for the flip-flop 11 in the preceding stage,
A total of N flip-flops 12 and various logic circuits 15 at the next stage are directly connected. In this case, the fan-out number of the flip-flop 11 is N.

The example shown in FIG. 3 (b) is a combination of the example shown in FIG. 2 (b) and the example shown in FIG. 3 (a). 1
2, an inverter 13 as an inter-stage logic circuit has M
Are connected in series, and a total of (N-1) logic circuits 15 are connected. That is, N flip-flops 12 and various logic circuits 15 in the next stage are combined with the preceding flip-flop 11 via the inverter 13 as an inter-stage logic circuit. Again,
The fan-out number of the flip-flop 11 becomes N.

There are three types of flip-flops 11, 12: asynchronous, synchronous, and synchronous, but the present embodiment can be applied to any type. Asynchronous flip-flops are those that cannot perform synchronous operations. The synchronizing flip-flop has a clock input terminal (synchronization input terminal) and operates only when an H-level clock is input to the clock input terminal. Synchronous flip-flops have a clock input terminal and operate only at the rising edge of the clock input to the clock input terminal (positive edge trigger type) or those that operate only at the falling edge of the clock (Negative edge trigger type). The synchronous flip-flop has R
There are an S flip-flop, a D flip-flop, a JK flip-flop, and the like. Generally, asynchronous and synchronous flip-flops are collectively referred to as latches, and synchronous flip-flops are simply referred to as flip-flops.

FIG. 4 is a flowchart for explaining an example of the details of the processing in S3000. First, S
At 3010, the structures (net information) of all the logic circuits shown in the logic diagram are searched, and only flip-flops are selected from them.

Next, in S3020, of the selected flip-flops, only the logical connection portions of the flip-flop direct connection structure in which the next-stage flip-flop 12 is directly connected to the preceding flip-flop 11 are selected.
Next, in S3030, among the selected logical connection portions of the flip-flop direct connection structure, the fan-out number (the number of net connections) of the preceding flip-flop 11 is a predetermined number n.
Only the following logical connection points are selected. The logical connection point selected in S3030 is a logical connection point that may cause a timing violation. Then, the process returns to the main routine shown in FIG. 1 and shifts to S4000.

In S4000, the logical connection point (the logical connection point selected in S3030) which may cause a timing violation extracted in S3000 is
Each delay circuit is inserted, and based on the delay circuit, S
The logic diagram input at 1000 is corrected and completed.

That is, in S3030, as shown in FIG. 5A, a logical connection portion having a flip-flop direct connection structure and a fan-out number of the preceding flip-flop 11 of a predetermined number n or less is selected. Then, in S4000, as shown in FIG. 5B, the delay circuit 14 is inserted into the data signal line DL which is the output of the flip-flop 11 in the preceding stage.

Incidentally, as the delay circuit 14, a delay cell or a buffer may be used. The delay cell is configured by connecting a plurality of inverters in series. Examples of the buffer include various circuits (for example, a waveform shaping circuit, a driving circuit, and the like) in which a predetermined delay time occurs in inputting and outputting data.

Thereafter, using the logic diagram modified in S4000, a layout design is performed in the same manner as in the related art. As described above, in the examples shown in FIGS. 4 and 5, the structures (net information) of all the logic circuits and all the connection information between the logic circuits represented in the logic diagrams created by the logic design are analyzed. , The number of fan-outs of the flip-flops 11 directly connected to the flip-flop structure and the number of fan-outs (the number of connected nets)
Extracts logical connection points (nets) having a predetermined number n or less and corrects the logic diagram by changing the logic so that the delay circuit 14 is inserted into the logical connection points.

When the flip-flops 11 and 12 have a direct connection structure, the flip-flop 11 of the preceding stage is connected between the flip-flops 11 and 12 as in the case where an inverter 13 is connected between the flip-flops 11 and 12. Since the output is not delayed by the inverter 13, the output of the flip-flop 11 in the preceding stage is promptly output from the flip-flop 12 in the next stage.
Is input to Therefore, each flip-flop 11, 12
Is caused by a propagation time difference (clock skew) of the clock CK input to the flip-flops 11,
When 12 has a direct connection structure, a data hold violation (timing violation) is likely to occur.

The smaller the fan-out number of the preceding flip-flop 11, the smaller the number of fan-outs of the preceding flip-flop 11.
, The output capacitance of the preceding flip-flop 11 is immediately input to the next flip-flop 12. Therefore, each flip-flop 1
Due to the propagation time difference (clock skew) between the clocks CK input to the clock signals 1 and 12, the data hold violation (timing violation) is more likely to occur as the number of fan-outs of the preceding flip-flop 11 decreases.

Therefore, in the examples shown in FIGS. 4 and 5,
By assuming that there is a high possibility that a logical connection point having a flip-flop direct connection structure and a fan-out number of the preceding flip-flop 11 of which the fan-out number is equal to or less than a predetermined number n causes a timing violation, the delay circuit 14 is inserted into the logical connection point. The delay of the output of the flip-flop 11 is input to the flip-flop 12 of the next stage to prevent occurrence of a data hold violation.

By the way, since it is only necessary to judge the presence or absence of the interstage logic circuit to judge whether or not it is the logical connection part of the flip-flop direct connection structure, the process of S3020 is very simple and easy. Can be implemented.
Note that the predetermined number n of the fan-out numbers is determined by various logic circuits 15 connected in parallel with the flip-flop 12 of the next stage.
May be set to an appropriate value by an experiment for determining the degree of occurrence of a timing violation when the number is changed.

The predetermined number n of the fan-out numbers described above
, The delay time of the delay circuit 14 to be inserted may be shortened. That is, a plurality of delay circuits 14 having different delay times are prepared in advance, and a delay circuit 14 having an optimum delay time is selected corresponding to the predetermined number n of the fan-out numbers. What is necessary is just to insert in the said logical connection part.

FIG. 6 is a flowchart for explaining another example of the details of the processing in S3000. First,
In S3110, S3010 in the example shown in FIG.
Performs the same processing as.

Next, in S3120, among the flip-flops selected in S3110, the number of inter-stage connection circuits (for example, inverters 13) connected between the flip-flops 11 and 12 is equal to or less than a predetermined number m. Select only logical connection points. Next, in S3130,
From the logical connection points selected in S3120, only the logical connection points where the fan-out number (the number of net connections) of the flip-flop 11 in the preceding stage is equal to or less than the predetermined number n are selected. The logical connection point selected in S3030 is a logical connection point that may cause a timing violation. Then, the process returns to the main routine shown in FIG. 1 and shifts to S4000.

That is, in S3110, as shown in FIG. 7A, the number of interstage connection circuits (inverters 13) is a predetermined number m or less and the number of fan-outs of the preceding flip-flop 11 is n or less. Select a location. Then, in S4000, as shown in FIG. 7B, the delay circuit 14 is inserted into the data signal line DL which is the output of the flip-flop 11 in the preceding stage.

As described above, in the examples shown in FIGS. 6 and 7, the structures (net information) of all the logic circuits represented in the logic diagrams created by the logic design and all the connection information between the logic circuits are included. Is analyzed, and the flip-flop 1
The number of interstage connection circuits (inverters 13) connected in series between the first flip-flop 12 and the next-stage flip-flop 12 is equal to or less than a predetermined number m, and the number of fan-outs (number of net connections) of the preceding flip-flop 11 Extracts logical connection points (nets) of a predetermined number n or less, and adds delay circuits 1 to the logical connection points.
The logic diagram is modified by changing the logic so that 4 is inserted.

Here, the smaller the number of inter-stage connection circuits, the faster the output of the preceding flip-flop 11 is input to the next flip-flop 12, so that the clock CK input to each flip-flop 11, 12 , A data hold violation (timing violation) is likely to occur.

Therefore, in the examples shown in FIGS. 6 and 7,
It is determined that there is a great possibility that a logical connection point where the number of interstage connection circuits is equal to or less than a predetermined number m and the fan-out number of the preceding flip-flop 11 is equal to or less than a predetermined number n causes a timing violation. , The output of the preceding flip-flop 11 is delayed and input to the next flip-flop 12, thereby preventing occurrence of a data hold violation.

It should be noted that the predetermined number n of the fan-out numbers described above
Can be set to an appropriate value by an experiment for determining the degree of occurrence of timing violation when the number of various logic circuits 15 connected between the preceding flip-flop 11 and the next flip-flop 12 is changed. Good.

The predetermined number m of the interstage connection circuits may be set to an appropriate value by an experiment for determining the degree of occurrence of a timing violation when the number of interstage connection circuits is changed. The delay time of the inserted delay circuit 14 may be reduced as the predetermined number m of the interstage connection circuits increases. That is, a plurality of delay circuits 14 having different delay times are prepared in advance, and the delay circuit 14 having the optimum delay time is selected in accordance with the predetermined number m of the inter-stage connection circuits, and the selected delay circuit is selected. The circuit 14 may be inserted at the logical connection point.

As described in detail above, in the present embodiment, the preset conditions (the flip-flop direct connection structure, the number of fan-outs of the preceding flip-flop 11 is equal to or less than a predetermined number n, the number of inter-stage connection circuits) Is a predetermined number m or less) to extract a logical connection point that may cause a timing violation, and uniquely insert the delay circuit 14 into the logical connection point to correct the logic diagram. To prevent timing violations.

Therefore, according to the present embodiment, since the logic design is corrected to prevent the timing violation without performing the timing analysis, it is possible to avoid all the problems of the method for preventing the timing violation described above. In addition, since the time and effort required for the timing analysis become unnecessary, the design T
AT can be shortened. In the present embodiment,
Since an unnecessary delay circuit is not provided, an increase in circuit scale can be suppressed, and high integration of a logic LSI can be achieved.

According to the present embodiment, since it is not necessary to reduce the clock propagation time difference (clock skew) more than necessary, the design TAT can be shortened accordingly. In addition, the number of delay circuits to be inserted at the logical connection point in order to reduce the clock propagation time difference can be reduced, so that it is possible to suppress an increase in circuit scale, and to achieve high integration of the logic LSI. it can.

The present invention is not limited to the above embodiment, but may be modified as follows. Even in such a case, the same operation and effect as in the above embodiment can be obtained. [1] As shown in FIG. 5 or 7, even when the clocks CK1 and CK2 input to the flip-flops 11 and 12 are different (that is, when the clocks CK1 and CK2 are different-phase clocks), Step 1
The delay circuit 14 may be inserted as in the case where the clocks CK input to 1 and 12 are the same.

[2] In the example shown in FIG. 5 or FIG. 7, the data propagation time is delayed by inserting the delay circuit 14 into the data signal line DL. However, FIG.
As shown in (b), the clock delay time may be delayed by inserting the delay circuit 14 in the clock signal line instead of the data signal line DL. In this case, for the logical connection point which may cause a timing violation extracted in S3000, the delay circuit 14 is connected to the clock signal line connected to the clock input terminal of the flip-flop 11 located at the preceding stage of the logical connection point. Is inserted, the output of the previous-stage flip-flop 11 is delayed and input to the next-stage flip-flop 12.

According to the example shown in FIG.
The same operation and effect as the example shown in (b) can be obtained. According to the example shown in FIG. 8B, the same operation and effect as those of the example shown in FIG. 7B can be obtained. [3] In the above embodiment, the data of the logic diagram is modified by making a logic change to the logic diagram created by the logic design, and the layout design is conventionally performed using the modified logic diagram. .

However, instead of correcting the logic diagram by making a logic change to the logic diagram, the logic change may be performed in the layout design. For example, in the layout design, the data of the circuit diagram is modified by changing the logic so that the delay circuit is inserted into the circuit diagram created as before, and the pattern design is performed using the modified circuit diagram as before. It may be. Also, in the layout design, modify the data of the pattern diagram by changing the logic so that a delay circuit is inserted into the pattern diagram created as before, and create a mask using the corrected pattern diagram as before Is also good. That is, the present invention may be implemented at any stage of the logic design and the layout design.

[4] In the above embodiment, an example was described in which the inverter 13 was used as an inter-stage logic circuit. However, the invention is not limited to the inverter, but any logic circuit (for example, flip-flop, adder, counter, multiplier, etc.) , Shifter, ALU
(Arithmetic Logic Unit), FIFO (First In Firs)
It is needless to say that the present invention can also be applied to the case where t.

[5] In the above embodiment, the flip-flop 1
Although the present invention is applied to 1 and 12, the present invention is not limited to flip-flops but may be applied to any logic circuit (for example, an adder, a counter, a multiplier, a shifter, an ALU, a FIFO, etc.).

[Brief description of the drawings]

FIG. 1 is a flowchart for explaining the operation of an embodiment embodying the present invention.

FIG. 2 is a block diagram illustrating an embodiment.

FIG. 3 is a block diagram illustrating an embodiment.

FIG. 4 is a flowchart for explaining the details of the process of S3000 in FIG. 1;

FIG. 5 is a block diagram illustrating an embodiment.

FIG. 6 is a flowchart for explaining details of the process of S3000 in FIG. 1;

FIG. 7 is a block diagram illustrating an embodiment.

FIG. 8 is a block diagram for explaining another embodiment.

[Explanation of symbols]

 11: preceding flip-flop 12: next-stage flip-flop 13: inverter 14: delay circuit 15: various logic circuits DL: data signal lines CK, CK1, CK2: clock

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5B046 AA08 BA03 BA04 DA00 DA05 JA07 5F064 BB02 BB07 BB19 BB20 DD13 DD25 EE15 EE47 EE54 HH06

Claims (11)

[Claims] A first processing for analyzing the structures of all the logic circuits constituting the semiconductor integrated circuit and all connection information between the logic circuits; and setting in advance based on an analysis result of the first processing. A second process for extracting a logical connection point that may cause a timing violation by referring to the set conditions, and a logic for preventing a timing violation of the logical connection point extracted in the second process. And a third process for performing a change. 2. The method for designing a semiconductor integrated circuit according to claim 1, wherein the logical change for preventing a timing violation in the third processing is a logical connection point extracted in the second processing. A method for designing a semiconductor integrated circuit, wherein a data propagation time from a preceding logic circuit to a next logic circuit is delayed by inserting a delay circuit into a data signal line. 3. The method for designing a semiconductor integrated circuit according to claim 1, wherein the logic change for preventing a timing violation in the third process is performed by the logic extracted in the second process. By inserting a delay circuit into the clock signal line connected to the clock input terminal of the logic circuit at the previous stage of the connection point,
A method for designing a semiconductor integrated circuit, comprising delaying a clock propagation time for a logic circuit in a preceding stage. 4. The method for designing a semiconductor integrated circuit according to claim 1, wherein the condition set in advance in said second processing is:
A method of designing a semiconductor integrated circuit, wherein the number is a fanout number of a logic circuit at a stage preceding a logic connection point where a timing violation may occur. 5. The method for designing a semiconductor integrated circuit according to claim 4, wherein a data propagation time from a preceding logic circuit to a next logic circuit or a clock for the preceding logic circuit is corresponding to the number of fan-outs. A method for designing a semiconductor integrated circuit, wherein a propagation time is delayed. 6. The method for designing a semiconductor integrated circuit according to claim 1, wherein the condition set in advance in said second processing is:
A method for designing a semiconductor integrated circuit, comprising: the number of inter-stage logic circuits connected in series between a logic circuit at a preceding stage and a logic circuit at a next stage of a logic connection portion that may cause a timing violation. 7. The method for designing a semiconductor integrated circuit according to claim 6, wherein a data propagation time from a preceding logic circuit to a next logic circuit or a logic of a preceding logic circuit corresponds to the number of inter-stage logic circuits. A method for designing a semiconductor integrated circuit, wherein a clock propagation time for a circuit is delayed. 8. The method for designing a semiconductor integrated circuit according to claim 1, wherein the condition set in advance in said second processing is:
A method for designing a semiconductor integrated circuit, wherein the logic circuit is a logical connection part where a preceding logic circuit and a next logic circuit are directly connected. 9. The method for designing a semiconductor integrated circuit according to claim 1, wherein the logic diagram is modified by performing a logic change on the logic diagram created by the logic design. Characteristic semiconductor integrated circuit design method. 10. The method for designing a semiconductor integrated circuit according to claim 1, wherein a logic change is performed on the circuit diagram or the pattern diagram in the layout design. A method for designing a semiconductor integrated circuit, comprising: 11. A computer-readable recording medium in which a program for causing a computer system to execute the method for designing a semiconductor integrated circuit according to claim 1 is recorded.