JP2000155407A - Reticle and production of reticle - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a reticle with which the enhancement of working efficiency for reticle formation. SOLUTION: The patterns of the reticle 100 comprises product patterns 10 which are arranged with patterns 10a to 10f of product chips in a matrix form of 2 rows×3 columns, patterns 20a and 20b of TEG(test element group) chips adjacent to light shielding zones 30a and 30b along the side parts of the patterns 10b and 10e and formed to a rectangular shape of the same length as the length of these side parts, the light shielding zones 30a and 30b which are arranged between the patterns 10b and 10e and the TEG patterns 20a and 20b and prevent exposure exclusive of the positions to be exposed and an outer frame 40 which encloses the product patterns 10, the TEG patterns 20a and 20b and the light shielding zones 30a and 30b, has projecting parts 40a and 40b projected in correspondence to the external shapes of the TEG patterns 20a and 20b and the light shielding zones 30a and 30b and prevents the exposure exclusive of the positions to be exposed. The patterns are formed to a shape lacking the four corners of the rectangular shape reticle 100 a whole.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to a reticle,
In particular, the present invention relates to a configuration of a reticle having a pattern formed by exposing a negative resist by scanning exposure.

[0002]

2. Description of the Related Art When a semiconductor chip is manufactured, a desired pattern formed on a reticle is reduced and projected by an exposure apparatus such as a stepper and transferred onto a wafer substrate.

A conventional reticle corresponds to a pattern of product chips arranged in a matrix, a light-shielding band arranged along the pattern arranged in the row direction, and a pattern of product chips arranged in the row direction. TEG arranged
(Test Element Group) A configuration in which an outer frame having a predetermined width is arranged around a region formed from the pattern of the chip.

Therefore, when exposing a wafer substrate using reticles having different reduction magnifications, the number of TEG chip patterns transferred by a reticle having a higher magnification is smaller than the number of patterns of TEG chips transferred by a reticle having a lower magnification. And the number of unnecessary TEG chips is formed on the wafer substrate, and the utilization rate of the wafer substrate is reduced.

In order to solve such a problem, Japanese Patent Application Laid-Open No. 10-50572 discloses a conventional reticle in which a light-shielding portion is provided instead of a part of the TEG chip pattern. A reticle having a configuration like the illustrated reticle 200 is disclosed.

The pattern formed on the reticle 200 is
Product chip patterns 10a to 10f arranged in a matrix of 2 rows × 3 columns, and product chip pattern 10
b, 10e adjacent to the pattern 20a of the TEG chip,
20b, the light-shielding portions 25a and 25b adjacent to the product chip patterns 10a and 10c, the product chip patterns 10d and 10f, and the product chip patterns 10a to 10c.
f and light-shielding bands 30a, 30 disposed between the TEG chip patterns 20a, 20b and the light-shielding portions 25a, 25b.
b, product chip patterns 10a to 10f and shading band 3
An outer frame 40 having a constant width is formed around the light shielding portions 25a and 25b and the light shielding portions 25a and 25b, and is formed in a rectangular shape as a whole.

[0007] However, the reticle 200 can increase the number of product chips formed on the wafer substrate, but increases the area of the light-shielding film due to the provision of the light-shielding portions 25a and 25b.
When creating a fine pattern on a reticle, the pattern is drawn on a negative resist by an electron beam drawing method or the like.As the area of the light-shielding film increases, the exposure time when exposing the reticle is increased. There is a problem that the reticle manufacturing time increases.

The resolution of the TEG chip patterns 20a, 20b transferred to the wafer substrate may be reduced by the reflected light of the light applied to the light shielding portions 25a, 25b. Since the patterns 20a and 20b of the TEG chip need to be accommodated in a limited area, the intervals between the patterns are formed narrower than the patterns 10a to 10f of the product chip. For this reason, there is a problem that a defect occurs in the TEG chip due to a decrease in resolution, a sufficient inspection cannot be performed, and the reliability of a product chip decreases.

Further, as the area of the light-shielding film and the time required for forming the reticle are increased, a portion which is not exposed due to the adhesion of foreign matter is formed on the resist film when the reticle is formed, and a pinhole for transmitting light for exposing the wafer substrate is shielded. There is a problem that the reliability of a product chip is reduced in some cases.

[0010]

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a reticle capable of improving the working efficiency of reticle manufacturing. Another object of the present invention is to provide a reticle capable of manufacturing a highly reliable semiconductor chip.

[0011]

In order to achieve the above object, a reticle according to a first aspect of the present invention is formed on a light-transmitting substrate and a rectangular shape as a whole on the substrate.
A product chip pattern for forming a plurality of product chips, and a test circuit formed on the substrate along one side of the product chip pattern, the side corresponding to the one side being formed shorter than the one side A first test pattern, and a first test pattern disposed on the substrate so as to shield light between the product chip pattern and the first test pattern, and formed to have substantially the same length as the first test pattern. First
Surrounding the light-shielding band, the product chip pattern, the first light-shielding band, and the first test pattern on the substrate;
And a light-shielding frame having a first protruding portion corresponding to the outer shape of the first test pattern.

Since the pattern formed on the reticle has an outer shape formed to protrude corresponding to the first light-shielding band and the first test pattern, the entire pattern is formed in a rectangular shape. The area of the light-shielding portion formed from the first light-shielding band or the frame can be reduced as compared with a normal case. Normally, the light shielding portion has a high light reflectance, and reflects exposure light when exposing a semiconductor wafer. In this reticle, since the area of the light shielding portion is small, the amount of reflected light is suppressed, and it is possible to prevent the resolution of the pattern transferred to the wafer substrate from being reduced by the reflected light. In addition, since the area of the light-shielding portion is reduced, the probability of exposure in a state in which a foreign substance adheres to the resist film during the production of the reticle can be reduced, and a decrease in the production yield of the reticle itself can be suppressed.

The reticle is disposed on the substrate,
A second test pattern for forming a test circuit, wherein the second test pattern is arranged along another side facing one side of the product chip pattern, and a side corresponding to the other side is formed shorter than the other side;
A second light-shielding band disposed on the substrate so as to shield light between the product chip pattern and the second test pattern, and formed to have substantially the same length as the second test pattern; The frame further surrounds the pattern of the product chip, the first and second light-shielding bands, and the first and second test patterns, and has an outer shape defined by the second light-shielding band and the second test pattern. May be further provided.

The product chip pattern, the first and second test patterns, and the first and second light-shielding bands are formed by using a negative resist and scanning exposure. Is desirable.

Scanning exposure using a negative resist is effective for forming a fine pattern. According to this resist, the area of the light-shielding portion, that is, the area of the non-etched portion can be suppressed, so that the exposure time when a pattern is formed on the reticle using scanning exposure or the like can be shortened.

The product chip pattern includes a plurality of patterns corresponding to the product chips arranged in a matrix in a row direction and a column direction, and the first test pattern includes one side of the product chip pattern in a row direction. A pattern for forming a test circuit corresponding to a part of the plurality of patterns arranged along
The second test pattern includes a pattern for forming a test circuit corresponding to a part of the plurality of patterns arranged along the other side in the row direction of the product chip pattern. You may.

Further, the product chip pattern includes an odd number of patterns corresponding to the product chips arranged in a row direction, and the first and second test patterns are arranged at least in the center of the odd number of patterns. It is preferable that a pattern for forming the test circuit is provided corresponding to the pattern arranged in the section.

The frame may be formed with a constant width. Preferably, the product chip pattern, the first and second test patterns, the first and second light-shielding bands, and the frame have a shape in which four rectangular corners are cut as a whole.

In order to achieve the above object, a reticle according to a second aspect of the present invention includes a product chip pattern and a test element group chip pattern formed by using a negative resist and electron beam exposure. In the reticle comprising: a pattern of a product chip is arranged, a first region formed in a rectangle, and a pair of mutually opposed sides of the first region are arranged to be adjacent to each other; A pair of first light-blocking regions formed in a short band shape;
A pair of second regions formed from a pattern of test element group chips, which are adjacent to one light shielding region and formed to have substantially the same length as the length of the first light shielding region; A second light-shielding region surrounding a region formed by the first region, the second region, and the first light-shielding region, and including a protrusion corresponding to the outer shape of the second region and the first light-shielding region And the following.

Also with this reticle, the area of the light-shielding portion can be reduced as compared with a normal reticle having a pattern formed entirely in a rectangular shape. Therefore, as described above, the resolution of the semiconductor chip to be manufactured can be increased, and the manufacturing time of the reticle itself can be shortened.

The first region is arranged in a matrix in a row direction and a column direction and has a pattern of product chips.
The second region may include a pattern of the test element group chip corresponding to a part of patterns of the product chips arranged in a row direction.

The first region has an odd number of product chip patterns arranged in the row direction, and the second region has at least a central portion of the odd number of product chip patterns. It is preferable to provide a pattern of the test element group chip corresponding to the pattern arranged in the test element group chip.

Further, the first region, the second region, and the first region
Region formed from the light-shielding region and the second light-shielding region,
The whole may have a shape in which four corners of a rectangle are cut out.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A reticle according to an embodiment of the present invention will be described below with reference to the drawings.

The reticle 100 according to the present embodiment is used when a desired pattern is transferred onto a wafer substrate by a stepper, and transmits a part of light emitted to a predetermined area by a blind of the stepper. Expose a desired area of the wafer substrate.

As shown in the partial sectional view of FIG. 1A, the reticle 100 includes a transparent substrate 1 formed in a flat plate shape, a chromium film 2 formed on the transparent substrate 1, The phase shift film 4 is formed on the chromium film 2.

The transparent substrate 1 is made of, for example, synthetic quartz glass and transmits light for exposing the wafer substrate. The chromium film 2 is formed of chromium and blocks light for exposing the wafer substrate. The phase shift film 4 is formed of, for example, silicon dioxide, and reverses the phase of light for exposing the wafer substrate.

The pattern drawn on the reticle 100 is
As shown in a plan view in FIG. 1B, a product pattern 10 for forming product chip patterns 10 a to 10 f transferred onto a wafer substrate, and an electrical connection between a product chip manufactured using the reticle 100. T for evaluating characteristics, etc.
TEG patterns 20a, 2 for forming a pattern of an EG (Test Element Group) chip
0b, and light-shielding bands 30a, 30b and an outer frame 40 for preventing exposure of a portion other than the exposure target position due to a positioning error of a blind provided in the stepper, and is formed in a shape in which four rectangular corners are cut as a whole. ing.

The product pattern 10 includes product chip patterns 10a to 10f arranged in a matrix of 2 rows × 3 columns, and is formed in a rectangular shape as a whole. The patterns 10a to 10f of each product chip are formed by arranging a chromium film 2 and a phase shift film 4 on a transparent substrate 1, and are formed in a substantially rectangular shape.

The TEG patterns 20a and 20b are formed by disposing a chromium film 2 and a phase shift film 4 on a transparent substrate 1. The TEG patterns 20a and 20b are arranged adjacent to the light-shielding bands 30a and 30b along the sides of the product chip patterns 10b and 10e, respectively, and include sides having substantially the same length as the sides. It is formed in a rectangular shape.

The light-shielding bands 30a and 30b are formed by arranging a chromium film 2 on a transparent substrate 1.
0b, 10e and the TEG patterns 20a, 20b. The light-shielding bands 30a and 30b prevent the TEG patterns 20a and 20b from being exposed when exposing the product chip patterns 10a to 10f on the wafer substrate due to a positioning error of a blind provided in the stepper. TEG patterns 20a, 2 on the substrate
0b is exposed when the patterns 10a to 10
f is prevented from being exposed.

The outer frame 40 is formed by arranging the chromium film 2 on the transparent substrate 1. The outer frame 40 surrounds the product pattern 10, the TEG patterns 20a and 20b, and the light-shielding bands 30a and 30b with a certain width. A projection 40a protruding corresponding to the outer shape of the light-shielding band 30a, and a projection 40b protruding corresponding to the outer shape of the TEG pattern 20b and the light-shielding band 30b are provided. The outer frame 40 prevents light from being irradiated to a position other than the position of the exposure target on the wafer substrate due to a positioning error of a blind provided in the stepper.

As described above, the reticle 100
Product pattern 10 and TEG patterns 20a and 20b
, Light shielding bands 30a, 30b, and an outer frame 40, and are formed in a shape in which four rectangular corners are cut as a whole, and compared with the reticle 200 shown in FIG.
The exposure area at the time of producing the reticle can be reduced because the reticle is not provided. Therefore, it is possible to reduce the time required for the exposure processing when creating the reticle. Also, T
Since the EG patterns 20a and 20b are arranged along the center of the product pattern 10, it is possible to suppress a decrease in accuracy of the exposure position when exposing the wafer substrate.

Next, a method of manufacturing the reticle 100 will be described with reference to the drawings.

As shown in the partial sectional view of FIG. 2A, a chromium film 2 is formed on one main surface of a transparent substrate 1 made of, for example, synthetic quartz glass by sputtering or the like.

As shown in the partial sectional view of FIG. 2B, for example, a negative resist film 3 is formed on the chromium film 2 by spin coating or the like, and the resist film 3 is formed by using an electron beam exposure apparatus or the like. Is exposed to light to form a desired pattern on the resist film 3.
Transfer to the top.

The unexposed portion of the resist film 3 is removed by a developing solution, and the resist film 3 remaining on the chromium film 2 is used as an etching mask as shown in the sectional view of FIG.
The chromium film 2 is etched to form a desired pattern on the transparent substrate 1.

The resist film 3 is peeled off from the chromium film 2,
It is checked whether or not the formed pattern has a defect. If the pattern has a defect that can be corrected, the defect is corrected.

As shown in FIG. 2D, for example, a phase shift film 4 made of silicon dioxide grown by chemical vapor deposition
Is formed on the transparent substrate 1 and the chromium film 2, and FIG.
As shown in FIG. 3, the negative resist film 5 is
Then, the resist film 5 is exposed to light, a desired shifter pattern is transferred to the resist film 5, and developed.

The phase shift film 4 is etched, and FIG.
As shown in (f), the resist film 5 is peeled off from the phase shift film 4 and the formed pattern is inspected and corrected, and a desired pattern formed from the phase shift film 4 and the chromium film 2 is formed. The transparent substrate 1 is washed.

In the above method, a 64 megabit DRAM
(Dynamic Random Access Me
When a reticle for exposing a reticle is exposed, a conventional reticle requires a manufacturing time of approximately 8 hours. However, according to the reticle 100, the manufacturing time is about 20% shorter than that of the conventional reticle. It is possible to

Further, since the exposure area at the time of producing the reticle is reduced, it is possible to reduce the probability that the exposure processing is performed in a state where the foreign matter adheres to the resist film, as compared with the conventional reticle. The occurrence of pattern defects due to the displacement can be reduced.

Next, an exposure process for a wafer substrate using the reticle 100 will be described.

The pattern of the reticle 100 is
As shown in FIG. 3, the stepper 50 for transferring the light to the reticle 100 irradiates a part of the light of the light source 51 with a blind 53 a to 53 d to a desired area of the reticle 100.
The light transmitted through the wafer substrate 60
Then, the operation of sliding the wafer stage 57 and irradiating light to other regions of the wafer substrate 60 is repeated, and the wafer substrate 60 is exposed.

For example, product chip patterns 10a-1
0f to the wafer substrate 60, the stepper 50
First, as shown in FIG.
The blinds 53a to 53d are arranged above the area other than the area to prevent the area from being irradiated with light.

The stepper 50 irradiates the product pattern 10 with light, and transmits the light transmitted through the product pattern 10 to the reduction lens 5.
Irradiate the wafer substrate 60 via 5, transfer the product chip patterns 10 a to 10 f onto the wafer substrate 60, and adjust the position of the wafer stage 57 so that the next target position on the wafer substrate 60 is irradiated with light. .

When transferring the TEG pattern 20a to the wafer substrate 60, the stepper 50 arranges blinds 53a to 53d above the region other than the TEG pattern 20a as shown in FIG. Prevents light irradiation. On the other hand, when transferring the TEG pattern 20b to the wafer substrate 60, the stepper 50 arranges the blinds 53a to 53d above the region other than the TEG pattern 20b as shown in FIG. Prevent irradiation.

The stepper 50 includes a TEG pattern 20a,
The wafer 20b is irradiated with light, and the light transmitted through the TEG patterns 20a and 20b is irradiated on the wafer substrate 60 via the reduction lens 55 to transfer the TEG patterns 20a and 20b to predetermined positions on the wafer substrate 60.

The above-described operation is repeated by the stepper 50 in a predetermined order to form a desired pattern on the wafer substrate 60.

When exposing the TEG patterns 20a and 20b to the wafer substrate 60 using the reticle 100, light from the light source 51 is shielded by the blinds 53a to 53d, so that light is irradiated around the TEG patterns 20a and 20b. Not done.

In the conventional reticle, since the light from the light source 51 is reflected by the chrome film 2 forming the light-shielding portion, the pattern resolution may be reduced by the re-reflected light. TE with pattern formed
During the exposure of the G patterns 20a and 20b, the re-reflected light from the chromium film 2 can be reduced, and the resolution of the pattern formed on the wafer substrate can be increased.

The positions at which the TEG patterns 20a and 20b are provided are arbitrary. For example, as shown in FIG. 5A, the TEG patterns 20a and 20b sandwich the product chip patterns 10a and 10d. A configuration may be adopted. Even with this configuration, it is possible to reduce the manufacturing time of the reticle 100 by almost 20% as compared with the conventional reticle.

Further, as shown in FIG. 5 (b), a structure in which a region formed from product chip patterns 10d to 10f arranged in the row direction is sandwiched between a TEG pattern 20a and a TEG pattern 20b may be employed. Good. According to this configuration, it is possible to reduce the manufacturing time of the reticle 100 by almost 10% as compared with the conventional reticle.

Furthermore, the number of TEG chips is also arbitrary. For example, as shown in FIG. 5C, the product chip patterns 10a and 10d are sandwiched between TEG patterns 21 and 23, and the product chip patterns 10b and 10d and TE
A configuration arranged between the G patterns 22 and 24 may be adopted. According to this configuration, it is possible to reduce the manufacturing time of the reticle 100 by almost 10% as compared with the conventional reticle.

The material of the transparent substrate 1 is arbitrary as long as it transmits light in the exposure step when manufacturing the wafer substrate 60. For example, the transparent substrate 1 may be formed of nitrocellulose.

The number and arrangement of the patterns of the product chips provided on the product pattern 10 are arbitrary.
As shown in FIG. 7, the pattern may be composed of nine product chip patterns 101 to 109 arranged in a matrix of 3 rows × 3 columns.

[0057]

As described above, according to the present invention,
The working efficiency of reticle manufacturing can be increased, and a highly reliable semiconductor chip can be manufactured.

[Brief description of the drawings]

FIG. 1A is a partial cross-sectional view of a reticle according to an embodiment of the present invention. FIG. 2B is a plan view of the reticle of FIG.

FIGS. 2A to 2F are partial cross-sectional views of the reticle in each step of manufacturing the reticle of FIG.

FIG. 3 is a side view of the stepper in a state where a pattern formed on the reticle of FIG. 1 is transferred to a wafer substrate.

4A is a schematic view showing a blind provided in a stepper in a state where a product pattern formed on a reticle of FIG. 1 is transferred to a wafer substrate. (B), (c) is a schematic diagram showing a blind provided in a stepper in a state where a TEG pattern formed on the reticle of FIG. 1 is transferred to a wafer substrate.

FIGS. 5A, 5B, and 5C are plan views of modified examples of the reticle according to the embodiment of the present invention.

FIG. 6 is a plan view of a modification of the reticle according to the embodiment of the present invention.

FIG. 7 is a plan view of a conventional reticle.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 transparent substrate 2 chromium film 3 resist film 4 phase shift film 5 resist film 10 product pattern area 10 a to 10 f product chip pattern 20 a, 20 b TEG pattern 21 to 25 TEG pattern 25 a, 25 b light shielding unit 30 a, 30 b light shielding band 40 outer frame 40a, 40b Projection 50 Stepper 53a-53d Blind 60 Wafer substrate 100 Reticle 101-109 Product pattern 200 Reticle

[Procedure amendment]

[Submission date] November 1, 1999 (1999.11.
1)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Name of invention

[Correction method] Change

[Correction contents]

Patent application title: Reticle and method for producing reticle

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] Claims

[Correction method] Change

[Correction contents]

[Claims]

[Procedure amendment 3]

[Document name to be amended] Statement

[Correction target item name] 0001

[Correction method] Change

[Correction contents]

[0001]

TECHNICAL FIELD The present invention relates to a reticle and a reticle.
More particularly, the present invention relates to a reticle having a pattern formed by exposing a negative resist by scanning exposure and a method of manufacturing a reticle .

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0011

[Correction method] Change

[Correction contents]

[0011]

In order to achieve the above object, a reticle according to a first aspect of the present invention is formed on a light-transmitting substrate and a rectangular shape as a whole on the substrate.
A product chip pattern for forming a plurality of product chips, and a test circuit formed on the substrate along one side of the product chip pattern, the side corresponding to the one side being formed shorter than the one side a first test pattern of use, disposed in the product chip pattern on the substrate so as to shield between the <br/> the first test pattern, the first
A first light-shielding band formed to have substantially the same length as the test pattern, and surrounding the product chip pattern, the first light-shielding band, and the first test pattern on the substrate with a constant width.
And a light-shielding frame.

[Procedure amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0012

[Correction method] Change

[Correction contents]

The pattern formed on this reticle is manufactured by
Product chip pattern, first shading zone and first test pattern
Since the down frame is surrounded by a constant width, Ru is formed in a shape projecting in correspondence to the first light-shielding zone of the first test pattern. For this reason , the area of the light-shielding portion formed from the first light-shielding band or the frame can be reduced as compared with a normal case where the entire pattern is formed in a rectangular shape. Normally, the light shielding portion has a high light reflectance, and reflects exposure light when exposing a semiconductor wafer. In this reticle, since the area of the light shielding portion is small, the amount of reflected light is suppressed, and it is possible to prevent the resolution of the pattern transferred to the wafer substrate from being reduced by the reflected light. In addition, since the area of the light-shielding portion is reduced, the probability of exposure in a state in which a foreign substance adheres to the resist film during the production of the reticle can be reduced, and a decrease in the production yield of the reticle itself can be suppressed.

[Procedure amendment 6]

[Document name to be amended] Statement

[Correction target item name] 0013

[Correction method] Change

[Correction contents]

The reticle is disposed on the substrate,
A second test pattern for forming a test circuit, wherein the second test pattern is arranged along another side facing one side of the product chip pattern, and a side corresponding to the other side is formed shorter than the other side;
A second test pattern disposed on the substrate so as to shield light between the product chip pattern and the second test pattern, and formed to have substantially the same length as the second test pattern;
The frame may surround the pattern of the product chip, the first and second light-shielding bands, and the first and second test patterns with a constant width.

[Procedure amendment 7]

[Document name to be amended] Statement

[Correction target item name] 0018

[Correction method] Change

[Correction contents]

The pattern of the product chip and the first and second
It is preferable that the test pattern, the first and second light-shielding bands, and the frame have a shape in which four rectangular corners are cut as a whole.

[Procedure amendment 8]

[Document name to be amended] Statement

[Correction target item name] 0019

[Correction method] Change

[Correction contents]

In order to achieve the above object, a reticle according to a second aspect of the present invention includes a product chip pattern and a test element group chip pattern formed by using a negative resist and electron beam exposure. In the reticle comprising: a pattern of a product chip is arranged, a first region formed in a rectangle, and a pair of mutually opposed sides of the first region are arranged to be adjacent to each other; A pair of first light-blocking regions formed in a short band shape;
A pair of second regions formed from a pattern of test element group chips, which are adjacent to one light shielding region and formed to have substantially the same length as the length of the first light shielding region; A second light-shielding region surrounding a region formed by the first region, the second region, and the first light-shielding region with a constant width .

[Procedure amendment 9]

[Document name to be amended] Statement

[Correction target item name] 0023

[Correction method] Change

[Correction contents]

Further, the first region, the second region, and the first region
Region formed from the light-shielding region and the second light-shielding region,
The whole may have a shape in which four corners of a rectangle are cut out. To achieve the above object, the present invention relates to a third aspect of the present invention.
A reticle manufacturing method uses a light-shielding film formed on a light-transmitting substrate.
And forming a negative resist film on the light-shielding film.
Rectangular product chip pattern to form a number of product chips.
Along the turn and two opposite sides of the product chip pattern.
At least two test putters formed in a rectangular shape
Between the product chip pattern and the test pattern.
And the product chip pattern
A fixed width frame pattern surrounding the test pattern
With turns and four rectangular corners cut out as a whole
A shape pattern is drawn on the resist film by scanning exposure.
And removing the unexposed portions of the resist film,
Using the exposed portion where the residual film remains as a mask,
Pattern the optical film, remove the resist film,
Exposure pattern drawn on the resist film
The shape of the
Exposure area is smaller than when the whole is rectangular,
As a result, the time required for scanning exposure has been reduced.
I do. By the reticle produced by this method
Is a regular laser with a pattern that is entirely rectangular.
The area of the light-shielding portion can be reduced as compared with the tickle. Obedience
Therefore, as described above, the resolution of the semiconductor chip to be manufactured is
And reduce the manufacturing time of the reticle itself
be able to. The method of manufacturing the reticle may include:
After removing the film, the substrate and the patterned shield are removed.
A phase shift film is formed on the optical film, and the phase shift film is
You may turn.

[Procedure amendment 10]

[Document name to be amended] Statement

[Correction target item name] 0039

[Correction method] Change

[Correction contents]

As shown in FIG. 2D, for example, a phase shift film 4 made of silicon dioxide grown by chemical vapor deposition
Is formed on the transparent substrate 1 and the chromium film 2, and FIG.
As shown in FIG. 3, the negative resist film 5 is
The resist film 5 is exposed to light and a desired shift pattern is formed.
The pattern is transferred to the resist film 5 and developed.

Claims (11)

[Claims] A light-transmitting substrate; a product chip pattern formed on the substrate as a whole in a rectangular shape to form a plurality of product chips; and one side of the product chip pattern on the substrate. And a first test pattern for forming a test circuit, the side corresponding to the one side being formed shorter than the one side, and a light shielding path between the product chip pattern and the first test pattern. A first light-shielding band disposed on the substrate and formed to have substantially the same length as the first test pattern; and a product chip pattern, a first light-shielding band, and a first light-shielding band on the substrate. A light-shielding frame surrounding the first test pattern and having a first protrusion corresponding to the outer shape of the first test pattern. 2. A test circuit forming device, wherein the test circuit is arranged on the substrate and is arranged along another side facing one side of the product chip pattern, and the side corresponding to the other side is shorter than the other side. And a second test pattern, which is disposed on the substrate so as to shield light between the product chip pattern and the second test pattern, and is formed to have substantially the same length as the second test pattern. Wherein the frame surrounds the pattern of the product chip, first and second light-shielding bands, and first and second test patterns, and wherein the second light-shielding band is provided. 2. The apparatus according to claim 1, further comprising a second protrusion corresponding to an outer shape of the first test pattern and the second test pattern.
The reticle described in 1. 3. The product chip pattern and first and second product chip patterns.
3. The reticle according to claim 2, wherein the test pattern and the first and second light-shielding bands are formed using a negative resist and scanning exposure. 4. The product chip pattern includes a plurality of patterns corresponding to the product chips arranged in a matrix in a row direction and a column direction, and the first test pattern is arranged in a row direction of the product chip pattern. A pattern for forming a test circuit corresponding to a part of the plurality of patterns arranged along one side of the plurality of patterns, wherein the second test pattern is a row direction of the product chip pattern. 4. The reticle according to claim 2, further comprising a pattern for forming a test circuit corresponding to a part of the plurality of patterns arranged along the other side of the reticle. 5. 5. The product chip pattern includes an odd number of patterns corresponding to a product chip arranged in a row direction, and the first and second test patterns are at least a center of the odd number of patterns. The reticle according to any one of claims 2 to 4, further comprising a pattern for forming the test circuit corresponding to the pattern arranged in the unit. 6. The reticle according to claim 1, wherein the frame has a constant width. 7. The product chip pattern and first and second product chip patterns.
The reticle according to any one of claims 2 to 5, wherein the test pattern, the first and second light-shielding bands, and the frame have a shape in which four corners of a rectangle are cut as a whole. 8. A reticle having a pattern of a product chip and a pattern of a test element group chip formed by using a negative resist and electron beam exposure, wherein the pattern of the product chip is arranged and formed into a rectangle. A first region, a pair of first light-shielding regions arranged adjacent to a pair of mutually opposed sides of the first region, and formed in a band shape shorter than the pair of sides; A pair of second regions formed from a pattern of test element group chips, which are adjacent to one light-shielding region and have substantially the same length as the length of the first light-shielding region; A second light-shielding region surrounding a region formed by the first region, the second region, and the first light-shielding region, and including a protrusion corresponding to the outer shape of the second region and the first light-shielding region And comprising Reticle. 9. The first area includes a pattern of product chips arranged in a matrix in a row direction and a column direction, and the second area includes a pattern of the product chips arranged in a row direction. 9. The reticle according to claim 8, comprising a pattern of the test element group chip corresponding to a part of the patterns. 10. The first area includes an odd number of product chip patterns arranged in a row direction, and the second area includes at least a central portion of the odd number of product chip patterns. 10. The reticle according to claim 9, comprising a pattern of the test element group chip corresponding to the pattern arranged in the reticle. 11. A region formed by the first region, the second region, the first light-shielding region, and the second light-shielding region has a shape in which four rectangular corners are cut as a whole. The reticle according to any one of claims 8 to 10, wherein