JP2000152508A - Storage with capacitor initializing function - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the current capacity of a bypass circuit in a capacitor and loss of initialization. SOLUTION: This storage is provided with a voltage detecting means 3 detecting full charge voltage Vful of respective capacitors Cs, an initialization selecting means Init selecting an initialization mode, bypass means 4, Tr, R which compare the terminal voltages of the respective capacitors Cs with reference voltage Vini equal to or less than the full charge voltage on condition that the initialization mode is selected by the initialization selecting means Init, and bypasses the part of charging current when the terminal voltage exceeds a reference voltage Vini, and charging control means 1, 2 which charge the capacitors Cs connected in series and stop charging on the condition that the full charging voltage Vful is detected from either of the capacitors Cs by the voltage detecting means 3, and formed so that a plurality of capacitors Cs may be connected in series.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a capacitor power storage device in which a plurality of capacitors are connected in series to form a power storage device.

[0002]

2. Description of the Related Art FIG. 8 is a diagram showing a circuit configuration of a parallel monitor.
FIG. 9 is a diagram for explaining a charge / discharge waveform with a parallel monitor and an operation without a parallel monitor. In the figure, C is an electric double layer capacitor, CMP is a comparator, D is a diode, T
r indicates a transistor, and Vr indicates a reference voltage.

An indispensable condition when a power storage device is configured by combining a plurality of large-capacity capacitors is a problem of equalization of burden voltage that occurs when capacitors are connected in series. The present inventors have proposed a power storage device called an ECS (Energy Capacitor System) using an electric double layer capacitor (for example, electronic technology, 1994-12, p1).
~ 3, Denki Kagaku B, Vol. 115, No. 5, 1995, p. 504
610). In the ECS, a parallel monitor as a voltage monitoring and control device is connected to individual capacitors connected in series so that the maximum charge can be performed within the withstand voltage range of the capacitors.

In the parallel monitor, as shown in FIG. 8, the voltage of the capacitor C is changed by a comparator CMP to a reference voltage Vr.
Is monitored by comparing with the reference voltage Vr.
Exceeds the set value, the transistor Tr is turned on to bypass the charging current. By this operation, the charging voltage of the capacitor C is maintained at the set value as shown in FIG. 9, and the constant voltage is relaxed until another capacitor connected in series reaches full charge and shifts to the next discharge. The charging mode is set. As described above, in the ECS, the method of suppressing the charging voltage to the upper limit in the following point, that is, initializing (clamping) the voltage of the capacitor at the upper limit, and performing charging and discharging from the starting point, allows the voltage distribution of the capacitor to be equal to the individual capacitance. This solves the problem that the variation is shown in the circle in FIG. 9 and that the individual burden voltages of the capacitors become non-uniform due to the voltage difference at the start of charging.

[0005]

However, since the above-mentioned structure can be realized simply and inexpensively and the operation is reliable, it has played a large role in the practical use of ECS. The problem is that the charging energy during the period when the parallel monitor is on becomes heat. That is, in the parallel monitor shown in FIG. 8, when the set voltage is reached, the transistor Tr is operated to form a bypass circuit, and the voltage is prevented from rising any more. Therefore, a loss corresponding to the charging current × the full charging voltage occurs in the bypass circuit, and heat is generated.

In the case of a secondary battery, heat is generated every time a charge / discharge cycle occurs. However, in a capacitor, heat is generated only once at first, and thereafter, the set value of full charge, As shown in the figure, starting from a potential, the battery is discharged downward, and when it is charged, it has the characteristic that it returns to the original potential. Due to this feature, the parallel monitor operates only by absorbing slight fluctuations in characteristics during use and deviations due to leakage current, except during initialization, so it generates less heat and exhibits sufficient practical effects Has been found in various practical examples.

[0007] In addition, a method has been considered in which the comparator and the transistor of the parallel monitor are replaced with a switching converter so that power is not consumed, or initialization is performed at a low level to make the full charge level uniform. However, in the former method, the number of coils and transformers is required as many as the number of capacitors, and the method is complicated and the cost is high. Therefore, there is a problem that the power transmission efficiency and the amount of power saving cannot be met. In the latter method, the initialization time is estimated by estimating the time to reach full charge.Therefore, if the level is reduced and the initialization power is reduced, the accuracy of the adjustment will deteriorate, while the accuracy of the adjustment will increase. There is a problem that if the level is increased, the initialization power becomes large.

[0008]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and aims to reduce the current capacity of a bypass circuit of a capacitor and the initialization loss.

Therefore, the present invention provides a capacitor power storage device comprising a plurality of capacitors connected in series to form a power storage device, voltage detecting means for detecting a full charge voltage of each of the capacitors, and initialization for selecting an initialization mode. Selecting means for comparing the terminal voltage of each capacitor with a reference voltage equal to or less than the full charge voltage, on condition that the initialization mode is selected by the initialization selection means, and when the charge current exceeds the reference voltage, Bypass means for partially bypassing, and charge control means for charging the series-connected capacitors and stopping charging on condition that a full charge voltage is detected from any of the capacitors by the voltage detection means. It is characterized by having.

[0010] The initialization selecting means may be arranged on condition that the sum of the terminal voltages of the respective capacitors at the time when the charging control means stops charging has reached a set value or has increased by a certain value or more. Deselect the initialization mode on the condition that the initialization mode is selected and a certain time has elapsed,
The initialization mode is selected on condition that the sum of the terminal voltages of the capacitors when the charging control unit stops charging is equal to or less than a set value, and the second set value exceeding the set value is reached. , The selection of the initialization mode is released.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram illustrating an embodiment of a power storage device with a capacitor initialization function according to the present invention, and FIG. 2 is a diagram illustrating an example of a charge / discharge curve of the power storage device with a capacitor initialization function according to the present invention. In the figure, 1 is a charging device, 2
The gate, 3 and 4 comparators, C _A, C _B, ...
.. Indicates a capacitor, D indicates a diode, R indicates a resistor, Tr indicates a transistor, Init indicates an initialization switch, and Vful and Vini indicate reference voltages.

In FIG. 1, capacitors C _A , C _B ,.
Are electric double layer capacitors connected in series to constitute a power storage device. The initialization switch Init is turned on when the initialization mode is selected, and turns on / off the initialization operation of the capacitor. The transistor Tr and the resistor R constitute a charging current bypass circuit when the terminal voltage of the capacitor becomes equal to or higher than the reference voltage Vini during the initialization of the capacitor, and limit the bypass current, that is, a part of the charging current. The resistor R bypasses the current and sets the current. The comparator 3 detects the full charge of the capacitor by comparing with the reference voltage Vful.
This is an initialization comparator that turns on the transistor Tr when the terminal voltage of the capacitor becomes larger than ini, and partially bypasses the charging current. Charging device 1
Charge the capacitors C _A , C _B ,... Connected in series, and charge the battery on the condition that a full charge voltage is detected from any of the capacitors C _A , C _B ,. Stop. The OR gate 2 performs a logical OR operation on the full charge detection signal F of the comparator 3 connected in parallel to each capacitor, and outputs a constant current charging stop signal S to the charging device 1.

Therefore, the reference voltage Vful is set to the full charge voltage of the capacitor, and the reference voltage Vini is set to a voltage lower than the reference voltage Vful. In the charging when the initialization switch Init is ON, a part of the charging current is bypassed by the bypass circuit including the transistor Tr and the resistor R sequentially from the capacitor charged to the reference voltage Vini earlier, and the charging speed is reduced. When the capacitor is fully charged, the charging device 1 stops charging with a constant current, and performs relaxing charging as necessary. The operation at the time of charging and discharging will be described below with reference to FIG.

When the capacitors C _A , C _B ,... Start charging with a constant current (constant current charging) from a state in which the capacitors C _A , C _B ,. When the charging switch Init is off, the charging current bias circuit does not operate.
The voltage rises at a slope corresponding to the difference in capacitance, as indicated by A and B shown at the left end of FIG. When one of the series-connected capacitors C _A , C _B ,..., For example, the smaller capacitor C _A reaches the reference voltage Vful at t1, the full charge detection signal F of the comparator 3 changes to “ H ”, the output signal S of the OR gate 2 becomes“ H ”and the charging device 1
Stops the constant current charging. In this state, when the terminal voltage of the capacitor A falls below the reference voltage Vful due to self-charging or self-discharging inside the capacitor, the signals F and S
Becomes "L" and the charging is started again, so that the state of the relaxed charging maintained at the constant voltage continues after t1.

Next, the next charge cycle is started at time t3 by using the electric power discharged at time t2 and stored in the capacitors C _A , C _B ,... At this time, the switch Init is turned on until the terminal voltage of any one of the capacitors reaches the reference voltage Vful (full charge) from the time t3 at which the initialization mode is selected and charging starts, and the stop signal S becomes "H". The period is defined as an initialization period. In the initialization Periodo, the terminal voltage of the capacitor rises progressed charged, first, the bypass circuit of the capacitor C _A at t4 when the terminal voltage of the capacitor C _A reaches the reference voltage Vini is turned on, further delayed capacitor at t5 bypass circuit C _B also turned on.

When the bypass circuits are turned on, the rise in the terminal voltage of the capacitor is delayed by the current flowing through them.
If the resistance R inserted and connected in series with the transistor Tr is zero, the terminal voltage cannot rise above the reference voltage Vini. Here, the value of the resistance R is selected so that the charging current is half bypassed, for example. By halving the speed, the terminal voltage continues to rise.

[0017] and thus the capacitor C _A has reached the reference voltage Vini at t4, the delayed capacitor C reaches the reference voltage Vini at t5 and _B, the time that operation of the bypass circuit, i.e. the quantity of electricity is bypassed Is the capacitor C _A
Is larger. As a result, when the voltages at t1 and t6 are compared, it is apparent that the capacitor C, which was low until then,
Becomes closer to the terminal voltage of the capacitor C _A full terminal voltage during charging (charging stop) of _B is increased.

This method involves two design conditions. The first is the interval between the reference voltages Vful and Vini. Since the reference voltage Vful is determined by the withstand voltage (full charge voltage) of the capacitor, it may be called the value of Vini. When the value of the reference voltage Vini is increased, the time during which the bypass circuit of the capacitor is on is short, so that the amount of compensation for displacement per charge is reduced. Conversely, when the value of the reference voltage Vini is reduced, the time during which the bypass circuit of the capacitor is on is extended, so that the amount of averaging the capacitor voltage even with the same bypass current increases. However, when the value of the reference voltage Vini is reduced, the amount of power bypassed by the capacitor increases, so that the heat generated in the bypass circuit increases, and the initialization loss increases.

The second condition is a bypass current value, that is, a ratio of bypassing the charging current. When the value of the reference voltage Vini is increased and the bypass current is increased, a large amount of bypass current flows only near the top of the charging curve, and the time for bypassing the charging current is shortened. Since the value increases in proportion to the square, the initialization loss increases, and the bypass circuit needs to be designed to withstand the current value.

Therefore, the interval between the reference voltages Vful and Vini and the value of the bypass current are determined by, for example, how much the time for operating the bypass circuit is limited according to the variation of the capacitor and the degree of heat generation. Of course can be arbitrarily set in consideration of the time and the number of times of charging for canceling. Also, the conditions for selecting the initialization mode (starting the initialization) and canceling (stopping the initialization) can be arbitrarily set.

The activation of the initialization is performed, for example, when the condition for performing the initialization is satisfied (initialization execution condition), when the total voltage Vout of the capacitor at the end of charging is lower than the reference value Vro (necessary initialization condition), and the like. It is. The initialization execution conditions are, for example, in the case of a hybrid electric vehicle, before starting to run, that is, at the start of operation, and, in the case of power storage, in the summer before the peak of the afternoon, that is, in the morning, etc. Set based on prediction.

The stop of the initialization is performed, for example, when the condition is that the initialization should be stopped (initialization stop condition), when the initialization has been performed (the initialization end condition), and the like. For example, in the case of a hybrid electric vehicle, the initialization stop condition is set based on a request according to a use, such as during regenerative braking, and driving prediction.
The initialization end condition is, for example, when a predetermined time has elapsed since the start of the initialization, when the total voltage Vout of each capacitor has increased by a certain value since the start of the initialization, and when the total voltage Vout of each capacitor has reached a predetermined value. When the temperature reaches the temperature, when the temperature of the heatsink of the parallel monitor rises. By properly using these conditions, it is possible to prevent the initialization operation from continuing for a long time without stopping charging.

Next, the operation of selecting / releasing the initialization mode will be described. FIG. 3 is a diagram showing an example of a circuit for selecting / releasing the initialization mode, FIG. 4 is a diagram showing an example of a circuit for generating an initialization mode release signal, and FIG. 5 is a diagram showing that the initialization mode is released during charging. FIG. 7 is a diagram for explaining an example of the operation performed. In the figure, reference numerals 11 and 16 denote sample and hold circuits, 12 and 19 denote comparators, 13 and 15 denote OR gates, 14 denotes an initialization selection / cancellation circuit, 17 denotes a subtraction circuit, and 18 denotes an addition circuit.

In FIG. 3, the sample and hold circuit 11
Is to sample and hold the total voltage Vout of each capacitor by using the charging stop signal S as a trigger, and the comparator 12 compares the total voltage Vout of each sampled and held capacitor with a reference value Vro. The OR gate 13 receives the initialization command issued based on the initialization execution condition or the total voltage Vout of each capacitor as the reference value Vout.
The initialization selection signal is output by the output signal of the OR gate 13 when the value is lower than ro. The initialization selection / cancellation circuit 14 selects the initialization mode by the initialization selection signal that is the output signal of the OR gate 13, that is, Initialization switch
Init is turned on, and the initialization mode is released by an initialization release signal generated based on the initialization stop condition or the initialization end condition, that is, the initialization switch Init is turned off.

As an example of a circuit for generating an initialization release signal based on an initialization end condition, an example of a circuit is shown on the condition that the total voltage Vout of each capacitor rises by a certain value after the start of initialization. Is shown in FIG. In the circuit shown in FIG. 4, the OR gate 15 outputs an initialization start signal when one of the initialization comparators 4 of each capacitor starts operating, and the sample and hold circuit 16 outputs the signal at the time of the start of the initialization. Total voltage Vou of each capacitor
Sample and hold t. Then, the difference between the total voltage Vout of each capacitor at the start of initialization and the voltage Vout × n when each capacitor is assumed to be the reference voltage Vini is obtained by the subtraction circuit 17, and the difference is calculated by the addition circuit 18. The total voltage Vout of each capacitor at the start of initialization is added. The addition circuit 18 is provided by the comparator 19.
When the total voltage Vout of each capacitor rises after the start of the initialization up to the added value of, an initialization release signal is output.

As described above, when the voltage rise value for generating the initialization release signal is determined according to the total voltage Vout of each capacitor at the start of the initialization, when the voltage variation is large as shown in FIG. The time during which the initialization operation is continued from the start of the initialization to the point P at which the initialization release signal is generated becomes longer. However, by repeating such initialization, as shown in FIG. 5, when the variation in voltage becomes smaller, the time for which the initialization operation continues until the point P at which the initial release signal occurs is shortened. Become. That is, the duration of the initialization operation can be automatically adjusted according to the voltage fluctuation. In this case, when the bypass current is changed, the voltage rising gradient after the initialization operation changes, so that the time changes according to the change in the gradient.

Even if the state is not completely initialized at one time as described above, a special initialization cycle and time are prepared by performing initialization while using it little by little over many cycles. It is not necessary, and for example, in the case of a hybrid electric vehicle, the initialization can be performed without the driver's notice. Originally, variations in capacitors gradually occur over a long period of time due to individual differences in leakage current and the like.Therefore, depending on the application, the slow method as described above is sufficient for initialization to correct it. Yes, but rather a reasonable approach.

In FIG. 4, the same applies when the comparator 19 is omitted, a timer is used in place of the adder circuit 18, a time is set according to the output of the subtractor circuit 17, and an initialization release signal is generated when the time is over. In addition, the duration of the initialization operation can be automatically adjusted according to the voltage variation. In FIG. 4, the subtraction circuit 1
7 can be omitted, and a constant value can be added to the total voltage Vout of each capacitor at the start of initialization, which is sampled and held in the sample-and-hold circuit 16 by the addition circuit 18, to make the rising voltage until the initialization release signal is generated constant. Similarly, the duration of the initialization operation can be kept constant.

FIG. 6 is a diagram showing an example of a configuration of a bypass circuit for bypassing a constant current, and FIG. 7 is a diagram showing an example of a circuit for detecting full charge. In the figure, Tr indicates a transistor, Rs indicates a current limiting resistor, Z indicates a reference voltage source, and 22 indicates a voltage monitoring device.

FIG. 1 shows a configuration in which a resistor R is inserted in series with a transistor Tr to limit a bypass current as a bypass circuit, but the configuration for limiting a bypass current is not limited to this. It goes without saying that a circuit can be adopted. FIG. 6 shows an example of this. As is well known as a constant current circuit, a current limiting resistor Rs is connected in series to an emitter of a transistor Tr, and a base and an emitter of the transistor Tr are connected to a current source. The zener diode Z is connected in parallel to a series circuit with the limiting resistor Rs. According to this circuit, the transistor Tr is controlled so that the voltage drop in the current limiting resistor Rs becomes the voltage of the reference voltage source Z, that is, the transistor Tr becomes a constant current. The current limiting resistor Rs is
Since it is used for detecting a current, the resistance R shown in FIG.
A resistor having a value much smaller than that of the resistor may be used. Although the figure shows a simple circuit to explain the principle of operation, when the bypass current to be handled is large, a low-loss sensor such as a current detection Hall element is used instead of the current limiting resistor Rs, and the control is also performed. The signals may be amplified, compared, and logically determined using an integrated circuit or a microcomputer.

FIG. 1 shows an example in which a reference voltage and a comparator are used as means for detecting the full charge of each cell. However, this is one example, and for example, the voltage monitoring device 2 shown in FIG.
2. Needless to say, any other known method can be used. The voltage monitoring device 22 shown in FIG. 7 is an arithmetic unit that collects voltages at the connection points of a large number of capacitors C1 to Cn connected in series and includes a comparator and an ADC (analog-to-digital converter). The voltage of Cn can be sequentially read. For this operation, for example, a microprocessor can be used, and the charging time of a normal large-sized capacitor is several tens of seconds or more. Therefore, the terminal voltages of many capacitors are read with a simple device, and further failure occurs. In such a case, control such as short-circuiting can be performed.

The present invention is not limited to the above embodiment, but can be variously modified. When some of a large number of capacitors fail, there is a method of short-circuiting the capacitors and continuing the operation as a whole system, but the method can be applied simultaneously with the parallel monitor of the present invention. It is. In the present invention, since neither the comparator nor the transistor is used except for a specific time during charging, the comparator and the transistor may be used for short-circuiting the deteriorated capacitor as necessary.
The selection of the initialization mode may be performed in combination with the fuel gauge and determined based on the remaining capacity at the time of stopping charging, or may be performed periodically.

[0033]

As is apparent from the above description, according to the present invention, in a capacitor power storage device comprising a plurality of capacitors connected in series to constitute a power storage device, voltage detecting means for detecting a charging voltage of each of the capacitors. And bypass means connected in parallel to each of the capacitors to bypass a charging current, and charge control means for charging the series-connected capacitors, wherein the bypass means is selected by selecting an initialization mode. When the terminal voltage of the capacitor is compared with a reference voltage and exceeds the reference voltage, a part of the charging current is bypassed, and the charge control means detects full charge from the terminal voltage of one of the capacitors by the voltage detection means. Charging until it is done, so there is no initialization cycle,
Initialization can be performed while repeating charge and discharge. Therefore, the present invention is also effective in the case where there is a restriction on the use situation such that there is no time to initialize the capacitor before starting. In addition, initialization can be performed little by little in a number of charging cycles instead of a single charging cycle, that is, the capacitor voltage distribution can be averaged. Furthermore, since the current flowing through the bypass circuit is limited, the bypass circuit does not need to have a current capacity up to the maximum charging current, and the current capacity of the bypass circuit can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram showing an embodiment of a power storage device with a capacitor initialization function according to the present invention.

FIG. 2 is a diagram illustrating an example of a charge / discharge curve of a power storage device with a capacitor initialization function according to the present invention.

FIG. 3 is a diagram showing an example of a circuit for selecting / releasing an initialization mode.

FIG. 4 is a diagram illustrating an example of a circuit that generates a reset signal for an initialization mode.

FIG. 5 is a diagram illustrating an example of an operation in which an initialization mode is canceled during charging.

FIG. 6 is a diagram illustrating a configuration example of a bypass circuit that bypasses a constant current.

FIG. 7 is a diagram illustrating an example of a circuit that detects full charge.

FIG. 8 is a diagram showing a circuit configuration of a parallel monitor.

FIG. 9 is a diagram for explaining a charge / discharge waveform with a parallel monitor and an operation without a parallel monitor.

[Explanation of symbols]

1 ... charger, 2 ... OR gate, 3,4 ... comparator, C _A, C _B, ......... capacitors, D ... Diode,
R: resistance, Tr: transistor, Init: initialization switch, Vr1, Vr2: reference voltage

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Dio Okamura 2-19-6 Minamiota, Minami-ku, Yokohama, Kanagawa Prefecture (72) Inventor Masahiko Shinozuka 1-1-1, Fukuura, Kanazawa-ku, Yokohama-shi, Kanagawa Co., Ltd. F-term in power system (reference) 5G003 AA01 BA03 CA02 CA14 CC02 CC04 DA04 DA12 FA06

Claims (6)

[Claims] 1. A capacitor power storage device comprising a plurality of capacitors connected in series to form a power storage device, a voltage detection means for detecting a full charge voltage of each of the capacitors, an initialization selection means for selecting an initialization mode, The terminal voltage of each of the capacitors is compared with a reference voltage equal to or less than the full charge voltage on condition that the initialization mode is selected by the initialization selection means, and when the voltage exceeds the reference voltage, a part of the charging current is bypassed. And charge control means for charging the series-connected capacitors and stopping charging on condition that a full charge voltage is detected from any of the capacitors by the voltage detection means. A power storage device having a capacitor initialization function. 2. The initialization selecting means cancels the selection of the initialization mode on condition that the sum of the terminal voltages of the capacitors reaches a set value when the charging control means stops charging. The power storage device with a capacitor initialization function according to claim 1. 3. The initialization selection means, on condition that the sum of terminal voltages of the capacitors has risen by a certain value or more when the charging control means stops charging after the initialization mode is selected. The power storage device with a capacitor initialization function according to claim 1, wherein the selection of the initialization mode is canceled. 4. The capacitor initialization function according to claim 1, wherein the initialization selection means cancels the selection of the initialization mode on condition that the initialization mode has been selected and a predetermined time has elapsed. Power storage device. 5. The initialization selection means selects an initialization mode on condition that the sum of the terminal voltages of the respective capacitors when the charge control means stops charging has become equal to or less than a set value. The power storage device with a capacitor initialization function according to claim 1. 6. The initialization selection means initializes on condition that the sum of the terminal voltages of the respective capacitors when the charge control means stops charging reaches a second set value exceeding the set value. The power storage device with a capacitor initialization function according to claim 2, wherein the mode selection is canceled.