JP2000152082A - Image sensor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image sensor which can read out frame information at a high speed and can use a low-speed and small-area A/D converter in the case of the same read time as conventional one. SOLUTION: An address decoder 2 controls a row scan shift register 3 based on an address AD and causes a row driver 6 to activate a row to read out the signal of the row to noise control circuits 27A and 27B. An A/D converter 28A converts the signal stored in the noise control circuit 27A to a digital signal and successively sends it to an output OUT under the control of a column scan shift register 24A, and an A/D converter 28B converts the signal stored in the noise control circuit 27B to a digital signal. Thereafter, the A/D converter 28B successively outputs the digital signal under the control of a column scan shift register 24B after read of the signal of the row signal to noise control circuits 27A and 27B, and the A/D converter 28A converts the signal of the next row to a digital signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an image sensor used as an image sensor in a portable device such as a digital camera.

[0002]

2. Description of the Related Art A MOS (Metal Oxide Semiconductor) image sensor (hereinafter simply referred to as "image sensor") is a C-type image sensor.
Since it does not have a structure in which charges are transferred by a bucket brigade type using a multi-phase clock like a CD (charge-coupled device), the power consumption can be reduced to about 1/10 of that of a CCD. Attention has been paid to an imaging device suitable for a portable device such as a camera. In addition,
The image sensor operates on a single power supply, CMOS
(Complementary MOS) Compatibility with logic process, SOC (System On Chi
It has various features such as realizing p). On the other hand, the image sensor also has disadvantages such as a problem of noise and low sensitivity of the light receiving unit. However, recently, the development of a noise canceling method and the realization of intra-pixel amplification using a fine transistor have solved the above-mentioned disadvantages. In addition to this, various factors such as a growing need for SOC and the CCD market being monopolized by some companies have led to an increasing interest in image sensors as replacements for CCDs.

FIG. 10 shows a conventional M
3 shows a configuration example of an OS type image sensor. In the figure, a pixel array 1 corresponds to one frame of an imaging screen, and is a DRAM (Dynamic Random Access Memory).
As in the case of a general memory such as that described above, a large number of pixels are arranged in a matrix. Each pixel on the pixel array 1 performs a photoelectric conversion on the received light and outputs an analog signal having a voltage corresponding to the light intensity. The address AD is for designating any pixel on the pixel array 1, and is a row address for designating a word line in the row direction of the pixel array 1 and a row address for designating a bit line in the column direction. It consists of a column address. Each word line corresponds to one horizontal line (1H) signal on the imaging screen.

An address decoder 2 outputs a pulse for selecting one of a row and a column to a row scan shift register 3 and a column scan shift register 4 based on an address AD supplied from outside the image sensor. I do. The row scan shift register 3 captures a pulse supplied from the address decoder 2, supplies the pulse to the row driver 6 while shifting the pulse according to a clock signal transmitted from the clock control circuit 5, and outputs the pulse to any one of the rows on the pixel array 1. Select Similarly, the column scan shift register 4
Capture the pulse supplied from the address decoder 2,
This is supplied to an A / D (analog / digital) converter 8 described later while being shifted according to the clock signal sent from the clock control circuit 5. Thereby, A /
The A / D converter 8 selects any one of the analog signals generated by the D converter 8.

The clock control circuit 5 generates a clock signal to be supplied to each part of the address decoder 2, row scan shift register 3, and column scan shift register 4 according to a clock CLK supplied from outside the image sensor. The row driver 6 is a component of the row scan shift register 3 among a plurality of rows on the pixel array 1.
Driving any one row selected in. The noise control circuit 7 performs a noise canceling process on each of the plurality of analog signals read from the row driven by the row driver 6, and converts the processed analog signals into an analog signal.
Output to the D converter 8. The A / D converter 8 converts the analog signal for one row output from the noise control circuit 7 into a digital signal, and sends a digital signal corresponding to a column selected by the column scan shift register 4 to an output OUT. Thereby, for example, these digital signals are transferred to a main storage device of a computer (not shown). The digital signal obtained by converting the analog signal is, for example, 8-bit data (that is, 256 gradations). In FIG. 10, the pixel array 1 and the noise control circuit 7 are analog units, and each unit other than these two units is a digital unit.

On the other hand, FIG. 11 shows a simplified configuration of the pixel array 1 so as to be convenient for explaining the operation of the image sensor shown in FIG. The configuration is shown in more detail. In addition, in FIG. 11, the illustration of the noise control circuit 7 shown in FIG. 10 is omitted. In FIG. 11, the same components as those shown in FIG. 10 are denoted by the same reference numerals. Further, FIG. 11 shows only two word lines WL0 and WL1 as word lines in the row direction, and BL0 and BL1 as bit lines in the column direction.
Are only shown.

As shown in FIG. 11, a unit pixel which is a constituent unit of the pixel array 1 includes a photodiode for performing photoelectric conversion on light and outputting a voltage signal, and an amplifier circuit for amplifying a voltage signal output from the photodiode. It consists of a set. For example, a unit pixel selected by the bit line BL0 and the word line WL0 includes an amplifier circuit 10-00 and a photodiode 11-00. Similarly, the amplifier circuit 10-
01, 10-10, 10-11 and photodiode 11-01, 1
Units 1-10 and 11-11 form a unit pixel. In the following description, the amplifier circuit 10-0
The voltage values of the analog signals output from 0, 10-10, 10-01, and 10-11 are “D0”,
It is assumed that they are “D1”, “D2”, and “D3”.

Next, an ADC (A / D converter) 12-0,1
2-1 converts an analog signal read from the bit lines BL0 and BL1 into a digital signal having an 8-bit length, for example. The latches 13-0 to 13-1 capture the digital signals output from the ADC in accordance with a timing chart of a capture instruction signal (not shown) output from the clock control circuit 5. Further, the transfer switch 14-0 sends the digital signal held by the latch 13-0 from the buffer 15 to the output OUT at the timing of the switching signal YSW0 sent from the column scan shift register 4. Similarly, the transfer switch 14-1 outputs the switching signal YS sent from the column scan shift register 4.
Output the contents held in the latch 13-1 at the timing of W1
Send to T. The A / D converter 8 in FIG.
ADC 12-0.12-1 and latches 13-0, 1 shown in FIG.
3-1; transfer switches 14-0 and 14-1;

The operation of the image sensor shown in FIG. 11 will be described below with reference to a timing chart shown in FIG. First, an address assigned to an arbitrary unit pixel on the pixel array 1 is represented by an address A.
When designated as D, the address decoder 2 and row scan shift register 3 select a specific row corresponding to the designated address. Now, assuming that the word line corresponding to the selected row is word line WL0, row driver 6 applies word line WL from time t1 to time t2.
Activate 0. As a result, the word line WL0
The analog signals D0 and D1 are simultaneously read out from the amplifier circuits 10-00 and 10-10 connected to the ADC 12-0 and 12-1 respectively, and output to the ADCs 12-0 and 12-1 (see FIG. 10). 11 (", the first" R "in FIG. 12).
At time t2, the ADCs 12-0 and 12-1 convert the analog signals D0 and D1 into digital signals in parallel with each other, and the latches 13-0 and 13-1 convert the digital signals obtained by the A / D conversion. Latches ("" in FIG. 11 and the first "ADC" in FIG. 12).

Next, when the column scan shift register 4 sets the switching signal YSW0 to high level at time t3, the transfer switch 14-0 corresponds to the digital signal (that is, the analog signal D0) held by the latch 13-0. The digital value is sent to the output OUT (“” in FIG. 11 and the first “OUT” in FIG. 12). Next, at time t4, the column scan shift register 4 outputs the switching signal YS.
When W0 is returned to the low level and the switching signal YSW1 is set to the high level, the transfer switch 14-1 sends the digital signal held by the latch 13-1 (that is, the digital value corresponding to the analog signal D1) to the output OUT. ("" In FIG. 11 and the second "OU" in FIG.
T "). As described above, after all the analog signals read from the word line WL0 are simultaneously converted into digital signals and latched, each digital signal is output to the output O.
Output in order from the UT.

At time t5, the column scan shift register 4 returns the switching signal YSW1 to low level, and at the same time, the row driver 6 activates the word line WL1 from time t5 to time t6. As a result, the same operation as when the word line WL0 is activated is performed thereafter. That is, at time t5, the amplification circuit 10
-01 and 10-11, the analog signals D2 and D3 are simultaneously read out ("" in FIG. 11 and "2" in FIG. 12).
Th "R"). Next, at time t6, the ADC 12
-0 and 12-1 convert the analog signals D2 and D3 into digital signals in parallel, and the latches 13-0 and 13-1 respectively latch these conversion results (see "" in FIG. 11 and FIG. The second “ADC” in the middle). Next, when the switching signal YSW0 goes high at time t7, the transfer switch 14-0 sends the digital signal held by the latch 13-0 to the output OUT ("" in FIG. 11, and "" in FIG. 12). Third "OUT"). Next, when the switching signal YSW1 becomes high level at time t8, the transfer switch 14-1 sends the digital signal held by the latch 13-1 to the output OUT ("" in FIG. 11, FIG. 12).
The fourth “OUT” in the middle).

As described above, in the conventional image sensor that performs an A / D conversion operation in units of bit lines (columns), a period corresponding to a blank period (return period) for reading out an analog signal from the pixel array 1, A period for performing A / D conversion on analog signals for one horizontal signal line and a period for sequentially outputting digital signals for one horizontal signal line obtained by the A / D conversion appear repeatedly. Will be. Incidentally, in the actual image sensor, when the pixel array 1 is, for example, 1024 pixels × 768 pixels, 1024 digital signals are sequentially output from the output OUT for each of the 768 word lines.

[0013]

By the way, in recent years, the operation speed of the device to which the image sensor is applied has been increasingly increased, and accordingly, it is necessary to read out the frame information of the imaging screen from the image sensor at higher speed. Is happening. In order to meet such a demand for higher speed, it is considered effective to further speed up the operation of the A / D converter 8 and the column scan shift register 4. However, it is known that, for example, an A / D converter having a lower conversion speed has a simpler circuit configuration. If an A / D converter having a higher conversion speed is used, the area is inevitably increased. The required image area is squeezed, which hinders an increase in capacity. As described above, as the A / D converter to be applied to the image sensor, it is desirable to use an A / D converter having the lowest possible conversion speed while realizing a high-speed image sensor.

On the other hand, in order to keep the chip area as small as possible while keeping the imaging area of the image sensor as large as possible, it is necessary to reduce the area occupied by peripheral circuits other than the pixel array 1. In order to achieve such an object, for example, it is considered effective to reduce the area for the A / D converter. However, in order to do so, it is necessary to configure the A / D converter with a small-scale circuit, so that the conversion time is delayed, which affects the reading time of frame information from the image sensor. That is, when the processing time in the conventional image sensor is estimated, usually, the readout period (“R” in FIG. 12) is about several μsec, and the A / D conversion period (“ADC” in FIG. 12) is several μsec. ~ Several tens of microseconds. The output period of the digital signal (“OUT” in FIG. 12) is tens of nanoseconds × n where the number of columns of each word line is “n”, and the number of pixels in the horizontal direction on the imaging screen is taken into consideration. Then, the time required for the output operation is several μsec to several tens μsec, which is almost the same as the A / D conversion period. As described above, the ratio of the frame information to the entire readout time is dominated by the A / D conversion time and the output time. The time required for the D conversion is not negligible.

As described above, in an image sensor that performs A / D conversion on a column (bit line) basis, the overall readout time is increased and the pixel array is increased in capacity.
In order to respond to the two requests in a well-balanced manner, it can be said that an important issue is how to adjust the timing between the A / D conversion processing and the output processing to reduce the time required for these processings. The present invention has been made in view of the above points, and an object of the present invention is to shorten the time required for A / D conversion so that frame information on an imaged screen can be read faster than before. An object of the present invention is to provide an image sensor capable of increasing the capacity of a pixel array by using an A / D converter having a smaller area and a lower speed when the information reading time is the same as that in the related art.

[0016]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the invention according to claim 1 is characterized in that a pixel array storing analog data representing the intensity of received light for each pixel and a pixel array arbitrarily selected. An image having read means for reading analog data on a row from the pixel array, conversion means for converting each of the read analog data into digital data, and output means for simultaneously taking in the digital data and sequentially outputting the digital data In the sensor, the pixel array is divided into a plurality of groups in predetermined column units, and the conversion unit and the output unit are provided for each of the groups, and a conversion process performed by the conversion unit and an output process performed by the output unit are performed. It is characterized by comprising control means for operating the groups in parallel. The invention according to claim 2 is a pixel array that stores analog data representing the intensity of received light for each pixel, reading means for reading analog data on an arbitrarily selected column from the pixel array, In an image sensor having conversion means for converting each of the read analog data into digital data, and output means for simultaneously capturing and sequentially outputting the digital data, the pixel array is divided into a plurality of groups in a predetermined row unit. Along with the division, the conversion means and the output means are provided for each of the groups, and a control means for performing the conversion processing performed by the conversion means and the output processing performed by the output means in parallel between the groups is provided. I have. According to a third aspect of the present invention, in the first or second aspect of the present invention, the control unit sequentially performs the conversion process and the output process for each of the groups while performing the conversion process of a certain group and the other processes. It is characterized in that group output processing is performed simultaneously. According to a fourth aspect of the present invention, in the invention according to any one of the first to third aspects, the time required for the conversion means to convert all of the analog data into digital data is determined by the output means simultaneously. It is characterized by being within the time required to output all the captured digital data. According to a fifth aspect of the present invention, in the image sensor according to the first aspect, the analog data read from a pixel array in which analog data representing the intensity of received light is stored for each pixel is converted into digital data and sequentially output. The array is divided into a plurality of groups in a predetermined row unit or a column unit, and among a plurality of processes sequentially performed in each group, different types of processes are processed in parallel between the groups. It is characterized by doing.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram illustrating a configuration of the image sensor according to the present embodiment.
The same components as those shown in FIG. 10 are denoted by the same reference numerals. In the present embodiment, the pixel array, the noise control circuit, the A / D converter, and the column shift scan register are divided into two groups, A group and B group, respectively. . That is, the pixel array 21A, the noise control circuit 27A, the A / D converter 28A, and the column shift scan register 24A constitute the group A, and the pixel array 21
B, a noise control circuit 27B, an A / D converter 28B, and a column shift scan register 24B constitute a B group. In addition, the clock control circuit 25 has the same basic configuration and function as the clock control circuit 5 shown in FIG. 10, but the control timing of the clock signal supplied to each part in the image sensor is the same as that of the prior art. It is different from the clock control circuit 5.

Here, the outline will be described. As described above, in the conventional image sensor, each row of the pixel array 1 (see FIG. 10) is
From the analog signal for the row at the same time,
After performing the A / D conversion time on these analog signals, the digital signals obtained by these conversions are sequentially output, which is a sequential operation. That is,
During the output period of the digital signal, the A / D converter does not function at all and is idle. On the other hand, in the image sensor according to the present embodiment, the pixel array is divided into an arbitrary number of column units (in the following description, divided into groups A and B). The D conversion operation and the output operation are performed simultaneously and in parallel. By doing so, the idle time of the A / D converter is eliminated, and the time required for the A / D conversion operation can be apparently lost.

On the other hand, FIG. 2 shows the configuration of the image sensor shown in FIG. 1 for convenience of explanation of the operation of the image sensor shown in FIG. The same components as those shown in FIG. 11 are denoted by the same reference numerals. For simplicity of description, the noise control circuits 27A and 27B are not shown in FIG. 2 as in FIG.
Only the book is shown. That is, in the case of FIG. 2, the bit lines of the group A and the group B are each one. Also,
The ADCs 22-0 and 22-1 of the present embodiment are not configured to asynchronously convert an analog signal input to each A / D converter into a digital signal. A conversion operation is performed at a timing when a conversion instruction signal not to be given to these A / D converters.

Here, the detailed configuration of each part constituting the image sensor will be further described. First, FIG. 3 shows details of a unit pixel constituting the pixel array 1, and FIG. 3 shows an example in which a three-transistor type active system is adopted. In the figure, a photodiode 31 has exactly the same configuration and function as the photodiode 11-00 shown in FIG. Also, the code BL
Is a bit line, WL is a word line, VDD is a power supply voltage, and 32 to 34 are FETs (field effect transistors). The FET 32 empties the electric charge accumulated in the photodiode 31 by the reset signal RST when reading the voltage value from the photodiode 31. In addition, FET33 and FET
Reference numeral 34 denotes a source follower. When the FET 34 is turned on by the word line WL, the charge of the photodiode 31 is received by the gate terminal of the FET 33 and converted into a current value of the drain-source current Ids. According to such a configuration, the current value of the drain-source current Ids changes according to the intensity of light incident on the photodiode 31.

That is, the gate voltage Vg of the FET 33
Is calculated by the following equation (1), where Qs and Cs are the charge and capacitance of the photodiode 31 and Cg is the gate capacitance of the FET 33. Vg = Qs / (Cs + Cg) (1) Then, the drain-source current Ids is calculated by the following equation (2), where the transconductance of the FET is gm, and the gate-source voltage is Vgs. Ids = gm × Vgs (2) where the transconductance gm is μ, the effective mobility at the interface, the unit capacitance of the gate oxide film is Cox, the gate width is W, the gate length is L, and the threshold voltage is Vt. Is calculated by the following equation (3). gm = μ × Cox × (W / L) × (Vgs−Vt) (3) With the above configuration, the effect of reset noise can be reduced and good S / N (signal-to-noise) ) Ratio. Although the change in the current value is detected in FIG. 3, it goes without saying that a configuration for detecting the voltage value does not pose any problem.

FIG. 4 shows noise control circuits 27A and 27B.
Is shown for a certain bit line. In the figure, capacitors CS and CR are capacitors for respectively storing a noise component and a signal component of an analog signal output to the bit line BL. Also, FETs 41 and 4
Reference numeral 2 is for accumulating the noise component and the signal component from the bit line BL in the above-mentioned capacitors CS and CR, respectively, during the period when the signals SHS and SHR are given. That is, the capacitor S CS
, A noise component is stored in advance, and then the signal SHR
Thus, the signal on the bit line BL is taken into the capacitor CR. The FETs 43 and 44 are transfer switches, and the buffers 45 and 46 respectively store the voltage values of the capacitors CS and CR according to the switching signal YSW.
To communicate. In this way, the buffers 45 and 46 output a differential signal including the noise component voltage Vref and the signal component voltage Vsig to the A / D converter (see FIG. 1). Therefore, if the difference between these two signals is obtained on the A / D converter side, a signal from which noise has been canceled can be obtained. As described above, the above-described noise control circuit is configured to perform two readings of the signal and the noise, accumulate them in different capacitors, and then take the difference outside the noise control circuit. 1/10 to 1
/ 100 can be reduced.

Next, a configuration example of the ADCs 22-0 and 22-1 will be described with reference to FIGS. Since various methods have been devised as methods for implementing the A / D converter, here, only two methods will be described as representative examples, and these will be briefly described. First,
FIG. 5 shows a successive approximation type A / D converter. A control circuit 51 controls an N-bit (N: natural number) value set in a successive approximation register 53 based on a comparison result of a comparator 52. The comparator 52 has an input voltage IN,
The D / A converter 54 compares the digital value of the successive approximation register 53 with a signal voltage obtained by converting the digital value into an analog value, and compares the comparison result indicating the magnitude relationship between the two with the control circuit 51.
Output to The control circuit 51 performs bit-by-bit comparison from the upper bit to the lower bit of the successive approximation register 53, and changes the set value of the successive approximation register 53 according to the obtained comparison result, thereby performing N comparisons. Converts the analog voltage value of the input voltage IN into a digital value.

For example, when the value of N is "8", the control circuit 51 first sets only bit 7 of the successive approximation register 53 to "1", and sets the analog signal voltage value corresponding to the digital value and the input voltage IN. Are compared by the comparator 52. If the obtained comparison result indicates “input voltage IN <output voltage of D / A converter 54”, control circuit 51 changes bit 7 of successive approximation register 53 to “0”; Is set to “1”. Thereafter, for each bit up to bit 0 in the same procedure as for bit 7, the bit is initially set to "1".
, And each bit is appropriately reset to “0” according to the comparison result output from the comparator 52 in accordance with the case of the bit 7. When the comparison for eight bits is performed in this manner, a result obtained by converting the input voltage IN into a digital value is obtained in the successive approximation register 53. Note that the conversion speed of the A / D converter shown in FIG. 5 is about 1 μs to several hundred μs, which is lower than that of the A / D converter of FIG. 6 described below. The circuit scale can be reduced.

FIG. 6 shows an A / D converter of the parallel comparison type.
Data, and in this case, to obtain an N-bit digital value.
Assume a match. If you do, 2^N-1Comparators
61 _-1~ 61_-N-1And the reference voltage V_RBetween the ground
2 with the same resistance^NThe voltage is divided by the resistors R. Compare
Data 61_-1~ 61_-N-1Is the input voltage IN and the voltage at each voltage dividing point
Compare the values simultaneously and compare the magnitude relationship between them with the comparison result.
And output each. Therefore, the encoder 62
Pareta 61_-1~ 61_-N-1Based on the comparison result output by
To generate a digital value corresponding to the input voltage IN. here
Thus, the conversion speed of the A / D converter shown in FIG.
Ns or less, compared to the A / D converter shown in FIG.
The conversion speed is fast. However, for example,
Even 255 quantizations
Circuit configuration is complicated and large-scale
Becomes

FIG. 7A illustrates a detailed configuration of the column scan shift registers 24A and 24B. For example, in the case of the column scan shift register 24A, delay flip-flops (hereinafter abbreviated as “FF”) of the same number as the number of bit lines existing in the group A are connected in cascade. In FIG. 7A, the FFs 71-n to FF71-n at the n-th stage (n: natural number) to (n + 3) -th stage
Only +3 is shown. Furthermore, the first stage F (not shown)
An input DI is supplied to F, and a common clock CL is supplied to clock terminals CK of all FFs.

FIG. 7B shows the operation of the column scan shift register shown in FIG. First, the input DI supplied to the data input terminal D of the first-stage FF becomes high level for one clock period at time t11 in synchronization with the rise of the clock CL. Thereafter, the data of the input DI sequentially propagates through the FFs of the second and subsequent stages in accordance with the clock CL. Thereafter, at time t13, the FF 71-n captures the transmitted data at the rising timing of the clock CL, and switches the switching signal YSW
A high level is output for one clock period as n. Thereafter, similarly, at time t14, the FF 71-n + 1 takes in the data output from the FF 71-n, and sets the switching signal YSWn + 1 to 1
At the time t15, the FF 71-n + 2 outputs the high level as the switching signal YSWn + 2 for one clock period. As described above, A
The switching signal YSW sequentially goes high for each of the group and the group B, and as shown in FIG. 2, the output of the latch provided in each group is output via the transfer switch corresponding to the latch. It is sequentially output to.

Hereinafter, the operation of the image sensor having the configuration shown in FIG. 2 will be described with reference to a timing chart shown in FIG. First, when the address given to the specific unit pixel on the pixel array 1 is designated by the address AD, the row corresponding to the address designated by the address AD is selected by the address decoder 2 and the row scan shift register 3. Now, assuming that the word line corresponding to this row is the word line WL0, the row driver 6 changes the word line WL0 from time t21 to time t22.
Activate. As a result, the analog signal D is output from the amplifier circuit 10-00 of Group A connected to the word line WL0.
0 is read out to the noise control circuit 27A shown in FIG.
The analog signal whose noise has been canceled is the ADC of group A.
Output to 22-0. At this time, the word line WL0
The analog signal D1 is read out from the amplifier circuit 10-10 of the B group connected to the A group and the noise control circuit 27B shown in FIG.
The signal is output to the DC 22-1 ("" in FIG. 1, the first "R" in FIG. 8).

Next, at time t22, the clock control circuit 25 sends a conversion instruction signal to the ADC 22-0 of the A group. As a result, the ADC 22-0 converts the analog signal D0 into a digital signal, and the latches 13-0 of the A group latch the obtained conversion results ("" in FIG. 1 and the first "ADC" in FIG. 8). )). Next, at time t23, when the column scan shift register 24A sets the switching signal YSW0 to high level, the transfer switch 14-0 sets the latch 13-0.
Holds the digital signal (ie, the analog signal D0)
Is sent to the output OUT (FIG. 1).
“” In FIG. 8, the first “OUT” in FIG. 8). In an actual image sensor, since a large number of bit lines exist in each of the groups A and B, a digital value corresponding to an analog signal read from each of the bit lines is sequentially output. At this same time t23,
The clock control circuit 25 outputs the conversion instruction signal to the ADC2 of the B group.
Send to 2-1. As a result, the ADC 22-1 converts the analog signal D1 into a digital signal, and outputs the latch signal of the B group.
The conversion result obtained by 3-1 is latched (“′” in FIG. 1 and the second “ADC” in FIG. 8). As described above, during the period from the time t23 to the time t24, the output operation in the group A and the A / D conversion operation in the group B are performed in parallel.

Next, at time t24, the column scan shift register 24A returns the switching signal YSW0 to the low level, while the row driver 6 applies the word selected next to the word line WL0 from time t24 to time t25. The line WL1 is activated. As a result, the analog signal D2 is read out from the A-group amplifier circuit 10-01 connected to the word line WL1 to the noise control circuit 27A and output to the A-group ADC 22-0. At this time, the amplifier circuits 10 of the group B connected to the word line WL1 at the same time.
-11, the analog signal D3 is read out to the noise control circuit 27B and output to the ADC 22-1 in the B group ("" in FIG. 1 and the second "R" in FIG. 8).

Next, at time t25, when the column scan shift register 24B sets the switching signal YSW1 to the high level, the transfer switch 14-1 causes the digital signal (ie, the digital signal corresponding to the analog signal D1) held by the latch 13-1 to be transferred. Is sent to the output OUT ("" in FIG. 1 and the second "OUT" in FIG. 8). At the same time t25, the clock control circuit 25 sends the conversion instruction signal to the ADC 22-0 of the A group. As a result, the ADC 22-0 converts the analog signal D2 into a digital signal, and the latches 13-0 of the A group latch the obtained conversion results ("'" in FIG. 1, the third in FIG. 8). "AD
C "). As described above, during the period from time t25 to time t26, the output operation in the group B and the A / D conversion operation in the group A are performed in parallel.

Thereafter, substantially the same operation as in the period from time t23 to time t26 is performed. First, at time t26, the switching signal YSW1 is returned to the low level, and
When SW0 is set to the high level, the digital signal (that is, the digital value corresponding to the analog signal D2) held by the latch 13-0 is transmitted to the output OUT via the transfer switch 14-0 (FIG. 1). "" In FIG. 3, 3 in FIG.
Th "OUT"). Also, at the same time t26, when the clock control circuit 25 sends the conversion instruction signal to the ADC 22-1 in the B group, the ADC 22-1 converts the analog signal D3 into a digital signal, and converts the conversion result into the latch 13- in the B group. 1 is latched (“′” in FIG. 1 and the fourth “A” in FIG. 8).
DC "). As described above, the output operation in the group A and the A / D conversion operation in the group B are performed in parallel from time t26 to time t27.

Next, at time t27, the column scan shift register 24A returns the switching signal YSW0 to the low level. Thereafter, when the switching signal YSW1 is changed to the high level at time t28, the digital signal (that is, the digital value corresponding to the analog signal D3) held by the latch 13-1 is output via the transfer switch 14-1 to the output OU.
T ("" in FIG. 1 and the fourth "OUT" in FIG. 8). As described above, all analog signals held in the pixel array 1 are converted into digital signals and output from the output OUT.

As described above, in this embodiment, the pixel array 1 and its peripheral circuits are divided into two groups A and B, so that each of these groups can be used in one A / D conversion period and one output period. The amount of data handled is reduced by half. The control is performed so that the A / D conversion period of the group A and the output period of the group B, and the A / D conversion period of the group B and the output period of the group A overlap each other. Thereby, the first A / D conversion operation (that is, time t2 in FIG. 8)
All A / D conversion operations except for 2 to t23) are performed concurrently with the output operation. Therefore, if the time required for the output operation is longer than the time required for the A / D conversion, it is possible to hide all the second and subsequent A / D conversion periods behind the output period.

Here, the processing time in the present embodiment is the same as that of the prior art, that is, several μsec for the readout period (“R” in FIG. 8). On the other hand, A / D
The conversion period ("ADC" in FIG. 8) is also the same as the conventional case, and is several μsec to several tens μsec. In this embodiment, the A / D conversion operation is not performed simultaneously for all the columns (bit lines), but different A / D conversion periods are provided for the groups A and B. For this reason, in the present embodiment, the time required for A / D conversion of one word line is twice as long as that of the related art, but as described above,
Since the period other than the first A / D conversion period is hidden by the output period, the time required for the second and subsequent A / D conversion can be regarded as substantially “0”. On the other hand, during the output period of the digital signal (“OUT” in FIG. 8), the output operation is performed while being divided into the groups A and B, so that one output period (for example, times t23 to t24 in FIG. 8). ) Is half of the conventional one (ie, if the number of columns is “n”, one output period is several tens of nanoseconds ×
n / 2). However, since the output operation is performed in groups A and B, the time required to output a digital signal for one word line is the same as the conventional case.

Next, with reference to FIG. 9, the advantages of the present invention will be described while comparing the operation of the present embodiment with the operation of the prior art. In FIG. 9, reference numerals such as "" indicate the same reference numerals as those shown in FIG. 2 or FIG. The time required for the latches 13-0 and 13-1 (see FIG. 2 or FIG. 11) to latch the digital signals output from the ADCs 22-0 and 22-1, respectively, is the A / D conversion period or the output period. Since this time is negligible when compared with, this time is included in the A / D conversion time in the following description.

FIG. 9A shows the operation timing when the conversion speed of the A / D converter used is the same in the prior art and this embodiment. First, the time required for reading from the pixel array 1 with respect to the word line WL0 (in each case "" in the figure) is the same as that of the prior art and this embodiment. Further, since it is assumed that the A / D conversion speed is the same as described above, the A / D conversion processing time in the related art and the A / D conversion processing time in the present embodiment are different.
The A / D conversion processing time of the group is also the same (in each case, "" in the figure). On the other hand, as for the output operation following the A / D conversion operation, the output operation for n columns is performed at a time in the related art (“” in the figure), whereas in the present embodiment, the output operation is first performed for the group A. Is performed (“” in the figure), so in the present embodiment, it is half of the time indicated by “” in the related art. At this time, in this embodiment, the A / D conversion operation for the group B is performed in parallel ('in the figure). Next, the reading time of the word line WL1 from the pixel array 1 is the same in the related art and the present embodiment ("", "
"" In the present embodiment).

Next, in the prior art, the same A / D conversion operation and output operation are performed on the word line WL1 in the period "-" as in the period "-". On the other hand, in the present embodiment, first, B
The output operation of the group ('in the figure) and the A / D conversion operation of the group A for the word line WL1 ("" in the figure) are performed at the same time. "") And A of group B for word line WL1.
After the / D conversion operation ("'" in the figure) is performed at the same time, the output operation of group B for the word line WL1 ("" in the figure) is performed. In this way, the read operation from the pixel array 1 can be completed in a processing time in the present embodiment that is shorter than the A / D conversion time indicated by “” in the related art. Strictly speaking, from the time indicated by "" in the prior art, the time t27 to t2 in FIG.
The processing time can be reduced by the time obtained by subtracting the time of “#” in FIG. As described above, the image sensor of the present embodiment has the same conversion speed A
When the / D converter is used, there is an advantage that high-speed reading is possible as compared with the conventional image sensor.

On the other hand, FIG. 9B shows the operation timing when the time required for the read operation from the pixel array 1 is made the same between the prior art and this embodiment. As can be understood from the description of FIG. 9A, “” of the related art and “” of the present embodiment, “” of the related art and “” and “” of the present embodiment, and “ ”And“ ”of the present embodiment, and“
"And""and""in the present embodiment have the same time. In other words, as is apparent from comparison of the respective times required for “” in the related art and “” in the present embodiment, the time corresponding to “” in the related art can be reduced in the present embodiment. Accordingly, the conversion speed required for the A / D converter can be reduced. Strictly speaking, ""
A / A is the time obtained by subtracting the time of “#” from the time shown in
The allowable range of the conversion time of the D converter can be extended. Also, the A / D conversion periods "'", "'",
Since the time of “′” is usually shorter than the time of the corresponding output periods “”, “”, “”, the conversion time capability of the A / D converter should be set in accordance with these output periods. For example, it is possible to hide behind the output period except for the first A / D conversion period. As described above, the image sensor according to the present embodiment can perform an A / D operation as compared with the related art if the reading operation from the pixel array 1 is completed within the same time as the related art image sensor.
There is an advantage that the conversion can be performed at a low speed and the A / D converter can be configured with a circuit occupying a small area.

It is to be noted that the pixel array does not necessarily have to be divided into two equal parts as in the above-described embodiment. For example, a configuration in which the number of columns of the group A and the number of columns of the group B are different from each other is also within the scope of the present invention. However, if the A / D conversion period is hidden behind the output period, the output period is the shortest (in other words, the number of columns or the number of bit lines is the smallest).
Since the maximum value of the conversion speed of the A / D converter is determined by the output time of each group, it is most preferable that the number of columns in each group be the same in order to equalize the output time of all groups. In the above embodiment, the conversion speed of the A / D converter is determined so that the A / D conversion period is always within the range of the output period. However,
Even if the A / D conversion period is slightly longer than the output period, the A / D
Such a case is also within the scope of the present invention because the conversion period is apparently zero. Further, in the above-described embodiment, an example in which the pixel array is divided in units of columns has been described, but it is needless to say that the same effect can be obtained even when the pixel array is divided in units of rows.

[0041]

As described above, according to the present invention, the pixel array is divided into a plurality of groups, and the conversion process from analog data to digital data and the output process of digital data are performed for each group. And output processing are performed in parallel between groups. Therefore, the processing time of a portion where the conversion process overlaps with the output process can be apparently eliminated. Accordingly, by ensuring that the time required for the conversion processing is always within the range of the time required for the output processing, when viewed from the outside of the image sensor, all A / D conversions except the first A / D conversion period are performed. It is possible to completely hide the period behind the output period. Further, when an A / D converter having the same conversion speed as that of the related art is used as the conversion means, the time required for reading out the frame information stored in the pixel array is shorter than that of the related art. Output can be realized. Furthermore, if the reading time of the frame information stored in the pixel array can be the same as the conventional one, an A / D converter capable of A / D conversion within the time required for the output processing may be used. Thus, it is possible to select an A / D converter having a smaller area and a lower speed than the conventional one.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an image sensor according to an embodiment of the present invention.

FIG. 2 is a block diagram showing the configuration of the image sensor shown in FIG. 1 in more detail.

FIG. 3 is a circuit diagram showing a configuration of a unit pixel which is a configuration unit of the pixel array in the embodiment.

FIG. 4 is a circuit diagram illustrating a configuration of a noise control circuit according to the first embodiment.

FIG. 5 shows a first example of the A / D converter in the embodiment.
FIG. 3 is a block diagram showing a configuration of a successive approximation type A / D converter which is a configuration example of FIG.

FIG. 6 shows a second example of the A / D converter in the embodiment.
FIG. 2 is a block diagram showing a configuration of a parallel comparison type A / D converter which is a configuration example of FIG.

FIGS. 7A and 7B are explanatory diagrams relating to the column scan shift register according to the embodiment, wherein FIG. 7A is a block diagram illustrating the configuration of the register, and FIG. 7B is a timing chart illustrating the operation of the register.

FIG. 8 is a timing chart showing the operation of the image sensor according to the first embodiment.

9A and 9B are diagrams comparing the operation performed in the conventional art and the embodiment, and FIG. 9A illustrates the operation timing when the A / D converter having the same conversion speed is used in the conventional art and the embodiment; (B) is an operation timing when the time required for the read operation from the pixel array is the same between the conventional technique and the present embodiment.

FIG. 10 is a block diagram illustrating a configuration of an image sensor according to a conventional technique.

11 is a block diagram showing the configuration of the image sensor shown in FIG. 10 in more detail.

FIG. 12 is a timing chart showing an operation of an image sensor according to a conventional technique.

[Explanation of symbols]

 1, 21A, 21B Pixel array 2 Address decoder 3 Row scan shift register 6 Row driver 24A, 24B Column scan shift register 25 Clock control circuit 27A, 27B Noise control circuit 28A, 28A A / D converter

Claims (5)

[Claims] 1. A pixel array for storing analog data representing the intensity of received light for each pixel, reading means for reading analog data on an arbitrarily selected row from the pixel array, and reading the analog data. In an image sensor having conversion means for converting each of the data into digital data and output means for simultaneously capturing and sequentially outputting the digital data, the pixel array is divided into a plurality of groups in predetermined column units, An image sensor comprising: a conversion unit and the output unit for each of the groups; and a control unit that performs a conversion process performed by the conversion unit and an output process performed by the output unit in parallel between the groups. 2. A pixel array for storing analog data representing the intensity of received light for each pixel, reading means for reading analog data on an arbitrarily selected column from the pixel array, and reading the analog data. In an image sensor having conversion means for converting each of the data into digital data, and output means for simultaneously capturing and sequentially outputting the digital data, the pixel array is divided into a plurality of groups in a predetermined row unit, An image sensor comprising: a conversion unit and the output unit for each of the groups; and a control unit that performs a conversion process performed by the conversion unit and an output process performed by the output unit in parallel between the groups. 3. The control unit according to claim 2, wherein the control unit causes the conversion process of one group and the output process of another group to be performed simultaneously while sequentially performing the conversion process and the output process for each group. Item 3. The image sensor according to Item 1 or 2. 4. The time required for the conversion means to convert all of the analog data to digital data is within a range required for the output means to output all digital data taken in at the same time. The image sensor according to claim 1, wherein: 5. An image sensor for converting analog data read from a pixel array in which analog data representing the intensity of received light is stored for each pixel into digital data and sequentially outputting the digital data, wherein the pixel array includes a predetermined row. It is divided into a plurality of groups in units or columns, and among a plurality of processes sequentially performed in each of these groups, different types of processes are processed in parallel between the groups. Image sensor.