JP2000151420A - Data coding device and data coding method, data processing unit and data processing method, data converter and data conversion method, data multiplexer and data multiplexing method, and data transmission equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data coding device or the like connecting to, e.g. a multiplexer where rate conversion can easily and quickly be converted. SOLUTION: A VLC section 205 obtains video data D5 that include coded data configured resulting from applying variable length coding to quantized DCT coefficient data D4 (coefficient series) obtained by applying DCT processing and quantization processing to a video signal. A generating section 207 outputs every unit-time information denoting a degree of order of the coefficient series where a share rate of a generated code quantity by coefficients of the degree of order or over to all generated code quantity of the video data D5 per unit time (occupancy ratio) is a reference occupancy ratio as information D7. An information addition section 208 adds the information D7 to the video data D5 for every unit-time to obtain output video data PESa. In the case that the video data PESa are fed to, e.g. the data multiplexer, where the data are multiplexed, a rate variable type multiplex buffer utilizes the information D7 to easily and quickly convert the rate into a prescribed rate.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data encoding device and a data encoding method, a data processing device and a data processing method, a data conversion device and a data conversion method, and a data conversion method suitable for, for example, a digital satellite broadcasting system. The present invention relates to a multiplexing device, a data multiplexing method, and a data transmission device. Specifically, input data is subjected to orthogonal transform coding to generate a coefficient sequence, the coefficient sequence is subjected to variable length coding to obtain coded data, output data including the coded data is obtained, and the coefficient per unit time is obtained. By generating information related to the generated code amount by coefficients of some or all orders of a column and outputting it in synchronization with output data, for example, it is easy to convert the output data to a predetermined rate in a multiplexer, The present invention relates to a data encoding device and the like which can be performed quickly.

[0002]

2. Description of the Related Art In recent years, digital satellite broadcasting systems have become widespread. In this system, a video signal and an audio signal are digitally compressed and encoded according to the MPEG standard and the like, and a bit stream obtained by multiplexing according to the MPEG standard and the like is transmitted via a satellite. Is received, video data and audio data are separated, and then decoded to obtain a video signal and an audio signal.

As a bit stream, for example, MPE
A G2 (Moving Picture Experts Group 2) transport stream is used. FIG. 17B shows an MPEG2 transport stream, in which a plurality of programs, for example, transport stream packets of a fixed length of 188 bytes of programs # 1 to # 3 (hereinafter referred to as “T
S packets) are continuous. Each T
As shown in FIG. 17A, the S packet includes a 4-byte packet header and an 184-byte adaptation field and / or payload.

[0004] The packet header includes a synchronization byte for detecting the head of the TS packet, and a PID (Packet Identifier) indicating the attribute of an individual stream (data string) of the packet.
identification: packet identifier), and adaptation field control information indicating the presence / absence of an adaptation field and the presence / absence of a payload in this packet. In the adaptation field, additional information and a stuffing byte (invalid data byte) regarding the individual stream are arranged. The payload includes, for example, video and audio PES (Packetized) shown in FIG. 17C.
Elementary Stream) packet is subdivided and distributed.

[0005]

Techniques for improving image quality and transmission efficiency by handling input data of a multiplexing device at a variable rate have been put to practical use. In a multiplexing device that multiplexes a plurality of variable rate signals, a statistical multiplexing method for performing feedback control to an encoder is often used as a multiplexing control method.

However, the feedback control to the encoder depends on the performance of the encoder, and the time required for the encoder to transition to a stable operation state cannot be defined by the multiplexer. Therefore, the multiplexing device must absorb the data delay variation of the surplus data which occurs before the stable operation starts. This increases the delay time when multiplexing and causes synchronization failure in the receiving apparatus. Therefore, a rate excellent in responsiveness for preventing synchronization failure until the encoder enters stable operation. A conversion device is required. Therefore,
SUMMARY OF THE INVENTION It is an object of the present invention to provide a data encoding device or the like that can easily and quickly convert to a predetermined rate in a multiplexing device.

[0007]

A data encoding apparatus according to the present invention comprises: first encoding means for orthogonally transform-encoding input data to generate a coefficient sequence; and variable-length encoding of the coefficient sequence for encoding. Second encoding means for obtaining encoded data, data output means for obtaining output data including the encoded data,
Code length output means for outputting the code length of each code word constituting the encoded data, and degree generation means for generating the degree of the coefficient sequence corresponding to the level indicated by each code word based on the coefficient sequence, Generating code amount calculating means for calculating the total generated code amount of the output data per unit time; code length output from the code length output means; the order generated by the order generating means; and the generated code amount calculating means. Based on the total generated code amount obtained in the above, the generation related to the ratio of the generated code amount due to the coefficients of part or all of the coefficient sequence to the total generated code amount of the output data per unit time. And generating code amount information output means for generating code amount information and outputting the generated code amount information in synchronization with the output data. It should be noted that there is no generated code amount calculation means,
The generated amount information output means may generate generated code amount information indicating the generated code amount based on the coefficients of part or all of the coefficient sequence per unit time.

In the present invention, input data is subjected to orthogonal transform coding to generate a coefficient sequence, the coefficient sequence is subjected to variable length coding to obtain coded data, and the coded data and another variable length code are obtained. The encoded data, the fixed-length encoded data, and the like are synthesized, and output data including the encoded data is obtained.

The encoded data is composed of a plurality of codewords, and the code length output means outputs the code length of each codeword. In addition, each codeword constituting the encoded data is
It shows a combination of runs, each of which is a continuous number of zero coefficients, and levels of non-zero coefficients that follow. In the order generation means, the order of the coefficient sequence corresponding to the level indicated by each of the above-mentioned code words is generated based on the coefficient sequence.
Further, the total generated code amount of output data per unit time, for example, in slice units of MPEG2 is calculated.

Then, based on the code length of each code word constituting the coded data, the order of the coefficient sequence corresponding to the level indicated by each code word, and the total generated code amount of output data per unit time, Generated code amount information related to the ratio of the generated code amount due to coefficients of a part or all of the coefficient sequence to the total generated code amount of output data per time is generated and output in synchronization with the output data. You. For example, the generated code amount information is added to the output data and output as one system of data.

For example, the generated code amount information is a coefficient sequence in which the ratio of the generated code amount by a coefficient of the order or more to the total generated code amount of output data per unit time is a predetermined ratio (reference occupancy ratio). Is the information indicating the order of. Further, for example, the generated code amount information includes information indicating a ratio of a generated code amount by a coefficient of the order or more to the entire generated code amount of output data per unit time in a part or the whole order of the coefficient sequence. Is done. Further, for example, the generated code amount information is information indicating a ratio of a generated code amount occupied by coefficients of a part or all orders of the coefficient sequence to a total generated code amount of output data per unit time. Further, for example, the generated code amount information is information indicating a generated code amount based on coefficients of some or all orders of the coefficient sequence per unit time.

As described above, the generated code amount information is also output in synchronization with the output data. Therefore, for example, in a multiplexing apparatus, the generated code amount information can be used when performing the rate conversion of the output data of the above-described data encoding apparatus, and the rate conversion can be performed easily and quickly. As a result, it is possible to avoid an increase in delay time in multiplexing, and to prevent inconvenience such as synchronization failure in the receiving device.

[0013] Further, a data processing apparatus according to the present invention comprises:
A data delay unit for delaying input data including coded data obtained by performing variable-length coding on a coefficient sequence of an orthogonal transform code by a predetermined time to obtain output data; and a data delay unit for forming coded data included in the input data. Code length output means for outputting the code length of the code word, degree generation means for decoding the coded data included in the input data and generating the degree of the coefficient sequence corresponding to the level indicated by each code word, and A code amount calculating means for calculating the total code amount of the input data, a code length output from the code length output means, an order generated by the order generating means, and a unit time based on the total code amount obtained by the code amount calculating means. Generates code amount information related to the ratio of the amount of code generated by coefficients of part or all of the coefficient sequence to the total code amount of input data per unit, and outputs it in synchronization with output data That it is intended and a code quantity information output means. It should be noted that the code amount calculating means is not provided, and the code amount information output means may generate the code amount information indicating the code amount by the coefficients of a part or all of the above-mentioned coefficient sequence per unit time. Good.

According to the present invention, input data including coded data obtained by performing variable length coding on a coefficient sequence of an orthogonal transform code is delayed by a predetermined time to obtain output data.
The coded data included in the input data is composed of a plurality of codewords, and the code length output means outputs the code length of each codeword. Further, each codeword constituting the encoded data indicates a combination of a run, which is the continuous number of zero coefficients, and a level of a non-zero coefficient that follows. In the order generating means, for example, the encoded data is decoded, and the order of the coefficient sequence corresponding to the level indicated by each codeword is generated based on the decoded data. Further, the total code amount of the input data per unit time, for example, in the slice layer unit of MPEG2 is calculated.

The unit time based on the code length of each code word constituting the encoded data, the order of the coefficient sequence corresponding to the level indicated by each code word, and the total code amount of the input data per unit time Code amount information relating to the ratio of the generated code amount due to coefficients of a part or all of the coefficient sequence to the entire code amount of the input data per unit is generated and output in synchronization with the output data. For example, code amount information is added to the output data and output as one system of data.

In this manner, the code amount information is also output in synchronization with the output data. Therefore, for example, in a multiplexing apparatus, the code amount information can be used when performing the rate conversion of the output data of the data processing apparatus, and the rate conversion can be performed easily and quickly. As a result, it is possible to avoid an increase in delay time in multiplexing, and to prevent inconvenience such as synchronization failure in the receiving device.

A data conversion device according to the present invention comprises: a data conversion means for performing data conversion processing on input data including coded data obtained by performing variable length coding on a coefficient sequence of an orthogonal conversion code; A data delay unit that obtains output data by delaying the conversion data output from the unit by a predetermined time, a code length output unit that outputs a code length of each code word included in the encoded data included in the conversion data,
Order generation means for decoding the encoded data included in the converted data to generate the order of the coefficient sequence corresponding to the level indicated by each codeword, and code amount calculating means for calculating the total code amount of the converted data per unit time; Based on the code length output from the code length output unit, the order generated by the order generation unit, and the total code amount obtained by the code amount calculation unit, the coefficient sequence of the coefficient sequence is converted with respect to the total code amount of the conversion data per unit time. A code amount information output means for generating code amount information relating to a ratio of a generated code amount occupied by coefficients of some or all orders, and outputting the generated code amount information in synchronization with output data. It should be noted that the generated code amount calculation means is not provided, and the code amount information output means generates the code amount information indicating the code amount by the coefficients of some or all orders of the coefficient sequence per unit time. Is also good.

In the present invention, data conversion processing is performed on input data including coded data obtained by performing variable length coding on a coefficient sequence of an orthogonal transform code. This data conversion processing is, for example, rate conversion processing or format conversion processing. Then, the converted data is delayed by a predetermined time to obtain output data. The encoded data included in the converted data is composed of a plurality of codewords, and the code length output means outputs the code length of each codeword. Further, each codeword constituting the encoded data indicates a combination of a run, which is the continuous number of zero coefficients, and a level of a non-zero coefficient that follows. In the order generating means, for example, the encoded data is decoded, and the order of the coefficient sequence corresponding to the level indicated by each codeword is generated based on the decoded data. Further, the total code amount of the converted data data per unit time, for example, in MPEG2 slice layer units is calculated.

Then, based on the code length of each code word constituting the encoded data, the order of the coefficient sequence corresponding to the level indicated by each code word, and the total code amount of the converted data per unit time, Code amount information relating to the ratio of the generated code amount due to the coefficients of a part or all of the coefficient sequence to the entire code amount of the converted data per unit is generated and output in synchronization with the output data. For example, code amount information is added to the output data and output as one system of data.

As described above, the code amount information is also output in synchronization with the output data. Therefore, for example, in a multiplexing apparatus, the code amount information can be used when performing the rate conversion of the output data of the data conversion apparatus described above, and the rate conversion can be performed easily and quickly. This allows
It is possible to avoid an increase in delay time during multiplexing, and to prevent inconvenience such as synchronization failure in the receiving device.

Further, the data multiplexing device according to the present invention comprises: a first input means for inputting a plurality of input data including coded data obtained by performing variable length coding on a coefficient sequence of an orthogonal transform code; A second input means for inputting a plurality of code amount information items related to the code amounts of the coefficients of part or all of the coefficient sequence per unit time, each being synchronized with the input data of And a data multiplexing means for multiplexing output data of the plurality of rate converting means to obtain multiplexed data based on the above.

According to the present invention, a plurality of input data including coded data obtained by performing variable length coding on a coefficient sequence of an orthogonal transform code is input, and a part or all of the coefficient sequence per unit time is input. A plurality of pieces of code amount information related to the code amount based on the order coefficient are input. In this case, the input data and the code amount information are input separately, or one system of data in which the code amount information is added to the input data is input.

In the plurality of rate conversion means, each rate conversion of the plurality of input data is performed based on the code amount information. Then, the output data of the rate converter is multiplexed to obtain multiplexed data, and the multiplexed data is output as, for example, data for transmission. As described above, the plurality of rate conversion means can perform the rate conversion based on the code amount information, and the rate conversion can be performed easily and quickly. As a result, it is possible to avoid an increase in delay time in multiplexing, and to prevent inconvenience such as synchronization failure in the receiving device.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows a digital satellite broadcasting system 1 according to a first embodiment.
00 is shown.

The broadcasting system 100 includes, on the transmission side, video encoders 111A to 111C for compressing and encoding video signals Va to Vc, for example, according to the MPEG standard, and video output from the video encoders 111A to 111C. Data (video PES packet) PESa to PE
Each Sc is packetized into a TS packet and multiplexed,
A multiplexing device 114 for obtaining a transport stream TS (see FIG. 17B);
A transmitter 115 for digitally modulating S and up-converting it to a predetermined frequency band to obtain a broadcast signal, and a transmitting antenna 1 for transmitting the broadcast signal to the satellite 120
16.

Note that the video data PESa to PESc
Are parallel data in byte units. In addition, although not shown in FIG. 17B, actually, each TS packet (188 bytes) is provided with a 16-byte error correction parity, which is used for error correction processing on the receiving side. The multiplexing device 114 has video data PESa generated by the video encoders 111A to 111C.
To PESC, video data PESa to PES reproduced by a reproducing device such as a disk device, for example.
A configuration for supplying c is also conceivable.

Further, the broadcasting system 100 provides the receiving side with:
A reception antenna 117 for receiving a broadcast signal transmitted from the satellite 120, and a demodulation process, a decode process, and the like are performed on the broadcast signal received by the reception antenna 117 to obtain a video signal Vo of a predetermined program. It has a receiving device 118 and a monitor 119 for displaying an image based on the video signal Vo.

In the above configuration, the video encoders 111A to 111C on the transmitting side respectively transmit video signals Va to Va.
Vc is compression-encoded and video data PESa-P
ESc is formed and the video data PESa to PES
c is supplied to the multiplexer 114. Multiplexer 114
, Video data PESa to PESc are packetized into TS packets, respectively, and then multiplexed to MPE.
A transport stream TS of G2 is formed, and the transport stream TS is supplied to the transmission device 115.

In the transmitting device 115, the transport stream TS is subjected to digital modulation processing and up-conversion processing to form a broadcast signal. Then, the broadcast signal is supplied to the transmission antenna 116, and the broadcast signal is transmitted from the transmission antenna 116 to the satellite 120.

The broadcast signal transmitted from the satellite 120 is received by the receiving antenna 117 on the receiving side, and the received broadcast signal is supplied to the receiving device 118. In the receiving device 118, demodulation processing, decoding processing, and the like are performed on the received broadcast signal, and a video signal Vo of a predetermined program is obtained. The video signal Vo is transmitted to the monitor 1
19, and the monitor 119 supplies a video signal Vo
Is displayed.

The configuration of the video encoder 111A will be described. FIG. 2 shows the configuration of the video encoder 111A. The video encoder 111A has an input terminal 200 for inputting a video signal Va, and a preprocessing unit 201 that performs preprocessing on the video signal Va to obtain macroblock data D1.

The pre-processing unit 201 generates an I picture (Intra-picture) for each frame image of the video signal Va sequentially inputted.
Picture), a P picture (Predictive-Picture), or a B picture (Bidirectionally Predictive-Picture), which is to be processed as one of the three image types, and then the corresponding frame is selected according to the image type of the frame image. The images are rearranged in the encoding order, and the frame image is further divided into macroblocks composed of a luminance signal of 16 pixels × 16 lines and a color difference signal corresponding to the luminance signal, and this is output as macroblock data D1. Is what you do.

The video encoder 111A converts the motion vector of each macroblock into macroblock data D
1 and a motion vector detecting unit 215 that obtains motion vector data D15 calculated based on the reference image data D13 stored in the frame memory 213. , An arithmetic circuit 202 for performing processing in one of the forward prediction mode, the backward prediction mode, and the bidirectional prediction mode to obtain transmission data.

Here, the intra mode is a method in which a frame image to be encoded is directly used as transmission data. The forward prediction mode is a method in which a prediction residual between a frame image to be encoded and a past reference image is used as transmission data. The backward prediction mode is a method in which a prediction residual between a frame image to be encoded and a future reference image is used as transmission data. The bidirectional prediction mode is a method in which a prediction residual between a frame image to be encoded and an average value of two prediction images, a past reference image and a future reference image, is used as transmission data.

The video encoder 111A reads the reference image data D13 by shifting the read address of the frame memory 213 in accordance with the motion vector data D15, and transfers the read reference image data D13 to the forward predicted image data D14F or the backward predicted image data. As D14B, it has a motion compensation unit 214 that supplies the arithmetic circuit 202 described above and an arithmetic circuit 212 described later.

The video encoder 111A performs a DCT (discrete cosine transform) process, which is one of orthogonal transforms, on the operation data D2 from the operation circuit 202 to convert the operation data D2 into a DCT coefficient. Quantization unit 2 that performs quantization processing on DCT coefficient data D3 from DCT unit 203 to obtain quantized DCT coefficient data D4
And a control unit 216 that supplies a quantization control value D16 to the quantization unit 204 and adjusts the quantization step size in the quantization process to control the amount of code generated.

The video encoder 111A performs an inverse quantization process on the quantized DCT coefficient data D4 output from the quantization section 210 to obtain DCT coefficient data D10. DCT coefficient data D10
DCT unit 211 that performs inverse DCT processing on the image to obtain operation data D11, and a reference image using operation data D11 from this inverse DCT unit 211 and image data D14F and D14B from motion compensation unit 214 described above. And an arithmetic circuit 212 for obtaining the data D13 and storing it in the frame memory 213.

In the above configuration, first, the operation when the macroblock data D1 is an I picture will be described. In this case, the macro block data D1 is processed in the intra mode.

That is, the arithmetic circuit 202 includes the pre-processing unit 20
The macroblock data D1 from 1 is supplied as it is to the DCT section 203 as operation data D2. DCT unit 2
03 performs DCT processing on the operation data D2 to make it a DCT coefficient, and supplies this to the quantization unit 204 as DCT coefficient data D3. Then, the quantization unit 204
Performs a quantization process on the DCT coefficient data D3 to obtain quantized DCT coefficient data D4. The quantized DCT coefficient data D4 is obtained by the inverse quantization unit 210 and a VLC (Variable Length Code) described later.
e) Supply to the unit 205.

The inverse quantization unit 210 performs quantization DCT.
An inverse quantization process is performed on the coefficient data D4 to obtain DCT coefficient data D10, which is supplied to the inverse DCT unit 211. The inverse DCT section 211 outputs the DCT coefficient data D10
Is subjected to inverse DCT processing to obtain operation data D11,
It is supplied to the arithmetic circuit 212. And the arithmetic circuit 2
12 supplies the operation data D11 as it is to the frame memory 213 as reference image data D13 and stores it.

Next, the operation when the macroblock data D1 is a P picture will be described. In this case, the macroblock data D1 is processed in one of the intra mode and the forward prediction mode.

When the prediction mode is the intra mode, the arithmetic circuit 202 supplies the macroblock data D1 from the preprocessing unit 201 to the DCT unit 203 as the arithmetic data D3 as it is, as in the case of the above-described I picture.

On the other hand, when the prediction mode is the forward prediction mode, the arithmetic circuit 202 performs a subtraction process on the macroblock data D1 using the forward prediction image data D14F supplied from the motion compensator 214. .

The forward predicted image data D14F is the reference image data D13 stored in the frame memory 213.
Is obtained by performing motion compensation according to the motion vector data D15. That is, in the forward prediction mode, the motion compensation unit 214 shifts the read address of the frame memory 213 in accordance with the motion vector data D15 to read the reference image data D13, and uses the read reference image data D13 as the forward prediction image data D14F. It is supplied to the arithmetic circuit 212. The operation circuit 202 subtracts the forward prediction image data D14F from the macroblock data D1 to obtain difference data as a prediction residual, and supplies the difference data as operation data D2 to the DCT unit 203.

In the forward prediction mode, the operation circuit 212 adds the forward prediction image data D14F to the operation data D11 obtained by the inverse DCT unit 211 to generate the reference image data D13 (P picture). Play local,
It is stored in the frame memory 213.

Next, the operation when the macroblock data D1 is a B picture will be described. In this case, the macroblock data D1 is processed in any of the intra mode, the forward prediction mode, the backward prediction mode, and the bidirectional prediction mode.

When the prediction mode is the intra mode or the forward prediction mode, the macroblock data D1 is subjected to the same processing as that for the P picture described above. Where B
Since the picture is not used as another predicted reference image,
In this case, the reference image data D13 obtained from the arithmetic circuit 212 is not stored in the frame memory 213.

On the other hand, when the prediction mode is the backward prediction mode, the arithmetic circuit 202 performs a subtraction process on the macroblock data D1 using the backward predicted image data D14B supplied from the motion compensator 214. .

The backward predicted image data D14B is the reference image data D13 stored in the frame memory 213.
Is obtained by performing motion compensation according to the motion vector data D15. That is, in the backward prediction mode, the motion compensation unit 214 shifts the read address of the frame memory 213 in accordance with the motion vector data D15 and reads the reference image data D13, and uses the read reference image data D13 as the backward prediction image data D14B. It is supplied to the arithmetic circuit 212. The arithmetic circuit 202 subtracts the backward prediction image data D14B from the macroblock data D1 to obtain difference data as a prediction residual, and supplies the difference data as arithmetic data D2 to the DCT unit 203.

In the backward prediction mode, the operation circuit 212 adds the backward prediction image data D14B to the operation data D11 obtained by the inverse DCT unit 211 to convert the reference image data D13 (B picture). Play locally. However, since the B picture is not used as another predicted reference image, the reference image data D13 in this case is used.
Are not stored in the frame memory 213.

Next, when the prediction mode is the bidirectional prediction mode, the arithmetic circuit 202 calculates the average of the forward predicted image data D14F and the backward predicted image data D14B supplied from the motion compensator 214 from the macroblock data D1. The value is subtracted to obtain difference data as a prediction residual, and the difference data is supplied to the DCT unit 203 as operation data D2.

In the bidirectional prediction mode, the operation circuit 212 is supplied with the forward prediction image data D14F and the backward prediction image data D14B from the motion compensation unit 214, and the operation circuit 212 includes an inverse DCT unit. The reference image data D13 (B picture) is locally reproduced by adding the average value of the forward prediction image data D14F and the backward prediction image data D14B to the operation data D11 obtained in 211. However, since the B picture is not used as another predicted reference image, the reference image data D13 in this case is not stored in the frame memory 213.

As described above, the video encoder 11
1A is subjected to motion compensation prediction processing, DCT processing, and quantization processing,
The data is supplied to the VLC unit 205 as coefficient data D4.

Next, a configuration other than the above-described configuration of the video encoder 111A will be described. That is, the video encoder 111A performs variable-length encoding on the quantized coefficient data D4 obtained by the quantization unit 204 based on a predetermined conversion table to obtain encoded data. And a VLC unit 205 that combines other variable-length coded data and fixed-length coded data to create video data D5 as a PES packet.

Even if not described above, the DCT unit 203 uses 8 pixels × 8 pixels.
DCT operation is performed for each line block. VLC
The quantized DCT coefficient data D4 supplied to the unit 205 is
The quantized two-dimensional DCT coefficient is a coefficient sequence that is made one-dimensional by zigzag scanning or the like. The variable length encoding process is performed in the following procedure. First, the coefficient sequence is converted into a combination of a run, which is the continuous number of zero coefficients, and a subsequent non-zero coefficient level. For example, 0,0,4,1,0,2,0,0,0,
The coefficient sequence of 0, 1, ... is (2, 4), (0,
1), (1, 2), (4, 1),... Next, each run level combination is subjected to variable length coding based on a predetermined conversion table.

Also, the video encoder 111A has a VLC
A buffer 206 for temporarily accumulating the video data D5 obtained by the unit 205, and a coefficient of a part or all of the coefficient sequence with respect to the entire generated code amount of the video data D5 per unit time (for example, slice layer unit). Generated code amount information generation unit 207 that generates generated code amount information D7 related to the ratio of the generated code amount occupied by, and generated code amount information D7 obtained by generation unit 207 to video data D5 read from buffer 206. Video data PESa
Information adding unit 208 for obtaining the video data PESa
And an output terminal 209 for outputting

Here, the generated code amount information D7 obtained by the generation unit 207 indicates that the ratio of the generated code amount occupied by the coefficient of the order or more to the total generated code amount of the video data D5 per unit time is a predetermined ratio. (In the present embodiment, as described later, 10%, 20%, 30%, 40%, 50%
%). Although not described above, the control unit 216 constantly monitors the data accumulation state of the buffer 206, and outputs the occupation amount information D from the buffer 206.
I got 6. The control unit 216 generates a quantization control value D16 based on the occupation amount information D6, supplies the generated quantization control value D16 to the quantization unit 204, adjusts the quantization step size in the quantization process, and responds to the accumulation state of the buffer 206. Generate the amount of data.

In the above configuration, the VLC unit 205
Variable-length coding is performed on the quantized coefficient data D4 (coefficient sequence) obtained by the quantization unit 204 to obtain coded data. Thereafter, the coded data and other variable-length coded data or fixed-length codes are obtained. Then, video data D5 as a PES packet is created by synthesizing the coded data and the like, and the video data D5 is supplied to the buffer 206 and stored.

The generated code amount information generation unit 207 outputs
In relation to the video data D5 created by the LC unit 205, a generated code based on a coefficient of a part or all of the coefficient sequence with respect to a total generated code amount of the video data D5 per unit time (for example, slice layer unit). Generated code amount information D7 related to the ratio occupied by the amount is generated. That is, the generation unit 207 determines that the ratio of the generated code amount due to the coefficient of the order or more to the total generated code amount of the video data D5 per unit time is 10%, 20%, 30%, 40%, 50%.
Information indicating the order of the coefficient sequence that becomes% is generated.

Then, the information adding unit 208
For each unit time, the corresponding generated code amount information D7 from the generation unit 207 is added to the video data D5 read from 06 to obtain video data PESa, and this video data PESa is output to the output terminal 209.

FIG. 3 shows a configuration of a circuit section 220 including a VLC section 205 and a generated code amount information generation section 207.

The circuit section 220 includes a control section 221 for controlling the entire operation and a quantized DCT from the quantization section 204.
Input terminal 222 for inputting coefficient data D4 (coefficient sequence)
And a run-level conversion unit 223 that converts the coefficient sequence into a run-level combination, and generates a variable-length code D24 (coded data) by performing variable-length coding on the run-level combination using a predetermined conversion table. And a variable-length code generation unit 224 that outputs the data. Here, the generation unit 22
The variable-length code D24 output from 4 is fixed-length width data in which each codeword is MSB (most significant bit) -packed with respect to fixed-length parallel data such as a 64-bit width. Therefore, the code length data D24a indicating the effective code length of each codeword constituting the variable length code D24 as fixed length data is also output from the generation unit 224.

The circuit unit 220 selectively takes out the variable length code D24 from the variable length code generation unit 224 and other variable length coded data, fixed length coded data, and the like, combines them, and generates a PES packet. And a selector 225 for creating the video data D5. In this case, other variable-length coded data and fixed-length coded data are also, for example, 6 bits.
Each codeword is MSB-packed fixed-length width data of fixed-length parallel data such as a 4-bit width, and is accompanied by code length data indicating the effective code length of each codeword. Therefore, the selector 225 outputs the video data D5 as the fixed length data,
Code length data D5a indicating the effective code length of each code word constituting the code word is output at the same time.

The circuit section 220 has a code length data D5
video data D as fixed-length width data based on
5, a barrel shifter 226 that takes out only valid bit data, converts it into parallel data in units of 8 bits, and obtains video data D5 to be supplied to the multiplexer 114.
And an output terminal 227 for outputting the video data D5.

The circuit unit 220 receives the quantized DCT coefficient data D 4 (coefficient sequence) input to the input terminal 222, and outputs the code length data D 2 output from the generation unit 224.
An order counter 228 counts the order of the DCT coefficient corresponding to the level indicated by the code word corresponding to 4a. In this case, in the case of data other than the DCT coefficient, a reset signal is input from the control unit 221 and the count output becomes 0.
Becomes In this case, in the degree counter 228, (run + 1) of the coefficient sequence is sequentially added.

The circuit section 220 includes the order counter 22
The order data D28, which is a count output of 8, and the code length data indicating the effective code length of each codeword constituting the variable length code D24 (encoded data) as fixed length data output from the variable length code generation unit 224 Based on D24a and code length data D5a indicating the effective code length of each codeword constituting video data D5 as fixed-length data output from selector 225, the total generated code amount of video data D5 per unit time DCT of that order or higher
10%, 20
% Information calculation unit 2 that obtains information indicating the order of the coefficient sequence of%, 30%, 40%, and 50% as generated code amount information D7.
29 and an output terminal 2 for outputting the generated code amount information D7.
30.

FIG. 4 shows the configuration of the degree information calculation unit 229. The order information calculation unit 229 includes a control unit 231
Controls the overall operation. The code length data D5a is input to the input terminal 232, the code length data D24a is input to the input terminal 233, and the order data D28 is input to the input terminal 234. Then, the input terminal 233
Is input to the input terminal IN of the data mask circuit 235, and the order data D28 input to the input terminal 234 is input to the data mask circuit 23.
5 is supplied to the control terminal CNT. Data mask circuit 2
35 has 64 output terminals OT1 to OT64.

[0068] Here, the code length indicated by the code length data D24a L, the order indicated by the order data D28 is N, further respectively DM0 _{_} 1~DMO_64 the output obtained at the output terminal OT1~OT64 data masking circuit 235 I do.
When N = 1 to 63, the data mask circuit 234
Outputs the L against DM0 _{_} 1~DMO_N, outputs 0 for all other DM0 _{_} N + 1~DMO_64,
In the case of N = 64 outputs an L for all DM0 _{_} 1~DMO_64, further in the case of N = 0 is DM0 _{_.} 1 to
It is configured to output 0 for all of DMO_64.

The output DM of the data mask circuit 235
0 _{_} 1~DMO_64 each cumulative addition circuit 236_1～2
36_64 and accumulated. Also, the input terminal 23
2 is input to the accumulator 23.
7, and the code length indicated by the code length data D5a is accumulated. Here, the cumulative addition circuits 236_1 to 236_64 and the cumulative addition circuit 237 are reset by a unit time such as a slice layer unit under the control of the control unit 231.
Therefore, as outputs of the accumulating circuits 236_1 to 236_64, DCTs of 1st to 64th order or more are output for each unit time.
Generated code amount AC_1 to AC_6 per unit time by coefficient
4 is obtained. Further, as the output of the accumulation circuit 237, the total generated code amount AC_0 per unit time of the video data D5 is obtained for each unit time.

Further, the accumulating circuits 236_1 to 236_64
The generated code amounts AC_1 to AC_64 output from the respective circuits are supplied to division circuits 238_1 to 238_64, respectively, and are divided by the generated code amounts AC_0 output from the accumulation circuit 237. As a result, the division circuits 238_1 to 238_64 output the video data D5 per unit time per unit time.
DCT of order 1 to 64 or more with respect to total generated code amount AC_0
The ratios (occupation rates) P_1 to P_64 occupied by the generated code amounts AC_1 to AC_64 due to the coefficients are obtained.

The occupancy rates P_1 to P_64 obtained by the division circuits 238_1 to 238_64 are supplied to an order information output unit 239. The order information output unit 239 includes the control unit 23
Reference occupancy from 1; 10%, 20%, 30 in this example
%, 40%, 50%. Then, in the degree information output unit 239, the division circuits 238_1 to 238_64 are used as the division circuits 1 to 64 as division circuits 1 to 64. Is detected, and the maximum value of M is output as generated code amount information D7. That is, the maximum value of M detected as described above is equal to or greater than the order of the total generated code amount of video data D5 per unit time.
10%, 2
This is information indicating the order of the coefficient sequence of 0%, 30%, 40%, and 50%. The generated code amount information D7 is output from the output terminal 2
It is output to 40.

FIG. 5 shows an example of the occupation ratio of the generated code amount by DCT coefficients of degree N or more. In this example, 10%, 20%, 30%, 40
When% and 50% are given, as shown in FIG. 6, information of order M is detected and output as generated code amount information D7.

Next, the operation of the circuit section 220 shown in FIG. 3 will be described. The quantized DCT coefficient data D4 (coefficient sequence) from the quantization unit 204 is input to the input terminal 222. The quantized DCT coefficient data D4 is supplied to the run level conversion unit 223.
And is converted to a combination of a run, which is the continued number of zero coefficients, followed by a level of non-zero coefficients.

The run-level combination from the run-level converter 223 is supplied to the variable-length code generator 224, and the run-level combination is converted into a variable-length code D24 (encoded data) using a predetermined conversion table. It is converted and output. The variable-length code D24 output from the generation unit 224 is fixed-length width data in which each codeword is MSB-packed with respect to fixed-length parallel data such as a 64-bit width. Code length data D24a indicating the effective code length of each codeword constituting the code D24 is also output.

The variable length code D24 and the code length data D24a output from the variable length code generator 224 are supplied to the selector 225. The selector 225 is further supplied with other variable-length coded data and fixed-length coded data necessary for creating video data as a PES packet. These other variable-length coded data and fixed-length coded data are also fixed-length width data in which each codeword is MSB-packed with respect to fixed-length parallel data such as a 64-bit width. It is accompanied by code length data indicating the effective code length.

In the selector 225, each piece of encoded data is selectively extracted and synthesized, and video data D5 as a PES packet is created and output. The video data D5 is also fixed-length data in which each code word is MSB-packed, and code length data D5a indicating the effective code length of each code word is output at the same time. The video data D5 and the code length data D5a as fixed length data output from the selector 225 are
26.

In the barrel shifter 226, the code length data D
Based on 5a, only valid bit data is extracted from video data D5 as fixed-length data, converted into 8-bit parallel data, and video data D5 to be supplied to multiplexer 114 is obtained. And
This video data D5 is output to the output terminal 227.

The quantized DCT coefficient data D4 input to the input terminal 222 is supplied to an order counter 228. The order counter 228 indicates a code word corresponding to the code length data D24a output from the generator 224. The order of the DCT coefficient corresponding to the level is counted.
The order data D28, which is the count output of the order counter 228, is supplied to the order information calculation unit 229.

The order information calculation unit 229 indicates the effective code length of each code word constituting the variable length code D24 (coded data) as fixed length data output from the variable length code generation unit 224. The code length data D24a and the code length data D5a indicating the effective code length of each code word constituting the video data D5 as the fixed length data output from the selector 225 are supplied. Then, in the order information calculation unit 229, the order data D28 and the code length data D24
a, D5a, the ratio of the generated code amount by the DCT coefficient of the order or more to the total generated code amount of the video data D5 per unit time is 10%, 20%, 3%.
Information indicating the order of the coefficient sequence of 0%, 40%, and 50% is obtained as generated code amount information D7 (see FIG. 4). Then, the generated code amount information D7 is output to the output terminal 230.

The above is a description of the configuration of the video encoder 111A. Although the detailed description is omitted, the video encoders 111B and 111C are also used as the video encoder 111A.
A is configured similarly to A (see FIG. 2). Therefore,
Multiplexer 11 from video encoders 111B and 111C
The video data PESb and PESc to be supplied to the multiplexor 4 also have generated code amount information D7 added thereto, similarly to the video data PESa supplied to the multiplexer 114 from the video encoder 111A.

Next, the configuration of the multiplexer 114 will be described. FIG. 7 shows the configuration of the multiplexer 114.

The multiplexing device 114 outputs the video data PES output from the video encoders 111A to 111C.
input terminals 130A-1 for inputting a through PESC respectively
30C and variable-rate multiplexing buffers 132A to 132C for writing and reading video data PESa to PESc to and from the buffers, respectively, and sequentially outputting data PDa to PDc constituting TS packets.

The multiplexing device 114 outputs the data PDa
To PDc to form a TS packet by adding a packet header and adding a parity for error correction,
Thereafter, a multiplexing circuit 133 for multiplexing each TS packet to form a transport stream TS, and an output terminal 134 for outputting the transport stream TS
And a multiplexing control unit 13 for controlling the operations of the variable-rate multiplexing buffers 132A to 132C and the multiplexing circuit 133.
5 and an input terminal 136 for inputting the transmission rate information TRI supplied from the transmission device 115 (see FIG. 1). Transmission rate information TR input to input terminal 136
I is supplied to the multiplexing control unit 135.

FIG. 8 shows a variable rate multiplexing buffer 132.
2 shows the configuration of A. The variable rate multiplexing buffer 132A includes an input terminal 151 to which the video data PESa is input, a delay unit 152 for adjusting the video data PESa input to the input terminal 151 by a predetermined time, and a delay unit 152. And a parallel data buffer 153 for writing and accumulating the video data PESa delayed in 152. Here, the buffer 153 has a data storage amount detection function, and the storage amount information DSI is supplied to the multiplexing control unit 135.

The variable rate multiplexing buffer 132A
Has a data analysis unit 154. Data analysis unit 1
54 is the video data PE supplied to the input terminal 151.
The generated code amount information D7 is obtained from Sa, and the variable-length code D24 (coded data) included in the video data PESa is decoded into a combination of run levels, so that which part of the video data PESa has It is analyzed whether the data is related to DCT coefficients. The data analysis unit 154 uses the generated code amount information D7 to
Bit enable data D1 to D5 indicating validity / invalidity of bit data of each byte of the video data PESa stored in the buffer 153 corresponding to the data reduction rates of%, 20%, 30%, 40%, and 50%. Generate

As described above, the generated code amount information D7 is
When the occupancy is information of the order M of the DCT coefficient corresponding to 10%, 20%, 30%, 40%, and 50% (see FIG. 6), the data analysis unit 154 determines whether the video data PESa has 37 or more orders. 26 or higher, 21 or higher, 14 or higher, 8
The bit enable data D1 to D5 are generated such that the portions related to the DCT coefficients higher than the next are invalidated.
For data D1 to D5, for example, "1" indicates valid,
“0” indicates invalid.

The data analyzer 154 detects the start synchronization code SCD from the video data PESa. As is well known, the encoded data of MPEG2 video has a hierarchical structure from a sequence layer to a block layer.
In addition, a synchronization start code is provided at the head above the slice layer. Each synchronization code is composed of 4 bytes, and the first 3 bytes are “00 00 01 (H)”. Therefore, the data analysis unit 154 detects the start synchronization code by detecting the 3-byte portion by a method such as pattern matching.

The variable rate multiplexing buffer 132A
Are the data D1 to D output from the data analysis unit 154.
5 is written in byte units and stored in bit enable buffers 155 _{-1 to} 155 _-5, and under the control of the multiplexing control unit 135, the buffer 155 corresponding to the data storage amount.
Data D1 to D read from _{-1 to} 155 _-5 respectively
5, an enable control unit 156 for selectively taking out one of data D0 (all bit data is “1” and byte data obtained in the enable control unit 156) corresponding to the reduction rate of 0%, and a buffer. A rate conversion unit 157 that discards invalid bit data from the bit data of each byte of the video data PESa read from the 153 using the bit enable data D extracted by the enable control unit 156.

The reading of the stored data from the buffer 153 is performed under the control of the multiplexing control unit 135. Writing and reading of the buffers 155 _{-1 to} 155 _-5 are performed corresponding to writing and reading of the buffer 153. The delay time of the delay unit 152 is set in the rate conversion unit 157 so that the bit enable data D corresponding to the bit data of each byte of the video data PESa supplied from the buffer 153 is supplied. .

The variable rate multiplexing buffer 132A
Is a barrel shifter 158 that converts output data of the rate conversion unit 157, that is, valid bit data of each byte of the video data PESa into parallel data in byte units to obtain data PDa as output data,
An output terminal 159 for outputting Da and a data analysis unit 154;
The operation of the barrel shifter 158 is controlled based on the detection output SCD of the start synchronization code from the
And a byte alignment unit 160 that determines that the data PDa output from 58 is byte data completed before the start synchronization code.

As described above, the rate converter 157 discards invalid bit data from the bit data of each byte of the video data PESa. Specifically, in the rate conversion unit 157, corresponding to each byte data of the video data PESa, the effective bit data is packed on the MSB side, and the other bit data is “0”.
The byte data BYD and effective bit data length information N are generated. The barrel shifter 158 uses the byte data BYD and the data length information N supplied from the rate converter 157 to form parallel data in byte units.

FIG. 9 shows an example of the configuration of the rate conversion section 157. The rate conversion unit 157 includes a 1-bit switching unit 171 to an 8-bit switching unit 178 and a ROM table 17.
9. The bit data of each byte of the video data PESa and a ₇ ~a _0, the bit data of each bit enable data D bytes and b ₇ ~b _0.

The 1-bit switching section 171 is supplied with a ₀ as an input signal, b ₀ as a control signal,
The output signals of the 1-bit switching unit 171 to 7-bit switching unit 177 and a _{1 to} a ₇ are supplied as input signals to the bit switching unit 172 to 8-bit switching unit 178, respectively, and b ₁
~b ₇ is supplied as a control signal, and byte data BYD (c ₇ ~c ₀₎ from 8-bit switching unit 178 is output. Also, as an input signal of the ROM table 179, b
_{7 to} b ₀ are supplied, and b _{7 is obtained} from the ROM table 179.
Data length information N indicating the number of "1" is output out of ~b _0.

FIG. 10 shows the configuration of the 1-bit switching section 171. The 1-bit switching section 171 is a changeover switch having two fixed terminals f ₀ and f ₁ and one movable terminal g ₁ . Fixing the terminal f ₀ is supplied to "0", the fixed terminal f ₁ is supplied with the input signal a _0, the output signal from the movable terminal g ₁ is derived. When the control signal b ₀ is “1”, the movable terminal g ₁ is connected to the fixed terminal f ₁ and the input signal a
₀ is directly derived as an output signal. On the other hand, when the control signal b ₀ is “0”, the movable terminal g ₁ becomes the fixed terminal f ₀
And “0” is derived as an output signal. FIG.
1 indicates the relationship between the signals of the 1-bit switching unit 171.

FIG. 12 shows the configuration of the n (n = 2 to 8) bit switching section 170. This n-bit switching unit 170
Are (n + 1) fixed terminals f ₀ , f ₁ , f ₂ ,..., F
_n−1 , f _n and n movable terminals g ₁ , g ₂ ,.
g _n-1 and g _n . Fixed terminal f
₀ is supplied with “0”, and the fixed terminals f ₁ , f ₂ ,.
f _n-1 and f _n are input signals I ₁ , I ₂ ,.
_n-1, I _n is supplied, the movable terminal _{g 1, g 2, ···,} g
_n-1, g _n each output signal from the _{O 1, O 2, ···,} O n-
_1, O _n is derived.

For example, in the case of the 2-bit switching section 172, it is a changeover switch having three fixed terminals I ₀ , I ₁ , I ₂ and two movable terminals g ₁ , g ₂ . Then, fixed to the terminal f ₀ is supplied to "0", is further supplied the output signal of the 1-bit switching unit 171 is the fixed terminal f ₁ as the input signal I ₁ is fed a ₁ as the input signal I _2, Output signals O ₁ and O ₂ are derived from the movable terminals g ₁ and g ₂ .

For example, in the case of the 8-bit switching unit 178, nine fixed terminals f ₀ , f ₁ , f ₂ ,.
₈ and eight changeover terminals g ₁ , g ₂ ,..., G ₈ . The fixed terminal f ₀ is “0”
Are supplied to the fixed terminals f ₁ , f ₂ ,..., F _7, and the output signals O ₁ , O ₂ ,.
·, O ₇ each input signal I _1, I _2, ···, supplied as I _7, a ₇ is supplied as an input signal I _8, the movable terminal g _1, g _2, ···, from g ₈ Each byte data B
Output signals O ₁ , O ₂ ,... Constituting YD [c _{0 to} c ₇ ]
O ₈ is derived.

When the control signal is "1", the movable terminal g
_{1, g 2, ···, g} n-1, g n are each fixed terminal f _1,
f ₂ ,..., f _n−1 , f _n and input signals I ₁ , I
_{2, ···, I n-1} , the output signal I _n is as O _1, O _2,
..., Is derived as O _n-1, O _n. On the other hand, when the control signal is “0”, the movable terminals g ₁ , g _{2 ,.
1,} g _n are each fixed terminal _{f 0, f 1, ···,} f n-2,
f _n−1 , “0” is derived as the output signal O ₁ , and the input signals I ₁ ,..., In _-2 , In _-1 are output signals O ₂ ,. It is derived as O _n-1, O _n. FIG. 13 shows the relationship between the signals of the n-bit switching unit 170. Note that I ₀ = “0”.

FIG. 14 shows an example of operation of the rate conversion section 157 for obtaining byte data BYD. This example, bit data of the video data PESa [a ₇ ~a _0] is [10
In 110111, bit data [b ₇ ~b ₀ bits enable data D] is an example of a case where the [00,101,110]. In this case, the byte data BYD [c ₇ to
[1011000] is generated as [c ₀ ]. This valid bit data of the bit data [a ₇ ~a _0] is M
It is packed on the SB side, and the other bit data is set to “0”. In this case, the data length information N output from the ROM table 179 indicates 4.

FIG. 15 shows the data stored in the bit enable buffer and the parallel data buffer 153 selected by the enable control unit 156, the output data of the rate conversion unit 157, and the output data of the barrel shifter 158. An example is shown.

Next, the operation of the variable rate multiplex buffer 132A shown in FIG. 8 will be described. The video data PESa input to the input terminal 151 is supplied to the parallel data buffer 153 via the delay unit 152, written and stored in byte units. The video data PESa input to the input terminal 151 is transmitted to the data analysis unit 154.
To obtain the generated code amount information D7, and analyze which part of the video data PESa is the data related to the next DCT coefficient.

The data analysis section 154 uses the generated code amount information D7 and the analysis result to calculate 10%, 2%
The video data P stored in the buffer 153 described above corresponds to the data reduction rates of 0%, 30%, 40%, and 50%.
Bit enable data D1 to D5 indicating validity / invalidity of bit data of each byte of ESa are generated. The bit enable data D1 to D5 are supplied to the bit enable buffers 155 _{-1 to} 155 _-5 and written and stored in byte units.

The stored data in the buffer 153 and the bit enable data in the buffers 155 _{-1 to} 155 _-5 are read out synchronously under the control of the multiplexing control unit 135. Then, any one of the data D1 to D5 read from the buffers 155 _{-1 to} 155 _-5 and the data D0 (byte data in which all the bit data is “1”) corresponding to the reduction rate of 0% is an enable control unit. At 156, the data is selectively extracted and supplied to the rate converter 157.

In the rate converter 157, invalid bit data is discarded from the bit data of each byte of the video data PESa read from the buffer 153 by using the bit enable data D extracted by the enable controller 156. That is, in the rate conversion unit 157, corresponding to each byte data of the video data PESa, the valid bit data is packed on the MSB side, and the other bit data is the byte data BYD and the valid bit of “0”. Data length information N is generated.

The byte data BYD generated by the rate converter 157 and the data length information N of valid bits are supplied to a barrel shifter 158. In the barrel shifter 158, the valid bit data of each byte of the video data PESa is converted into parallel data in byte units based on the byte data BYD and the data length information N, and data PDa as output data is obtained. Then, the data PDa is output to the output terminal 159.

Here, the data analysis unit 154 detects the start synchronization code of the encoded code of MPEG2 from the video data PESa, and the operation of the barrel shifter 158 is controlled by the byte alignment unit 160 based on the detected output SCD. As a result, the data PDa output from the barrel shifter 158 is one in which the byte data is completed before each start synchronization code.

Although not described above, the reading of the stored data from the buffer 153 is limited by the reading of the stored data in another variable-rate multiplex buffer and the transmission rate indicated by the transmission rate information TRI. When the amount of data stored in the buffer 153 increases, the multiplexing control unit 135 controls the enable control unit 15.
In 6, the bit enable data having the higher data reduction rate is selected, and the data amount is reduced. in this case,
Bit enable data with a higher data reduction rate is selected as the data storage amount increases. This suppresses an increase in the amount of data stored in the buffer 153, and prevents an increase in delay time during multiplexing.

As described above, in the variable rate multiplexing buffer 132A shown in FIG. 8, the bit enable data of a predetermined data reduction rate is selected by the enable control unit 156 in accordance with the accumulation amount of the parallel data buffer 153, The conversion unit 157 selectively discards the bit data and performs rate conversion. For example, when the data storage amount increases, DCT coefficients of a predetermined order or higher are discarded, and the data amount is reduced.

In this case, based on the generated code amount information D7 added to the video data PESa, the bit enable data D1 to D1 supplied to the enable control unit 156 are stored.
D5 sets the data amount to 10%, 20%, 30%,
It is formed so as to reduce by 40% and 50%. Therefore, conversion to the predetermined rate is easily and quickly performed. Therefore, an increase in the amount of data stored in the buffer 153 is effectively suppressed, an increase in delay time during multiplexing is avoided, and inconveniences such as synchronization failure on the receiving side due to the increase can be satisfactorily prevented.

Returning to FIG. 7, although detailed description is omitted, the variable rate multiplexing buffers 132B and 132C are also configured in the same manner as the above-described variable rate multiplexing buffer 132A, operate in the same manner, and operate on data PDb and PDc. Are sequentially output.

The operation of the multiplexer 114 shown in FIG. 7 will be described. Video data PESa is supplied from an input terminal 130A to a variable rate multiplexing buffer 132A, and data PDa constituting a TS packet is sequentially output from the variable rate multiplexing buffer 132a. Also, input terminal 1
30B, the video data PESb is supplied to the variable-rate multiplex buffer 132B, and the data PDb constituting the TS packet is supplied from the variable-rate multiplex buffer 132b.
Are sequentially output. Further, the video data PESC is input from the input terminal 130C to the variable rate multiplexing buffer 132C.
Is supplied, and the data PDc constituting the TS packet is sequentially output from the variable rate multiplex buffer 132C.

Variable rate multiplex buffers 132A to 132
Data PDa to PDc output from 2C are supplied to the multiplexing circuit 133. In this multiplexing circuit 133, a packet header is added to each of the data PDa to PDc, and a parity for error correction is added to form a TS packet. In the multiplexing circuit 133, the TS packets formed from the data PDa to PDc are multiplexed to form a transport stream TS.
4 is derived.

As described above, in the first embodiment, the video data PESa-PESc output from the video encoders 111A-111C are all generated per unit time and per unit time. Information indicating the order of the coefficient sequence in which the ratio of the generated code amount by the DCT coefficient of the order or more to the code amount is 10%, 20%, 30%, 40%, and 50% is the generated code amount information D7. Has been added. Therefore, the variable rate multiplexing buffers 132A to 132C can easily and quickly convert to a predetermined rate using the generated code amount information D7. Therefore, an increase in the amount of data stored in the buffer 153 is effectively suppressed, an increase in delay time during multiplexing is avoided, and an inconvenience such as a synchronization failure on the receiving side due to the increase can be satisfactorily prevented.

The variable rate buffer 1 shown in FIG.
In 32A, the data analysis unit 154 refers to the generated code amount information D7 to refer to 10%, 20%, 30%, 40%,
Corresponding to 50% of the data reduction factor to produce a bit enable data D1~D5 indicating a valid or invalid bit data of each byte of the video data PESa accumulated in the buffer 153, the buffer 155 _-1 to enabled controller 156
155 _-5 data are read from each D1~D5 and D0 are configured to selectively take out rate conversion to either (all-bit data byte data is "1").

However, separately from this, the data analysis unit 15
In step S4, bit enable data D1 to D64 for discarding DCT coefficients of order 1 to 64 or higher are generated, and the enable control unit 156 refers to the generated code amount information D7 to generate data D1 to D64 and D0 ( It is also conceivable to adopt a configuration in which one of the bit data in which all the bit data is “1” is selectively extracted and the rate conversion is performed.

The video encoder 111A shown in FIG.
In the video data PESa, the ratio of the generated code amount by the DCT coefficient of the order or more to the total generated code amount per unit time is 10%, 20%, 30%.
%, 40%, and 50% are added and output as generated code amount information D7.

However, as the generated code amount information D7, information indicating the ratio of the generated code amount of the DCT coefficients of the order or more to the total generated code amount per unit time in part or all of the order of the coefficient sequence. Alternatively, information indicating the ratio of the generated code amount occupied by DCT coefficients of a part or the whole order of the coefficient sequence to the entire generated code amount per unit time may be output. Further, as the generated code amount information D7, information indicating the generated code amount by the DCT coefficients of a part or the whole order of the coefficient sequence per unit time may be output. In these cases, in the multiplexer 114, the generated code amount information D7 is appropriately processed, converted into necessary information, and used.

Next, a second embodiment of the present invention will be described. FIG. 16 shows a configuration of a data conversion device 300 according to the second embodiment.

This data converter 300 converts video data PESe as a PES packet including encoded data obtained by subjecting a coefficient sequence of DCT coefficients obtained by performing DCT processing to a video signal to variable length coding (video data shown in FIG. 3). D
5), and a data conversion unit 302 that performs data conversion processing on the video data PESe. The data conversion process in the data conversion unit 302 is, for example, a rate conversion process or a format conversion process. The video data PESe may be data output from a video encoder, or data reproduced by a reproducing device such as a disk device.

The data converter 300 also has a delay section 303 for delaying the converted video data D32 output from the data converter 302 by a predetermined time to obtain output video data D33, and an output terminal for outputting the video data D33. 304. Here, the delay unit 3
Reference numeral 03 is provided for time adjustment so that the code amount information D38 obtained for each unit time by the degree information calculation unit 308 described later corresponds to the video data D33.

The data conversion device 300 detects the start synchronization code from the converted video data D32 output from the data conversion unit 302 by a method such as pattern matching, analyzes the header information, and performs a unit of slice layer unit. Every time, the total code amount AC of the converted video data D32
_0 and outputs a reset signal R every unit time.
It has a control unit 305 that outputs E.

The data conversion device 300 has a VLD unit 306 for processing the converted video data D32 output from the data conversion unit 302. This VLD unit 30
6 detects the code length of each codeword constituting the coded data included in the converted video data D32, that is, the coded data obtained by performing variable length coding on the coefficient sequence of the DCT coefficients, and code length data indicating the code length. D36a is output. Also, V
The LD unit 306 decodes the encoded data into a combination of run levels, and outputs run level combination information. Further, the VLD unit 306 outputs a DCT block flag indicating that the encoded data portion of the converted video data D32 is valid and the other portions are invalid.

Further, data conversion apparatus 300 performs VLD section 306 based on the run level combination information and DCT block flag output from VLD section 306.
It has an order count 307 for counting the order of the DCT coefficient corresponding to the level indicated by the code word corresponding to the output code length data D36a. In this case, DCT
In a period in which the block flag indicates valid, (run + 1) is cumulatively added, while in a period in which the DCT block flag indicates invalid, the count value is reset to 0.

The data conversion device 300 outputs the order data D37, V, which are the count outputs of the order counter 307.
Based on the code length data D36a output from the LD unit 306, the total code amount AC_0 output from the control unit 305, and the reset signal RE, the total code amount AC_0 of the converted video data D32 per unit time in slice layer units is calculated. The order information calculation unit 308 that obtains, as the code amount information D38, information indicating the order of the coefficient sequence in which the DCT coefficient of the order or more occupies the code amount of 10%, 20%, 30%, 40%, and 50%. And an output terminal 309 for outputting the code amount information D38.

Here, although the detailed description of the order information calculating section 308 is omitted, the order information calculating section 22 shown in FIG.
9 is configured in the same manner. In this case, the order data D37 is input to the input terminal 234, and the code length data D36a is input to the input terminal 233. Also, since the total code amount AC_0 is supplied from the control unit 305, the cumulative addition circuit 23
The part 7 is unnecessary. Thereby, the division circuit 238_1
238_64, the total code amount AC_0 of the converted video data D32 per unit time is 1 to
Code amount AC_1 to AC_64 by DCT coefficient of 64 order or more
(Occupation ratio) P_1 to P_64 are obtained, and the above-mentioned code amount information D38 is obtained at the output terminal 240.

Next, the data converter 300 shown in FIG.
Will be described. The video data PESe input to the input terminal 301 is supplied to the data conversion unit 302. In the data conversion unit 302, a rate conversion process and a format conversion process are performed on the video data PESe to obtain converted video data D32. The converted video data D32 is delayed by a predetermined time in the delay unit 303,
The output video data D33 is output to the output terminal 304.

The converted video data D32 output from the data converter 302 is supplied to the controller 305.
The control unit 305 converts the converted video data D3
2, the start synchronization code is detected by a method such as pattern matching, the header information is analyzed, and the converted video data D32, that is, the total code amount AC_0 of the output video data D33 is output for each unit time in slice layer units. And a reset signal RE is output for each unit time. The total code amount AC_0 and the reset signal RE
Is supplied to the degree information calculation unit 308.

The converted video data D32 output from the data conversion unit 302 is supplied to the VLD unit 306. The VLD unit 306 converts the converted video data D32
Is detected, the code length of each codeword constituting the coded data obtained by performing variable length coding on the coefficient sequence of the DCT coefficients is detected, and code length data D36a indicating the code length is output. This code length data D36a is output to the degree information calculation unit 308.
Supplied to

The VLD section 306 decodes the encoded data into a combination of run levels, outputs run level combination information, and outputs the run level combination information in the converted video data D32 in the encoded data portion. A DCT block flag indicating valid and invalid during other periods is output. The run level combination information and the DCT block flag are supplied to the degree counter 307. Then, the order counter 307 counts the order of the DCT coefficient corresponding to the level indicated by the code word corresponding to the code length data D36a based on the information of the combination of the run levels and the DCT block flag. The count output of the order counter 307 is supplied to the order information calculation unit 308 as order data D37.

Then, the order data calculation unit 308 calculates the order data D37, the code length data D36a, and the total code amount AC.
Based on the reset signal RE and the reset signal RE, the ratio of the code amount by the DCT coefficient of the order or more to the total code amount AC_0 of the converted video data D32 per unit time of the slice layer unit is 10%, 20%, 30%. %, 40%, 5
Information indicating the order of the coefficient sequence that becomes 0% is obtained for each unit time. This information is output to the output terminal 3 as code amount information D38.
09 is output.

As described above, in the data conversion device 300 according to the second embodiment, the output video data D33 obtained by performing data conversion processing on the video data PESe is output and the unit time Every,
The order of the coefficient sequence in which the ratio of the code amount of the DCT coefficient of the order or more to the total code amount of the output video data D33 per unit time is 10%, 20%, 30%, 40%, and 50% The indicated information is output as code amount information D38.

Therefore, when the output video data D33 from the data converter 300 is supplied to, for example, a multiplexer 114 as shown in FIG.
In the variable rate multiplex buffer, conversion to a predetermined rate can be performed easily and quickly using the code amount information D38. Therefore, an increase in the amount of data stored in the buffer is effectively suppressed, an increase in delay time during multiplexing is avoided, and inconvenience such as a failure in synchronization on the receiving side due to the increase can be satisfactorily prevented.

The data converter 300 shown in FIG.
, A coefficient sequence in which the ratio of the code amount of DCT coefficients of the order or more to the total code amount per unit time is 10%, 20%, 30%, 40%, and 50% for each unit time Is output as code amount information D38.

However, as the code amount information D38, information indicating the ratio of the code amount of DCT coefficients of the order or more to the total code amount per unit time in the order of all or a part of the coefficient sequence, or the unit DCT of the order of part or all of the coefficient sequence with respect to the total code amount per time
Information indicating the ratio of the code amount occupied by the coefficient may be output. Further, as the code amount information D38, the DCT of a part or all of the order of the coefficient sequence per unit time is used.
Information indicating the code amount by the coefficient may be output. In that case, for example, in the multiplexer 114,
The code amount information D38 is appropriately processed, converted into necessary information, and used.

The data converter 300 shown in FIG.
Is to obtain the code amount information D38 corresponding to the output video data D33 obtained by performing data conversion processing on the video data PESe. Can also be obtained. In this case, a data processing device is obtained by removing the data conversion unit 302 from the data conversion device 300 shown in FIG.

In the above-described embodiment, the video data is subjected to DCT processing, and the sequence of DCT coefficients obtained by the processing is subjected to variable-length coding to obtain coded data. It is not limited to DCT.

[0137]

According to the present invention, the output data including the coded data obtained by subjecting the coefficient sequence of the orthogonal transform code to variable length coding is partially or wholly included in the coefficient sequence per unit time. Code amount information related to the code amount based on the order coefficient is generated and output in synchronization with the output data. Therefore, for example, conversion of the output data to a predetermined rate in a multiplexing device can be performed easily and quickly, an increase in the amount of data stored in a buffer can be effectively suppressed, and a delay time in multiplexing increases. Can be avoided, thereby preventing inconvenience such as synchronization failure on the receiving side.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a digital satellite broadcast system according to a first embodiment.

FIG. 2 is a block diagram illustrating a configuration of a video encoder.

FIG. 3 is a block diagram illustrating a configuration of a VLC unit and a generated code amount information generation unit.

FIG. 4 is a block diagram illustrating a configuration of an order information calculation unit.

FIG. 5 is a diagram illustrating an example of an occupation rate of a generated code amount by DCT coefficients of degree N or more.

FIG. 6 is a diagram illustrating an example of a relationship between a reference occupancy and degree information.

FIG. 7 is a block diagram illustrating a configuration of a multiplexing device.

FIG. 8 is a block diagram illustrating a configuration of a variable rate multiplex buffer.

FIG. 9 is a block diagram illustrating a configuration example of a rate conversion unit in a variable rate multiplexing buffer.

FIG. 10 is a diagram showing a configuration of a 1-bit switching unit in the rate conversion unit.

FIG. 11 is a diagram illustrating a relationship between signals of a 1-bit switching unit.

FIG. 12 is a diagram showing a configuration of an n-bit switching unit in the rate conversion unit.

FIG. 13 is a diagram illustrating a relationship between signals of an n-bit switching unit.

FIG. 14 is a diagram illustrating an operation example of a rate conversion unit.

FIG. 15 is a diagram illustrating an operation example of a rate conversion unit and a barrel shifter.

FIG. 16 is a block diagram illustrating a configuration of a data conversion device according to a second embodiment.

FIG. 17 is a diagram for explaining the configuration of an MPEG2 TS packet or PES packet.

[Explanation of symbols]

100: Digital satellite broadcasting system, 111A-
111C: video encoder, 114: multiplexing device, 115: transmitting device, 116: transmitting antenna, 117: receiving antenna, 118: receiving device, 119: monitor 120, satellite, 130A
... 130C ... input terminal, 132A-132C ...
Variable rate multiplexing buffer, 133 ... multiplexing circuit,
134: output terminal, 135: multiplexing control unit, 1
51 ... input terminal, 152 ... delay unit, 153
... Parallel data buffer, 154 ... Data analysis unit, 155 _{-1 to} 155 _-5 ... Bit enable buffer, 156 ... Enable control unit, 157 ... Rate conversion unit, 158 ... Barrel shifter 159
Output terminal, 160: byte alignment unit, 200
... input terminal, 201 ... preprocessing part, 202, 21
2 ... arithmetic circuit, 203 ... DCT unit, 204 ...
A quantizing unit, 205 VLC unit, 206 buffer, 207 generated code amount information generating unit, 208
Information addition unit, 209 output terminal, 210 inverse quantization unit, 211 inverse DCT unit, 213 frame memory, 214 motion compensation unit, 215 motion Vector detection unit, 216 ... control unit, 221 ...
Control unit, 222 ... input terminal, 223 ... run level conversion unit, 224 ... variable length code generation unit, 225 ...
.Selector, 226 ... Barrel shifter, 227 ...
Output terminal, 228: order counter, 229: order information calculation unit, 230: output terminal, 231: control unit, 232 to 234: input terminal, 235: data mask circuit, 236_1 to 236_64, 237 ...
Accumulative addition circuit, 238_1 to 238_64 division circuit,
239: order information output unit, 300: data conversion device, 301: input terminal, 302: data conversion unit, 303: delay unit, 304, 309: output terminal, 305 ..Control unit, 306... VLD unit
307: order counter, 308: order information calculation unit

Claims (40)

[Claims] A first encoding unit that orthogonally transform-codes input data to generate a coefficient sequence; and a second encoding unit that performs variable-length encoding on the coefficient sequence to obtain encoded data.
Encoding means; data output means for obtaining output data including the encoded data; code length output means for outputting the code length of each code word constituting the encoded data; and Order generating means for generating the order of the coefficient corresponding to the level indicated by each codeword; generated code amount calculating means for calculating the total generated code amount of the output data per unit time; and output from the code length output means The code length, the degree generated by the degree generating means, and the total generated code amount obtained by the generated code amount calculating means, based on the total generated code amount of the output data per unit time. Generate generated code amount information related to the ratio occupied by the generated code amount due to some or all of the order coefficients of the coefficient sequence,
A data encoding apparatus comprising: a generated code amount information output unit that outputs the generated code amount in synchronization with the output data. 2. The data encoding apparatus according to claim 1, further comprising information adding means for adding said generated code amount information to said output data. 3. The generated code amount information is a degree of the coefficient sequence in which a ratio of a generated code amount occupied by a coefficient whose order is equal to or greater than a predetermined ratio to a total generated code amount of the output data per unit time. The data encoding device according to claim 1, wherein the information is information indicating 4. The generated code amount information occupies a part or all of the order of the coefficient sequence by a generated code amount of a coefficient of the order or more of the entire generated code amount of the output data per unit time. The data encoding device according to claim 1, wherein the information is information indicating a ratio. 5. The generated code amount information is information indicating a ratio of a generated code amount occupied by coefficients of part or all orders of the coefficient sequence to a total generated code amount of the output data per unit time. 2. The data encoding device according to claim 1, wherein: 6. A first encoding means for orthogonally encoding input data to generate a coefficient sequence, and a second encoding means for performing variable length encoding on the coefficient sequence to obtain encoded data.
Encoding means; data output means for obtaining output data including the encoded data; code length output means for outputting the code length of each code word constituting the encoded data; and An order generating means for generating an order of a coefficient corresponding to a level indicated by each code word; a unit time based on the code length output from the code length output means and the order generated by the order generating means. Generating code amount information indicating a generated code amount by a coefficient of a part or all of the order of the coefficient sequence, and generating code amount information output means for outputting in synchronization with the output data. Data encoding device. 7. The data encoding apparatus according to claim 6, further comprising information adding means for adding said generated code amount information to said output data. 8. A data delay means for delaying input data including coded data obtained by subjecting a coefficient sequence of an orthogonal transform code to variable length coding by a predetermined time to obtain output data, and a data delay means included in the input data. Code length output means for outputting a code length of each code word constituting the encoded data; and an order of the coefficient sequence corresponding to a level indicated by the code word by decoding the encoded data included in the input data. The code length calculating means for calculating the total code amount of the input data per unit time; the code length output from the code length output means; and the code length generated by the degree generating means. Based on the degree and the total code amount obtained by the code amount calculation means, a code based on a coefficient of a part or the whole degree of the coefficient sequence with respect to the total code amount of the input data per unit time. Generates a code amount information relating to the percentage of occupied, the data processing apparatus characterized by comprising a code amount information output means for outputting in synchronization with the output data. 9. The data processing apparatus according to claim 8, further comprising information adding means for adding said code amount information to said output data. 10. The code amount information indicates an order of the coefficient sequence in which a ratio of a generated code amount by a coefficient of the order or more to a total ratio of the entire code amount of the input data per unit time is a predetermined ratio. 9. The data processing device according to claim 8, wherein the data is information. 11. The code amount information indicates a ratio of a code amount of a coefficient of the order or more to a total code amount of the input data per unit time in a part or the entire order of the coefficient sequence. 9. The data processing device according to claim 8, wherein the data is information. 12. The code amount information is information indicating a ratio of a code amount of a coefficient of a part or all of the coefficient sequence to a total code amount of the input data per unit time. The data processing device according to claim 8, wherein 13. A data delay means for delaying input data including coded data obtained by performing variable length coding on a coefficient sequence of an orthogonal transform code by a predetermined time to obtain output data; Code length output means for outputting a code length of each code word constituting the encoded data; and an order of the coefficient sequence corresponding to a level indicated by the code word by decoding the encoded data included in the input data. Based on the code length output from the code length output means, and the degree generated by the degree generation means, based on the order of some or all of the coefficient sequence per unit time. A code amount information output unit that generates code amount information indicating a code amount based on the coefficient and outputs the code amount information in synchronization with the output data. 14. The data processing apparatus according to claim 13, further comprising information adding means for adding said code amount information to said output data. 15. A data conversion means for performing data conversion processing on input data including coded data obtained by performing variable length coding on a coefficient sequence of an orthogonal transform code, and conversion data output from the data conversion means. Data delay means for obtaining output data by delaying the data by a predetermined time; code length output means for outputting the code length of each code word constituting the encoded data included in the conversion data; An order generating means for decoding the encoded data to generate an order of the coefficient sequence corresponding to the level indicated by each code word; a code amount calculating means for obtaining a total code amount of the conversion data per unit time; Based on the code length output from the code length output unit, the order generated by the order generation unit, and the total code amount obtained by the code amount calculation unit, a unit time A code to generate code amount information related to a ratio of a code amount by a coefficient of a part or the whole order of the coefficient sequence to a total code amount of the conversion data, and output the code in synchronization with the output data. A data conversion device comprising: a quantity information output unit. 16. The data conversion apparatus according to claim 15, further comprising information adding means for adding said code amount information to said output data. 17. The code amount information is information indicating an order of the coefficient sequence in which a ratio of a code amount by a coefficient of the order or more to a total ratio of the code amount of the conversion data per unit time is a predetermined ratio. 16. The method according to claim 15, wherein
2. The data conversion device according to 1. 18. The code amount information indicates a ratio of a code amount of a coefficient of the order or more to a total code amount of the conversion data per unit time in a part or all of the order of the coefficient sequence. The data conversion device according to claim 15, wherein the data conversion device is information. 19. The code amount information is information indicating a ratio of a code amount occupied by coefficients of some or all orders of the coefficient sequence to a total code amount of the conversion data per unit time. The data conversion device according to claim 15, wherein 20. Data conversion means for performing data conversion processing on input data including coded data obtained by performing variable length coding on a coefficient sequence of an orthogonal transform code, and conversion data output from the data conversion means. Data delay means for obtaining output data by delaying the data by a predetermined time; code length output means for outputting the code length of each code word constituting the encoded data included in the conversion data; An order generating means for decoding the encoded data to generate an order of the coefficient sequence corresponding to the level indicated by each code word; and the code length output from the code length output means; and the order generating means Based on the generated order, code amount information indicating a code amount of a coefficient of a part or all of the order of the coefficient sequence per unit time is generated, and is synchronized with the output data. Data conversion apparatus characterized by comprising a code amount information output means for outputting Te. 21. The data conversion apparatus according to claim 20, further comprising information adding means for adding said code amount information to said output data. 22. A first input means for inputting a plurality of input data including coded data obtained by performing variable-length coding on a coefficient sequence of an orthogonal transform code; A second input unit for inputting a plurality of code amount information related to a code amount based on a coefficient of a part or the entire order of the coefficient sequence per time; and the plurality of input units based on the plurality of code amount information. A data multiplexing apparatus, comprising: a plurality of rate conversion units for performing respective rate conversions of data; and a data multiplexing unit for multiplexing output data of the plurality of rate conversion units to obtain multiplexed data. 23. The code amount information is information indicating an order of the coefficient sequence in which a ratio of a code amount by an order equal to or greater than the order is a predetermined ratio to a total code amount of the input data per unit time. 23. The method according to claim 22, wherein
3. The data multiplexing device according to 1. 24. The code amount information indicates a ratio of a code amount of a coefficient of the order or more to a total code amount of the input data per unit time in a part or all of the order of the coefficient sequence. 23. The data multiplexing device according to claim 22, wherein the data multiplexing device is information. 25. The code amount information is information indicating a ratio of a code amount of a coefficient of a part or all of the coefficient sequence to a total code amount of the input data per unit time. 23. The data multiplexing device according to claim 22, wherein: 26. The data multiplexing apparatus according to claim 22, wherein the code amount information is information indicating a code amount based on coefficients of a part or all of the coefficient sequence per unit time. . 27. A data transmission apparatus comprising: a data multiplexing unit that multiplexes a plurality of input data to obtain multiplexed data; and a data transmission unit that transmits the multiplexed data, wherein the data multiplexing unit includes: First input means for inputting a plurality of input data including coded data obtained by performing variable-length coding on a coefficient sequence of a transform code; and the coefficient sequence per unit time synchronized with the plurality of input data, respectively. Second input means for inputting a plurality of pieces of code information related to a code amount based on a part or all of the order coefficients, and a rate conversion of each of the plurality of input data based on the plurality of code amount information And a data multiplexing means for multiplexing output data of the plurality of rate converting means to obtain multiplexed data. 28. The data transmission apparatus according to claim 27, further comprising a plurality of encoders for obtaining said plurality of input data and said plurality of code amount information. 29. The data transmission apparatus according to claim 27, further comprising a plurality of data converters for obtaining said plurality of input data and said plurality of code amount information. 30. The code amount information is information indicating an order of the coefficient sequence in which a ratio of a code amount by an order equal to or higher than the order is a predetermined ratio to a total code amount of the input data per unit time. 28. The method according to claim 27, wherein
A data transmission device according to claim 1. 31. The code amount information indicates a ratio of a code amount of a coefficient of the order or more to a total code amount of the input data per unit time in a part or all of the order of the coefficient sequence. The data transmission device according to claim 27, wherein the data transmission device is information. 32. The code amount information is information indicating a ratio of a code amount occupied by coefficients of some or all orders of the coefficient sequence to a total code amount of the input data per unit time. 28. The data transmission device according to claim 27, wherein: 33. The data transmission apparatus according to claim 27, wherein the code amount information is information indicating a code amount based on coefficients of a part or all of the coefficient sequence per unit time. 34. A first encoding step of orthogonally encoding input data to generate a coefficient sequence, and a second encoding step of performing variable length encoding on the coefficient sequence to obtain encoded data.
A data output step of obtaining output data including the coded data; a code length output step of outputting a code length of each code word constituting the coded data; and An order generation step of generating an order of the coefficient sequence corresponding to the level indicated by each codeword; a generation code amount calculation step of obtaining a total generation code amount of the output data per unit time; and a code length output step. Based on the output code length, the order generated in the order generation step, and the total generated code amount obtained in the generated code amount calculation step, the total generated code amount of the output data per unit time is calculated. On the other hand, the generated code amount information related to the ratio of the generated code amount occupied by the coefficients of a part or the whole order of the coefficient sequence is generated, and the generated code amount information output is output in synchronization with the output data. Data encoding method characterized by having a degree. 35. A first encoding step of orthogonally encoding input data to generate a coefficient sequence, and a second encoding step of performing variable length encoding of the coefficient sequence to obtain encoded data.
A data output step of obtaining output data including the coded data; a code length output step of outputting a code length of each code word constituting the coded data; and An order generation step of generating an order of the coefficient sequence corresponding to the level indicated by each codeword; and the code length output in the code length output step, based on the order generated in the order generation step, Generating code amount information indicating a generated code amount by a coefficient of part or all of the order of the coefficient sequence per unit time, and a generated code amount information output step of outputting in synchronization with the output data. Characteristic data encoding method. 36. A data delay step of delaying input data including coded data obtained by subjecting a coefficient sequence of an orthogonal transform code to variable-length coding by a predetermined time to obtain output data; A code length output step of outputting a code length of each code word constituting the encoded data; and an order of the coefficient sequence corresponding to a level indicated by the code word by decoding the encoded data included in the input data. The code length calculation step for calculating the total code amount of the input data per unit time; the code length output in the code length output step; and the code length output in the degree generation step. Based on the order and the total code amount obtained in the code amount calculation step, a code based on a coefficient of a part or the entire order of the coefficient sequence with respect to the total code amount of the input data per unit time. It generates a code amount information relating to the percentage of occupied data processing method characterized by having a code quantity information output step of outputting in synchronization with the output data. 37. A data delay step of delaying input data including coded data obtained by performing variable length coding on a coefficient sequence of an orthogonal transform code by a predetermined time to obtain output data; A code length output step of outputting a code length of each code word constituting the encoded data; and an order of the coefficient sequence corresponding to a level indicated by the code word by decoding the encoded data included in the input data. An order generation step of generating the code length, and the code length output in the code length output step, and the order generated in the order generation step, based on the part or all of the order of the coefficient sequence per unit time. A code amount information indicative of a code amount based on the coefficient of (i), and outputting the code amount information in synchronization with the output data. 38. A data conversion step of performing a data conversion process on input data including coded data obtained by performing variable length coding on a coefficient sequence of an orthogonal transform code, and converting the converted data obtained in the data conversion step. A data delay step of delaying by a predetermined time to obtain output data, a code length output step of outputting a code length of each code word constituting the encoded data included in the conversion data, and a code length output step of outputting the code length included in the conversion data An order generation step of decoding encoded data to generate an order of the coefficient sequence corresponding to the level indicated by each codeword; a code amount calculation step of obtaining a total code amount of the conversion data per unit time; Based on the code length output in the code length output step, the order generated in the order generation step, and the total code amount obtained in the code amount calculation step, a unit time Generates code amount information related to the ratio of the code amount occupied by coefficients of some or all of the coefficient sequence to the total code amount of the conversion data, and outputs the code amount in synchronization with the output data A data conversion method comprising an information output step. 39. A data conversion step of performing data conversion processing on input data including coded data obtained by performing variable length coding on a coefficient sequence of an orthogonal transform code, and converting the converted data obtained in the data conversion step into A data delay step of delaying by a predetermined time to obtain output data, a code length output step of outputting a code length of each code word constituting the encoded data included in the conversion data, and a code length output step of outputting the code length included in the conversion data An order generating step of decoding encoded data to generate an order of the coefficient sequence corresponding to the level indicated by each of the codewords; the code length output in the code length output step; Based on the above-described order, code amount information indicating a code amount by a coefficient of part or all of the order of the coefficient sequence per unit time is generated, and output in synchronization with the output data. Data conversion method characterized by having a code quantity information output step of. 40. A first input step of inputting a plurality of pieces of input data including coded data obtained by performing variable length coding on a coefficient sequence of an orthogonal transform code; A second input step of inputting a plurality of pieces of code amount information relating to a code amount of a coefficient of a part or the whole order of the coefficient sequence with respect to a total code amount of the plurality of input data per time; A rate conversion step of performing a rate conversion of each of the plurality of input data based on the code amount information of; a data multiplexing step of multiplexing a plurality of output data obtained in the rate conversion step to obtain multiplexed data; A data multiplexing method comprising: