JP2000150919A - Overvoltage surge protective element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an overvoltage surge protective element, which can reduce both of an operating voltage and an electrostatic capacity, and moreover has wider control range of the operating voltage and has high latitude in design. SOLUTION: This overvoltage surface protective element is provided with n+ type heavily-doped regions 21 and 22, which are exposed on both surfaces of an n- semiconductor layer 11, respectively, and are used as trigger regions involved in the layer 11 which is used as a substrate, a p+ type semiconductor layer 12 which is exposed on the surface on one side of the surfaces of the layer 11 and encircles the region 21 involved in the layer 11, an n+-type semiconductor layer 13, which is exposed on the surface on one side of the surfaces of the layer 11 and is involved in the layer 12 in such a way as to encircle the region 21 via the layer 11, a p+-type semiconductor layer 14, which is exposed on the other surface of the layer 11 and encircles the region 22 involved in the layer 11, an n+-type semiconductor layer 15, which is exposed on the other surface of the layer 11 and is involved in the layer 14 in such a way as to encircle the region 22 via the layer 11, and electrodes 31 and 32, which short-circuit the layers 13 and 15 with the layers 12 and 14.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thyristor-type overvoltage surge protection device for protecting an overvoltage surge from entering a communication line into a low-withstand-voltage integrated circuit or the like. More specifically, a thyristor-type overvoltage surge protection element having a pnpn-type or npnp-type thyristor structure, and a pn-type or pnp-type thyristor structure, and a semiconductor pn-junction breakdown mechanism of which impurity concentration is controlled by diffusion is used. It is about.

[0002]

2. Description of the Related Art Driving voltages of integrated circuits and the like tend to be lower and lower. Although the integrated circuit itself has a certain level of surge protection capability, it is essential to protect it against overvoltage surges from power supply lines and further overvoltage surges from communication lines. Since the voltage (breakdown voltage) at which the protection element starts operating is determined by the resistivity (or impurity concentration) of the starting silicon substrate, a surge protection element with a low breakdown voltage has a low resistance, that is, a silicon substrate with a high impurity concentration. I need. On the other hand, when a surge protection element is used for a communication line, it is required to have a low capacitance in order to reduce transmission loss. However, when the impurity concentration is increased, the capacitance of the silicon substrate is increased. Therefore, it is difficult to realize a low capacitance with a low-resistance silicon substrate. That is, simply controlling the impurity concentration of the silicon substrate cannot achieve both a reduction in breakdown voltage and a reduction in capacitance, and these have a trade-off relationship.

In order to improve this trade-off relation, a surge protection element whose operating voltage is controlled independently of the substrate concentration is used as a base junction (p.
A bidirectional thyristor is disclosed in which a region (buried trigger region) in which an impurity of the same type as a silicon substrate is diffused (buried trigger region) having a low breakdown voltage is provided in a part of an n-junction (for example, Japanese Patent Laid-Open No. 4-340276). The capacitance of this surge protection element is determined by the junction outside the embedded trigger area,
In addition, since the depletion layer can be greatly extended by lowering the impurity concentration in the substrate, the capacitance can be reduced. On the other hand, in order to operate at a lower voltage, a surge protection element provided with a junction (trigger region) having a high impurity concentration in the vicinity of the surface has been proposed (for example, Japanese Unexamined Patent Application Publication No. Hei 5 (1999)).
-190837, JP-A-4-106935). In these surge protection elements, breakdown occurs in a trigger region having a high impurity concentration. Therefore, the operating voltage is approximately determined by the lower impurity concentration. Further, a high breakdown voltage can be obtained by deeply diffusing the impurity in the trigger region and reducing the concentration of the junction. FIG. 8 shows a surge protection element described in Japanese Patent Application Laid-Open No. H5-190837. This surge protection element has an n ⁻ -type semiconductor layer 111 serving as a substrate, n′ ^- type semiconductor layers 118 and 119 exposed on both surfaces, and a semiconductor layer 118 exposed on one surface and overlapping the semiconductor layer 118. Layer 11
8 and p ⁺ -type semiconductor layer 112 surrounding the semiconductor layer 112 so as to surround the semiconductor layer 118 exposed on one surface
The n ⁺ -type semiconductor layer 113 included in the semiconductor layer 11 and the semiconductor layer 11 are exposed on the other surface and overlap the semiconductor layer 119.
9 and p ⁺ -type semiconductor layer 114 that surrounds the semiconductor layer 114 so as to surround the semiconductor layer 119 exposed on the other surface
N ⁺ type semiconductor layer 115 encapsulated in the semiconductor layer 11
An electrode 131 short-circuits the semiconductor layer 3 to the semiconductor layer 112, and an electrode 132 short-circuits the semiconductor layer 115 to the semiconductor layer 114. In this surge protection element, the operating voltage is controlled by the concentration and concentration gradient of the diffused impurity.

[0004]

However, the above-mentioned Japanese Patent Application Laid-Open No.
In the thyristor disclosed in JP-A-340276, in order to form a buried trigger region having a low breakdown voltage, deeper impurity diffusion is required and the impurity concentration needs to be controlled with respect to the base junction. Therefore, when the operating voltage is controlled only by the concentration of the diffused impurity,
The disadvantage is that the range of achievable operating voltages is limited.
That is, in the control range of the operating voltage obtained by performing the high-concentration deep diffusion, the upper limit is the breakdown voltage determined by the substrate concentration, and the lower limit is the extent of the impurity diffusion profile control range in the trigger region. The surge protection element disclosed in the above-mentioned Japanese Patent Application Laid-Open No. 5-190873 and the like can operate at a low voltage because a breakdown occurs at a junction having a high impurity concentration in the vicinity of the surface. Current concentrates on the narrow area of
It was difficult to obtain a high surge current resistance. Furthermore,
In the surge protection device disclosed in Japanese Patent Application Laid-Open No. 4-106935, a trigger region is provided at a portion exposed on the outer surface of the base layer, that is, at a peripheral portion of the device. In addition, there is a disadvantage that it is difficult to form a channel stopper for preventing the silicon surface from being inverted.

An object of the present invention is to provide an overvoltage surge protection element which can reduce both the operating voltage and the capacitance, has a wider control range of the operating voltage, and has a greater degree of design freedom. Another object of the present invention is to provide an overvoltage surge protection device that does not increase the size of the device and does not hinder the formation of a channel stopper.

[0006]

The invention according to claim 1 is
As shown in FIGS. 1 and 2, a first semiconductor layer 11 of a first conductivity type (n ⁻ type) serving as a substrate, and a trigger region exposed on both surfaces and included in the first semiconductor layer 11, respectively. The first and second impurity regions 21 and 22 of high concentration of the first conductivity type (n ′ type) and the first impurity region 21 exposed on one surface and included in the first semiconductor layer 11 are surrounded. The second semiconductor layer 12 of the second conductivity type (p ⁺ type) is included in the second semiconductor layer 12 so as to be exposed on one surface and surround the first impurity region 21 via the first semiconductor layer 11. A third semiconductor layer 13 of the first conductivity type (n ⁺ type) and a second impurity region 2 exposed on the other surface and included in the first semiconductor layer 11.
2 of the second conductivity type (p ⁺ type) surrounding the second semiconductor layer 1
And a fifth semiconductor of the first conductivity type (n ⁺ type) included in the fourth semiconductor layer so as to be exposed on the other surface and to surround the second impurity region 22 via the first semiconductor layer 11. Layer 15
A first electrode 31 that short-circuits the third semiconductor layer 13 to the second semiconductor layer 12, and a second electrode 32 that short-circuits the fifth semiconductor layer 15 to the fourth semiconductor layer 14. The punch-through voltage determined by the distance Y between the second semiconductor layer 12 and the distance Y between the second impurity region 22 and the fourth semiconductor layer 14 is increased by the first semiconductor layer 11, the second semiconductor layer 12, and the fourth
An overvoltage surge protection element characterized in that the voltage is lower than the withstand voltage of the pn junction between the semiconductor layers. The invention according to claim 2 is the invention according to claim 1, wherein the junctions J ₁ and J ₂ between the second semiconductor layer 12 and the fourth semiconductor layer 14 and the first semiconductor layer 11 as shown in FIG.
The overvoltage surge protection element is provided with high-concentration third and fourth impurity regions 23 and 24 of the first conductivity type (n ″ type) which become trigger regions having a lower withstand voltage than other portions. .

According to a third aspect of the present invention, as shown in FIG. 4, a first conductive type (n ⁻ type) first semiconductor layer 11 serving as a substrate is provided.
And the second conductivity type (p ⁺⁺ type) exposed on both surfaces
Of the second conductivity type (p ⁺ type) surrounding the sixth semiconductor layer 16 so as to be exposed on one surface and overlap the sixth semiconductor layer 16. A semiconductor layer 12, a third semiconductor layer 13 of a first conductivity type (n ⁺ type) which is exposed on one surface and is included in the second semiconductor layer 12 so as to surround the sixth semiconductor layer 16; The seventh semiconductor layer 17 is exposed so as to be exposed on the surface and overlap the seventh semiconductor layer 17.
Semiconductor layer 14 of the second conductivity type (p ⁺ type) surrounding
And the first conductivity type (n ⁺⁾ included in the fourth semiconductor layer 14 so as to be exposed on the other surface and surround the seventh semiconductor layer 17.
A fifth semiconductor layer 15, a first electrode 31 for short-circuiting the third semiconductor layer 13 to the second semiconductor layer 12, and a fifth semiconductor layer 1.
And a second electrode 32 for short-circuiting the first and second semiconductor layers 5 to the fourth semiconductor layer 14. The junction between the sixth semiconductor layer 16 and the seventh semiconductor layer 17 and the first semiconductor layer 11 has a lower withstand voltage than other portions. An overvoltage surge protection element characterized in that high-concentration fifth and sixth impurity regions 25 and 26 of the first conductivity type (n ′ type) serving as trigger regions are provided respectively. The invention according to claim 4 is the invention according to claim 3, wherein, as shown in FIG. 5, the second semiconductor layer 12, the junction between the fourth semiconductor layer 14 and the first semiconductor layer 11, and the other parts are formed. This is an overvoltage surge protection element provided with high-concentration third and fourth impurity regions 23 and 24 of the first conductivity type (n ″ type), which become trigger regions having a relatively low withstand voltage.

According to a fifth aspect of the present invention, as shown in FIG. 6, a first conductive type (n ⁻ type) first semiconductor layer 11 serving as a substrate is provided.
And the first conductivity type (n ′ type) exposed on both surfaces
Of the second conductivity type (p ⁺ type) surrounding the eighth semiconductor layer 18 so as to be exposed on one surface and overlap the eighth semiconductor layer 18. A semiconductor layer 12, a third semiconductor layer 13 of a first conductivity type (n ⁺ type) that is exposed on one surface and enclosed in a second semiconductor layer 12 so as to surround an eighth semiconductor layer 18; The ninth semiconductor layer 19 is exposed so as to be exposed on the surface and overlap the ninth semiconductor layer 19.
Semiconductor layer 14 of the second conductivity type (p ⁺ type) surrounding
And the first conductivity type (n ⁺⁾ included in the fourth semiconductor layer 14 so as to be exposed on the other surface and surround the ninth semiconductor layer 19.
A fifth semiconductor layer 15, a first electrode 31 for short-circuiting the third semiconductor layer 13 to the second semiconductor layer 12, and a fifth semiconductor layer 1.
And a second electrode 32 for short-circuiting the first semiconductor layer 5 to the fourth semiconductor layer 14. The second semiconductor layer 12 and the junction between the fourth semiconductor layer 14 and the first semiconductor layer 11 have a lower withstand voltage than other portions. An overvoltage surge protection element characterized in that third and fourth high-concentration third and fourth impurity regions 23 and 24 of a first conductivity type (n ″ type) serving as trigger regions are provided.

In this specification, the first semiconductor layer, the third semiconductor layer,
The semiconductor layer, the fifth semiconductor layer, the eighth semiconductor layer, the ninth semiconductor layer, and the first to sixth impurity regions are each of the first conductivity type of n-type, and the second semiconductor layer, the fourth semiconductor layer, and the sixth Although the semiconductor layer and the seventh semiconductor layer are each of the p-type, which is the second conductivity type, the present invention is not limited to this, and the first semiconductor layer,
The third semiconductor layer, the fifth semiconductor layer, the eighth semiconductor layer, the ninth semiconductor layer, and the first to sixth impurity regions are each p-type, and the second semiconductor layer, the fourth semiconductor layer, the sixth semiconductor layer, and the seventh Each of the semiconductor layers may be n-type.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In the overvoltage surge protection device according to the first aspect, the semiconductor layers 12, 1 which are p ⁺ base diffusion regions.
The operation start voltage is defined by appropriately designing the horizontal distance Y between the gate electrode 4 and the impurity regions 21 and 22 serving as trigger diffusion regions, and this breakdown voltage is used as a punch-through voltage. That is, a diffusion junction serving as an operation start region is formed in a part near the element surface, and when the depletion layer of the second semiconductor layer 12 or 14 spreads and reaches the impurity region 21 or 22, a punch for determining the operation voltage is formed. Take a through structure. In this surge protection element, the depletion layer spread by the applied voltage reaches the adjacent diffusion region to conduct. For this reason, the operating voltage can be determined according to the size of the interval Y, and the control range of the operating voltage is wider and the degree of freedom in design is increased. This surge protection element has a shorter operation time and a faster on-operation than the avalanche breakdown. If the impurity concentration of the first semiconductor layer 11 serving as the substrate is reduced and the resistance of the substrate is increased, the spread of the depletion layer of the pn junction increases, and the capacitance can be reduced. Further, by forming the impurity regions 21 and 22 serving as trigger regions inside the semiconductor layers 13 and 15 of the n ⁺ emitter, the size of the element is not increased, and the n ⁺ emitter can be sufficiently provided after breakdown in the trigger region. , And the entire device can be reliably turned on.

[0011] In the overvoltage surge protection device according to claim 2, by the base substrate junction J ₁ and J ₂ adding impurity regions 23 and 24 are embedded trigger, the second breakdown region is provided. As a result, it is possible to improve a structure in which a failure is easily caused by current concentration in the trigger region, improve a surge current withstand capability, and quickly respond to an overvoltage surge. In the surge protection element having this structure, carriers break down in the p ⁺ base layers of the semiconductor layers 12 and 14 after breakdown occurs in the impurity regions 21 and 22 of the trigger. However, base-substrate bonding J
_1, the breakdown voltage of the J ₂ is sufficiently higher than the breakdown voltage of the trigger area, the carrier after breakdown acts as a gate current, but smaller than the original breakdown voltage, the breakdown voltage of the trigger area Greater than. For this reason, after being turned on in the trigger region, it is difficult for the on region to spread over the entire device. By providing triggers (impurity regions 23, 24) at the base-substrate junctions J ₁ and J ₂ having a breakdown voltage such that carriers after turning on act as a gate current, the ON can be spread over the entire device. Therefore, a stable element operation with respect to a surge can be realized.

In the overvoltage surge protection device according to the third aspect, the semiconductor layers 16 and 17 which are p ⁺⁺ diffusion layers are overlapped with the semiconductor layers 12 and 14 which are p ⁺ base layers, and the impurity regions which are n 'trigger regions. Formed on 25, 26, the operating voltage is determined by the avalanche breakdown of the p ⁺⁺ / n 'diode in the trigger region. Semiconductor layer 1 on the surface
By providing a pn Zener diode having a low breakdown voltage, which is composed of the elements 6, 17 and the impurity regions 25 and 26, the junction is formed in the vertical direction of the element. Large, stable breakdown. In the overvoltage surge protection element according to claim 4,
By adding an embedded trigger to the structure shown in FIG. 4, the same operation and effect as the overvoltage surge protection element according to claim 2 can be obtained in addition to the operation and effect of the overvoltage surge protection element according to claim 3. In the overvoltage surge protection element according to the fifth aspect, the junction breakdown mechanism is avalanche breakdown. By adding the embedded trigger, the same operation and effect as those of the overvoltage surge protection element according to claim 2 can be obtained.

The surge protection element according to claims 1 to 5 is manufactured by planar technology. That is, a silicon oxide film having a predetermined thickness is formed on the surface of an n-type (or p-type) silicon substrate, and a part of the oxide film is removed using a photolithography technique (hereinafter, referred to as photolithography).
An impurity is diffused from there to form a base region and an emitter region sequentially. By repeating this oxidation, photolithography and diffusion a predetermined number of times, a surge protection element having a pnpn-type or npnp-type thyristor structure can be obtained. n-type (or p
Regions 23 and 24 as buried trigger regions of (type)
Is provided, the diffusion is performed first. The base diffusion layers 12 and 14 diffuse p-type (or n-type) impurities, and the emitter diffusion layers 13 and 15 diffuse n-type (or p-type) impurities. Also, an n-type (or p-type) having a small breakdown voltage
Regions 22, 22, 2, which are trigger regions of (type)
Numerals 5 and 26 diffuse n-type (or p-type) impurities of the same type as the substrate. The emitter diffusion and the trigger diffusion may be performed at the same time, but may be performed in separate diffusions in order to satisfy various characteristics of the completed surge protection device.

Although the above-mentioned diffusion method can be performed by an ion implantation method, a two-stage diffusion method is preferably used in order to perform high-concentration impurity diffusion. When a low dose that cannot be realized by thermal diffusion is required, the ion implantation method is effective. In the photolithography process before the base diffusion, a part in which the base diffusion is not performed is provided in a part of the base diffusion region. Surround the non-base diffusion and allow emitter diffusion into the base diffusion. The trigger diffusion is formed in the non-base diffusion. By providing the trigger diffusion portion in the non-base diffusion portion inside the base diffusion layer, the size of the surge protection element can be reduced as compared with the case where the trigger diffusion portion is provided outside the base diffusion layer (at the periphery of the device). There is an advantage that the formation of the stopper is not hindered. The surface of the diffusion portion of the trigger is protected by an oxide film in order to maintain electrical insulation with a metal electrode to be formed later. The metal electrode is a single electrode that short-circuits the base diffusion portion and the emitter diffusion portion exposed on the surface. Preferably, a metal electrode is formed on the oxide film above the trigger. This is to protect the oxide film from contamination in a process such as resin sealing and to prevent the oxide film from being broken by a current surge. By using a metal electrode, the element can have a high surge current withstand without a failure due to a current surge.

The operation of the overvoltage surge protection device shown in FIGS. 4, 5 and 6 can be considered as follows. When an overvoltage surge is applied to the surge protection element, avalanche breakdown occurs at the junction between the reverse-biased base diffusion layer and the trigger diffusion layer, carriers are doubled, and spread to the substrate side and the base through the trigger region. The electrons spreading on the substrate recombine with holes injected to satisfy the charge neutrality condition, and most of the generated energy becomes heat. The hole drifting in the base travels in the base immediately below the emitter, and a voltage drop occurs to bias the emitter by the base lateral resistance. This voltage drop causes carriers to be injected from the emitter. The injected electrons pass through the inside of the base layer and travel toward the substrate, thereby turning on the device.

[0016]

Embodiments The following embodiments of the present invention will be described. <Examples 1 to 4> A surge protection element shown in FIG. 1 was produced. After the silicon oxide film 11a is formed on the surface of the n-type silicon substrate 11 doped with phosphorus, a portion in the base diffusion region where no base diffusion is performed is provided in a photolithography process before the base diffusion. That is, a part of the silicon oxide film is left. Then, impurities were diffused by photolithography in the portion from which the silicon oxide film was removed to form p ⁺ -type semiconductor layers 12 and 14. Next, the semiconductor layers 13 and 15 were formed by surrounding the non-base diffusion portion and performing emitter diffusion in the base diffusion portion. Subsequently, the silicon oxide film in the non-base diffusion portion was removed, and n ′ impurity regions 21 and 22 were formed there. The trigger diffusion was performed with the impurity regions 21 and 22 spaced apart from the semiconductor layers 12 and 14 as base diffusion portions by a predetermined distance Y. That is, by limiting the diameter of the non-base diffusion region and the diameter of the trigger diffusion region, a surge protection element having a structure intended for bunch-through operation was manufactured. The surface of the trigger diffusion region is again covered with silicon oxide films 11a, 11a in order to maintain electrical insulation from metal electrodes 31 and 32 to be formed later. The metal electrodes 31 and 32 are single electrodes that short-circuit the base diffusion portion and the emitter diffusion portion exposed on the surface.

In this surge protection element, the depletion layer extending from one (base diffusion portion) reaches the diffusion layer of the other (trigger diffusion region portion) in a punch-through operation in which the junction is broken down. More specifically, a depletion layer is formed mainly in the direction of the substrate when the base is negatively biased with respect to the substrate. The spread is in the normal direction and the horizontal direction of the base-substrate junction. In this case, the width of the depletion layer extending in the horizontal direction increases as the distance from the interface of the silicon oxide film within the interval Y increases. When the depletion layer reaches the trigger diffusion region formed in the non-base diffusion region, a channel by carriers is formed, and conduction is made between the base and the substrate.

The spread width of the depletion layer of the reverse-biased junction is approximately expressed by the following equation (1) for, for example, a one-sided junction.

[0019]

(Equation 1)

Here, W is the spread width of the depletion layer, ε is the dielectric constant of silicon, q is the elementary charge, V _app is the applied voltage, and N _d is the basic impurity concentration.

FIG. 7 shows the breaks of the four types of surge protection devices of Examples 1 to 4 when the interval Y, which is the difference between the non-base diffusion portion and the trigger diffusion portion, is changed to three values of 10 μm, 20 μm and 30 μm. This shows a situation where the down voltage changes. Surge protection device of Example 1 is a resistance 324Ω semiconductor layer 12 or 14 of FIG. 1 (p ⁺ base layer), n ^-
Has an impurity concentration of 2 × 10 ¹⁴ / cm ³ . In the surge protection element of the second embodiment, the resistance of the p ⁺ base layer is 138Ω, and the impurity concentration of the n ⁻ semiconductor layer 11 is 1 × 10 ¹⁵ / cm ³ . In the surge protection element of the third embodiment, the resistance of the p ⁺ base layer is 136Ω and the impurity concentration of the n ⁻ semiconductor layer 11 is 2 × 10 ¹⁴ / cm ³ . Furthermore, the surge protection element of the fourth embodiment has a resistance of the p ⁺ base layer of 11
6 Ω, and the impurity concentration of the n ⁻ semiconductor layer 11 is 2 ×
10 ¹⁴ / cm ³ . What differs between the four types of surge protection elements of Examples 1 to 4 is the impurity concentration of the p ⁺ base layer, and this impurity concentration is measured as the sheet resistance. The higher the impurity concentration, the lower the sheet resistance.

As is clear from FIG. 7, the operating voltage increases as the sheet resistance increases (the impurity concentration decreases). Theoretically, if the impurity concentration of the n ⁻ semiconductor layer 11 and the interval Y are determined, the breakdown voltage is uniquely determined. However, in reality, diffusion is simultaneously performed in the lateral direction (Y direction). Therefore, the effective width W of the depletion layer differs in each case. As a result, when the impurity concentration of the p ⁺ base layer is high (the sheet resistance is low), the diffusion in the lateral direction is large, and the spread width W of the depletion layer is smaller than the design value.
The breakdown voltage becomes smaller. Further, the sheet resistance is almost the same (1) as in the element of the second embodiment and the element of the third embodiment.
38 Ω and 136 Ω), the device of Example 3 in which the impurity concentration of the n ⁻ semiconductor layer 11 as the substrate is low is lower than that of the device of Example 2 in which the impurity concentration is high. Since the spread width W is large, breakdown occurs at a lower voltage. From the above, it can be seen that the breakdown voltage changes depending on the interval Y. That is, a channel is formed when the width W of the depletion layer proportional to the square root of the applied voltage becomes equal to the interval Y. By using these data and the theoretical formula, a design value of a predetermined breakdown voltage becomes possible on the mask. In addition, since the element shifts to the ON state due to the expansion of the depletion layer, the response time is improved and the surge response characteristic is improved.

Example 5 A surge protection device shown in FIG. 4 was manufactured. Semiconductor layer 12 which is ap ⁺ base diffusion region
Semiconductor layers 16 and 17, which are p ⁺⁺ diffusion layers, were formed on impurity regions 25 and 26, which are n ⁺ triggers, in the non-base diffusion portion so as to overlap with N and. This gives p ⁺⁺
A / n ′ junction Zener diode was formed, and a surge protection element whose operating voltage was determined by the breakdown of the Zener diode was obtained. Further, p ⁺⁺ diffusion layers 16 and 17 are added to the surge protection element manufactured in Example 1 to trigger n ′ diffusion regions 25 and 2.
6 so as to overlap with the semiconductor layers 12 and 14, which are base diffusion regions surrounding the periphery, so that a seven-layer structure of pnpnpnp (semiconductor layer 16 → impurity region 25 → semiconductor layer 12) is formed in the longitudinal direction of the surge protection element. → Semiconductor layer 11
→ the semiconductor layer 14 → the impurity region 26 → the semiconductor layer 17). The diffusion junction that determines the operating voltage is the p ⁺⁺ diffusion layer 16,
17 and trigger n 'diffusion regions 25 and 26. These diffusion regions are highly concentrated with respect to each other and avalanche breakdown occurs at low voltages. The p ⁺⁺ diffusion that spreads over the trigger n 'is
At the same time, a diffusion region for increasing the base surface concentration may be used.

Example 6 A surge protection element shown in FIG. 3 was manufactured. In the manufacturing method of this structure, the impurity regions 23 and 24, which are the second trigger regions that cause a breakdown at a higher operating voltage than the breakdown voltage of the trigger-base junction to be operated first, are connected to the base-substrate junctions J ₁ and J ₂ Formed. This second trigger area may be the same as the conductivity type of the substrate. After the formation of the second trigger region, an impurity region 21 which is a first trigger region having a low breakdown voltage is formed near the surface according to the manufacturing method described in the first embodiment. With such a structure, first, the trigger portion near the surface causes breakdown due to punch-through, and electrons and holes travel in the substrate and the base, respectively. The hole running in the base serves as a gate current for breaking down the second trigger region formed in the base-substrate junction. The current path after the breakdown becomes a path that passes through the trigger section near the surface and the second trigger section, so that the current does not concentrate only on the trigger section, the characteristic against the overvoltage surge is improved, and especially the current that does not break down the element. The surge current resistance indicating the size is remarkably improved.

In the surge protection device shown in FIG. 6, during operation, the trigger portion near the surface first causes breakdown breakdown due to avalanche, and electrons and holes travel in the substrate and the base, respectively. Hereinafter, the same operation as described above is performed.

[0026]

As described above, the operating voltage of the surge protection element, which was conventionally determined by the substrate concentration, is determined by the pn junction formed near the element surface by impurity diffusion.
A surge protection element that operates at a low voltage can be realized. In such a structure, the capacitance is low because the substrate concentration is low, and the trade-off relationship between the operating voltage and the capacitance can be improved. In addition to controlling the operating voltage by controlling the impurity concentration by diffusion, by appropriately designing the horizontal distance Y between the base diffusion region and the trigger diffusion region, the operation start voltage can be set in a wide range, By estimating the operating voltage at the element design stage, the degree of freedom in design is greatly increased.

By providing the second trigger (embedded trigger) at the junction between the second and fourth semiconductor layers and the first semiconductor layer, a stable breakdown operation occurs. The operation can be achieved, and in particular, the surge current withstand capability can be significantly improved. In particular, even if the surge protection element has multiple terminals, it can be applied immediately, and a trigger section is formed at a junction that determines the operating voltage between any two terminals.
The operating voltage can be selected for each terminal, and the device can be used as a device having a desired operating voltage. This eliminates the need to prepare the same number of products as the operating voltage, thereby eliminating the need for productivity and inventory management. .

[Brief description of the drawings]

FIG. 1 is a sectional view of the surge protection device according to FIG.
Line sectional view.

FIG. 2 is a plan view of the surge protection element of FIG. 1 from which a silicon oxide film and electrodes are removed.

FIG. 3 is a sectional view of the surge protection element according to claim 2;

FIG. 4 is a sectional view of a surge protection element according to claim 3;

FIG. 5 is a sectional view of the surge protection element according to claim 4;

FIG. 6 is a sectional view of the surge protection element according to claim 5;

FIG. 7 is a diagram showing a situation in which the breakdown voltage of the surge protection element changes when the interval Y, which is the difference between the non-base diffusion part and the trigger diffusion part, is changed in the first embodiment.

FIG. 8 is a cross-sectional view of a conventional surge protection element.

[Explanation of symbols]

Reference Signs List 11 first semiconductor layer (n ⁻ type) 12 second semiconductor layer (p ⁺ type) 13 third semiconductor layer (n ⁺ type) 14 fourth semiconductor layer (p ⁺ type) 15 fifth semiconductor layer (n ⁺ type) 16 sixth semiconductor layer (p ⁺⁺ type) 17 seventh semiconductor layer (p ⁺⁺ type) 18 eighth semiconductor layer (n 'type) 19 ninth semiconductor layer (n' type) 21 first impurity region (n ' 22) Second impurity region (n 'type) 23 Third impurity region (n "type) 24 Fourth impurity region (n" type) 25 Fifth impurity region (n' type) 26 Sixth impurity region (n ' (Type) 31 First electrode 32 Second electrode

Claims (5)

[Claims] 1. A first semiconductor layer of a first conductivity type serving as a substrate.
(11) and first and second high-concentration first and second impurity regions (21, 22) of the first conductivity type which are exposed on both surfaces and become trigger regions included in the first semiconductor layer (11), respectively. A second conductivity type second semiconductor layer (12) that is exposed on one surface and surrounds the first impurity region (21) included in the first semiconductor layer (11); The first impurity region (21) is
The second semiconductor layer is surrounded by a semiconductor layer (11).
A third semiconductor layer (13) of the first conductivity type included in (12) and a second impurity region (22) exposed on the other surface and included in the first semiconductor layer (11). A second semiconductor layer (14) of the second conductivity type and the second impurity region (22) exposed on the other surface;
The fourth semiconductor layer is surrounded by a semiconductor layer (11).
A first conductive type fifth semiconductor layer (15) included in (14), a first electrode (31) for short-circuiting the third semiconductor layer (13) to the second semiconductor layer (12), A second electrode (32) for short-circuiting the fifth semiconductor layer (15) to the fourth semiconductor layer (14); a distance between the first impurity region (21) and the second semiconductor layer (12); (Y), the second impurity region (22), and the fourth semiconductor layer
A punch-through voltage determined by an interval (Y) between the first semiconductor layer (11) and a voltage lower than a withstand voltage of a pn junction between the first semiconductor layer (11), the second semiconductor layer (12), and the fourth semiconductor layer (14). An overvoltage surge protection device characterized in that it is configured to: 2. A second semiconductor layer (12) and a fourth semiconductor layer (14).
First and second high-concentration third and fourth impurity regions (23, 24) of the first conductivity type serving as trigger regions having a lower withstand voltage than other portions are formed at the junction between the first semiconductor layer (11) and the first semiconductor layer (11). The overvoltage surge protection device according to claim 1, wherein the overvoltage surge protection device is provided. 3. A first semiconductor layer of a first conductivity type serving as a substrate.
(11) and the sixth and seventh conductive types exposed on both surfaces, respectively.
A second conductive type second semiconductor layer surrounding the sixth semiconductor layer so as to be exposed on one surface and overlap the sixth semiconductor layer;
A semiconductor layer (12), and a third semiconductor layer (13) of the first conductivity type, which is exposed on one surface and enclosed in the second semiconductor layer (12) so as to surround the six semiconductor layers (16). A fourth conductive type fourth electrode surrounding the seventh semiconductor layer (17) so as to be exposed on the other surface and overlap the seventh semiconductor layer (17).
A semiconductor layer (14) and a first conductive type fifth semiconductor layer (15) which is exposed on the other surface and is enclosed by the fourth semiconductor layer (14) so as to surround the seventh semiconductor layer (17). ), A first electrode (31) for shorting the third semiconductor layer (13) to the second semiconductor layer (12), and a short circuit for the fifth semiconductor layer (15) to the fourth semiconductor layer (14). A second electrode (32), the sixth semiconductor layer (16) and the seventh semiconductor layer (17) and the first electrode
High-concentration fifth and sixth impurity regions (25, 26) of the first conductivity type, which are trigger regions having a lower breakdown voltage than other portions, are provided at the junction with the semiconductor layer (11). An overvoltage surge protection device characterized by the following. 4. A second semiconductor layer (12) and a fourth semiconductor layer (14).
First and second high-concentration third and fourth impurity regions (23, 24) of the first conductivity type serving as trigger regions having a lower withstand voltage than other portions are formed at the junction between the first semiconductor layer (11) and the first semiconductor layer (11). The overvoltage surge protection device according to claim 3, which is provided. 5. A first semiconductor layer of a first conductivity type serving as a substrate.
(11) and the eighth and ninth of the first conductivity type exposed on both surfaces, respectively.
A second conductive type second semiconductor layer (18, 19) surrounding the eighth semiconductor layer (18) so as to be exposed on one surface and overlap the eighth semiconductor layer (18);
A semiconductor layer (12); and a third semiconductor layer (13) of the first conductivity type, which is exposed on one surface and enclosed in the second semiconductor layer (12) so as to surround the eighth semiconductor layer (18). ), A fourth of the second conductivity type surrounding the ninth semiconductor layer (19) so as to be exposed on the other surface and overlap the ninth semiconductor layer (19).
A semiconductor layer (14) and a first conductive type fifth semiconductor layer (15) which is exposed on the other surface and is included in the fourth semiconductor layer (14) so as to surround the ninth semiconductor layer (19). ), A first electrode (31) for shorting the third semiconductor layer (13) to the second semiconductor layer (12), and a short circuit for the fifth semiconductor layer (15) to the fourth semiconductor layer (14). The second semiconductor layer (12) and the fourth semiconductor layer (14) and the first electrode (32).
High-concentration third and fourth impurity regions (23, 24) of the first conductivity type, which become trigger regions having a lower breakdown voltage than other portions, are provided at the junction with the semiconductor layer (11), respectively. An overvoltage surge protection device characterized by the following.