JP2000150700A - High-density integrated circuit package - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable the components of an IC package to be protected. SOLUTION: A high-density IC package 30 comprises an opening 86, a first and second surfaces 92 and 94, and a substrate 70. The substrate 70 has a plurality of rooting strips 82 extending into the opening 86. A plurality of pads 100 are disposed on the first and second surfaces 92 and 94 and connected with at least one of the rooting strips 82. A via 84 electrically connects the pad 100 disposed on the first surface 92 with the pad 100 disposed on the second surface 94. A chip 50 is bonded to the substrate 70 having bonding pads 120. A bonding wire 80 electrically connects at least one bonding pad 120 with at least one rooting strip 82. The opening 86 is filled with potting material.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention generally relates to integrated circuits (I
C) The field of packages, and more particularly, to a substantially planar high density integrated circuit package and a method of manufacturing the same.

[0002]

BACKGROUND OF THE INVENTION Without limiting the scope of the invention,
As an example, the background will be described in connection with an IC package.

Heretofore, in this field, integrated circuits have been formed on semiconductor wafers. The wafer is divided into individual chips, which are then processed and packaged. This packaging process is one of the most important steps in the integrated circuit manufacturing process, both in terms of cost and reliability. Specifically, the cost of the package can easily exceed the cost of the IC chip, and most device failures are related to packing.

[0004] The integrated circuit is manufactured in a subsequent manufacturing process.
Also, the integrated circuit must be packaged in a suitable medium that protects the integrated circuit from the intended application environment. Therefore, wire bonding and encapsulation are two major steps in the packaging process. Wire bonding connects the leads from the chip to the terminals of the package. By this terminal
It becomes possible to connect the IC package to other components. Following wire bonding, seals are used to seal surfaces to protect against moisture and contamination, and to protect wire bonds and other components from corrosion and mechanical shock.

In the conventional method, the packing of an integrated circuit necessarily involves bonding individual chips to a lead frame, and after wire bonding and sealing, designated portions of the lead frame become package terminals. Packing an integrated circuit also involves placing the chip on a flexible board, followed by bonding and wire bonding of the chip to the surface of the flexible board, followed by sealing on the flexible board adjacent to the chip. Stops are applied to seal and protect the chips and other components.

Unfortunately, current methods of encapsulating silicon chips not only have a high failure rate due to the multi-step nature of this process, but also a problem between the encapsulant and the components of the integrated circuit. Various problems including cracks have occurred.
For example, the industry has been plagued by cracks due to differences in the coefficients of thermal expansion of different components between soldering materials at different interfaces and between metal and non-metal components. Cracks between the silicon wafer and the encapsulation material are also common, but usually this is
Also, due to extreme temperature changes between operating and non-operating periods

Another problem often arises when a sealed silicon chip is successfully assembled into a functioning integrated circuit. Once encapsulated, the silicon chip is usually surface mounted using radiant heat or steam saturation heating. However, this process can result in poor coplanarity due to irregular reflow, thereby causing integrated circuit failure.

For this reason, high-density IC packages and high-density
An IC package manufacturing process is desired. There is also a need for a process for manufacturing an integrated circuit module by laminating integrated circuit modules and IC packages together.
There is a need for materials and methods that lead to increased yields by more closely matching the coefficients of thermal expansion of the materials used in the package. Further, there is a need for a flat, high-density, double-sided IC package that protects silicon chips and wire bonding from the intended environment in which the package is intended during subsequent manufacturing and inspection processes.

[0009]

SUMMARY OF THE INVENTION The present invention disclosed herein relates to a high-density IC package and the components of the IC package during the manufacturing and inspection processes, as well as from the intended environment of use for which the package is intended. And a manufacturing process of a high-density IC package for protecting the semiconductor device. The invention also includes an integrated circuit module and a process for manufacturing an integrated circuit module with a high density double sided IC package stack.

[0010] The high density IC package of the present invention includes a substrate having an opening and first and second surfaces. A plurality of routing strips are configured with the substrate and extend into the openings.
A plurality of pads surrounding the opening on the first surface are arranged. A plurality of pads surrounding the opening on the second surface may be arranged.
At least one of the pads located on the first side and at least one of the pads located on the second side are electrically connected to at least one of the routing strips. The high-density IC package also includes at least one via that electrically connects a pad located on the first side to a pad located on the second side. A chip having bonding pads disposed on the chip is bonded to the substrate. Wire bonding electrically connects this bonding pad to the routing strip. Potting material is placed in the openings to protect this wire bonding.

[0011] The high density IC package further includes a bus bar configured with the substrate and extending into the opening. The bus bar electrically connects at least one of the bonding pads of the chip to at least one of the pads located on the first and second surfaces of the substrate.

The high-density IC package of the present invention also includes a solder ball electrically connected to a pad disposed on the surface of the substrate. At least one of the pads arranged on the second surface of one high-density IC package is electrically connected to at least one of the pads arranged on the first surface of another high-density IC package Thereby, an integrated circuit module is formed. In one embodiment, electrical connections between IC packages are made using solder balls. In another embodiment, columns are used to make electrical connections between IC packages.

The integrated circuit module may further include additional high density IC packages that are electrically connected together in a stackable manner. For example, a third high-density IC package may be electrically connected to the integrated circuit module in a stackable manner.

[0014]

BRIEF DESCRIPTION OF THE DRAWINGS For a more complete understanding of the features and advantages of the present invention, a detailed description of the present invention is provided by reference to the accompanying drawings. In these accompanying figures, corresponding numbers in different figures indicate corresponding parts.

The manner in which various embodiments of the present invention are practiced and utilized will now be discussed in detail, but the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. You should understand that. The examples discussed herein are merely illustrative of specific ways to make and use the invention and do not limit the scope of the invention.

The present invention relates to a high-frequency integrated circuit using a high-density board-on-chip design having a double-sided board, which achieves high-speed performance while meeting the space constraints of modern semiconductors. The present invention also relates to a high-frequency integrated circuit designed so that a plurality of IC packages can be stacked together for high-speed performance. For example, the principles of the present invention can be incorporated into a synchronous DRAM (SDRAM) silicon chip. However, the present invention also provides, for example, LOGIC, SRAM, EPR
It can also be applied to OM and any other integrated circuit components.

FIG. 1 is a simplified cross-sectional view of an IC package, generally indicated at 30. The IC package 30 includes a silicon chip 50. This chip, for example, DRAM,
It may be any integrated circuit component such as an EPROM, SRAM or logic chip. The printed circuit board 70 is bonded to the silicon chip 50 by the adhesive layer 60. The adhesive layer 60 may be made of, for example, a double-sided adhesive polyamide tape, an adhesive, or epoxy. Printed circuit board 70 has upper layer 72, intermediate layer 74, intermediate layer 7
6, and a bottom layer 78.

The printed circuit board 70 is, for example, FR-FR available from Motorola Inc., USA.
It may be assembled from materials such as 4. FR-4 is an epoxy resin reinforced with glass woven fabric. Printed circuit board 70
One of ordinary skill in the art will recognize that four parameters must be considered when selecting the material for use: thickness, dielectric constant, glass transition temperature, and coefficient of thermal expansion.

The thickness depends on the number of layers required and the amount of reinforcement used in a given layer. The reinforcing glass woven fabric can range in thickness from 2 mils per sheet (model number 106) to about 8 mils per sheet (model number 7628). The dielectric constant is determined by the combination of the resin used, the thickness of the reinforcing material used, and the model number. Standard FR-4
Has a dielectric constant of about 4.5. This dielectric constant can be reduced to about 3 by replacing the epoxy resin with a cyanate ester resin.
Can be dropped. However, the thicker the thickness, the more the thickness control, the rough surface,
lection) and problems associated with insufficient resin replenishment.

The temperature at which the resin changes from a glassy state to a "rubbery" state is generally indicated by Tg. Standard FR-4
Made of a bifunctional polymerized epoxy with a Tg of about 110 ° C. Higher Tg temperatures such as 125-150 ° C. can also be tolerated by using tetrafunctional epoxies. For higher Tg values in the range of 150-200 ° C, cyanate / epoxy blends can be used. Furthermore, a printed circuit board having a Tg of 250 ° C. or higher can be made using polyimide.

The thermal expansion coefficient of FR-4 is about 16 ppm / ° C.
Printed circuit board 70 and silicon chip made from FR-4
Due to the difference in the coefficient of thermal expansion between the IC package 30 and the IC package 30, the IC
Failure of the package 30 may occur.

The adhesive layer 60 may be Hitachi HM122u. Alternatively, the silicon chip 50 can be bonded to the printed circuit board 70 with a die bonding film such as HIATTACH-335 (DF-335) manufactured by Hitachi Chemical Co., Ltd. (Tokyo, Japan). HIATTACH-335 (DF-335) is a silver-filled thermosetting resin film for die bonding. The bonding process generally involves bonding the film onto a printed circuit board 70 at a temperature of 160 ° C. and applying a force of 1000-3000 grams for 5 seconds. The bonding of the silicon chip 50 onto the film is then performed at 220 ° C. for 5 seconds with a force of 150-200 grams.

DF-335 has the following characteristics. Inspection items Comments Unit DF-335 ────────────────────────────────── Appearance Visual-Silver film Solid 200 ℃ -2h wt% ≧ 96 Ash 600 ° C-1.5h wt% 40 Ash / Solid 600 ° C-1.5h wt% / Solid 42 Thickness Dial gauge μm 25 Tensile strength RT kgf / mm ² 7.1 Tensile coefficient RT kgf / mm ² 271 Shear strength 4x4mm chip / Ag kgf / chip Plating alloy 42 RT ≧ 10 250 ℃ 0.9 Peel strength 8x8mm chip / kgf / chip ≧ 3.0 240 ℃ (Rear / Bear alloy 42 85 ℃ 85%, 48h) Tg TMA , 180 ℃ -1h ℃ 123 Curing coefficient Viscoelastic spectrometer Mpa 1300 Humidity 85 ℃ / 85% RH, 48h wt% 0.1

Other examples of adhesives include thermosetting adhesives such as epoxy, polyimide and silicone.
The silicon chip 50 may be bonded to the printed circuit board 70 using a hot melt type thermoplastic adhesive such as a sheet-shaped or pressure-sensitive adhesive tape. In general, elastomers, for ease of use and incorporation into the manufacturing process,
Silicon or acrylic resin based adhesive tapes are used.

Referring to FIGS. 1 and 2 together, the intermediate layer
74 has a routing strip 82 that is electrically connected through a via 84 to a pad 100 located on the top surface 92 of the top layer 72 and the bottom surface 94 of the bottom layer 78. Because the IC package 30 of the present invention can be assembled and used in a variety of locations and orientations, the terms "top" and "bottom" as well as the terms "side" and "edge" are for illustration purposes only. It should be understood by those skilled in the art that only

The intermediate layer 76 includes a pair of bus bars 110.
These buses run through vias 84 to one or more pads 10
It is electrically connected to 0. The bus 110 may serve, for example, as power supply or ground, with one bus 110 performing one function such as power supply and the second bus 110 performing another function such as grounding.

The silicon chip 50 includes a silicon chip 50
There is a bonding pad 120 which is usually arranged in the central region. The bonding pad 120 is connected to the routing strip 82 and the bus bar 11 by wire bonding 80.
Connected to 0. Solder ball 15 located on pad 100
0 allows the IC package 30 to be joined to another IC package 30 or other components such as a motherboard or a single in-line memory module.

FIG. 1 shows a printed circuit board 70 having four layers (72,
(76, 76 and 78)
Those skilled in the art should understand that printed circuit board 70 may be comprised of a single layer or may be comprised of a multilayer printed circuit board having a different number of layers.

According to the above-mentioned components and their structures and interrelationships, an assembly for sealing is performed as described below. The term "assembly" refers to components that have been assembled prior to sealing. This assembly consists of a printed circuit board 70, a bonded silicon chip 50 and wire bonding 80. The printed circuit board 70 has an upper opening
Routing strip 82 and bus 11 extending into 86
There is a top opening 86 with zeros and a cavity 88. The upper opening 86 and the cavity 88 are open with respect to each other.

The wire bonding 80 process may begin after the silicon chip 50 has been bonded to the printed circuit board 70. Next, place the silicon chip 50 and the printed circuit board 70 on the heated table, and set the bonding temperature to 100 to 3
Raise to hot point between 00 ° C. A single gold wire having a diameter typically in the range of 0.7 mil to 1.3 mil is passed through a capillary tube heated to a temperature in the range of 200-500 ° C. One solder ball is made at the end of the wire using either flame or spark technology. The solder ball is then brought to the bonding pad 120 on the silicon chip 50 and a desired metal bond is made using a combination of compressive force and ultrasonic energy. By utilizing this "stitch" technique, the cross section of the wire is significantly reduced at that point. Then
Make a loop in the wire bond 80 above the bond just made and route the wire bond 80 to the desired connection on the printed circuit board 70, such as a routing strip 82 or busbar 110. Clamp the wire bond 80 and raise the capillary so that the wire bond 80 comes off at the outer edge of the bond. This process is repeated until all bonding pads 120 requiring electrical connection on silicon chip 50 are electrically connected to printed circuit board 70.

Following assembly of the above components, the upper opening 86 is filled with a potting material 90 as shown by the dashed line above the upper opening 86. Also, as shown by a broken line in the cavity 88, place the cavity 88 in a potting material.
May be filled with 90.

The potting material 90 is made of KMC184VA or KM
It may be a cyanate ester type resin such as C188VA-4 which can be purchased from Shin-Etsu Chemical Co., Ltd. Other examples of potting materials that can be used in the present invention include epoxy, polyester, polyimide, cyanoacrylate,
There are ceramic, silicon and urethane. The potting material may also include fillers that affect the coefficient of thermal expansion as well as the strength and elasticity of the potting material. As is known to those skilled in the art, the choice of potting material and filler will depend on the components used to fabricate IC package 30.

Typical Potting Resin Properties Epoxy Polyester Silicon Urethane 誘 電 Dielectric Rate, D-150 60 Hz 3.9 4.7 2.7 5.7 106 Hz 3.2 --- 2.7 3.4 Loss rate, D-150 60 Hz 0.04 0.017 0.001 0.123 106 Hz 0.03 --- 0.001 0.03 Dielectric strength, D-149 V / mil 450 325 550 440 Volume resistivity, D-257 Ωcm 10 ¹⁵ 10 ¹⁴ 10 ¹⁵ 10 ¹³ Arc resistance, D-495; second 150 135 120 180 Specific gravity, D-792 1.15 1.2 1.05 1.0 Water absorption, D-570% 24 h 0.15 0.3 0.12 0.4 Heat strain temperature D-648; 380 260 <70 <70 264 1b / in2 ° F Tensile strength, D-638; 9000 10,000 1000 2000 1b / in2 Impact strength (Izod), 0.5 0.3 No break No break D-256; ft 1b / in Coefficient of thermal expansion, 5.5 7.5 4.0 15 D-969; 10 ^-5 / ° F Thermal conductivity, C-177; 1.7 1.7 1.5 1.5 Btu ・ in / (h ・ ft2 ・ ° F) Linear shrinkage;% 0.3 3.0 0.4 2.0 Elongation, D-638;% 3 3 175 300

The solder balls 150 used in the present invention may be joined to the pads 100 using a conventional solder reflow system. For example, an IC package that condenses steam and uses a cloud of steam
A vapor phase solder reflow system that surrounds 30 and printed circuit board 70 may be utilized. A liquid, such as non-chlorinated (non-CFC) fluorocarbon, is first heated with sufficient energy to generate a vapor and sustain the vapor cloud. Then, when the IC package 30 is passed through the vapor, the vaporized liquid condenses on the package and releases latent heat of vaporization. This energy is then transferred to the IC package 30. As long as the IC package 30 remains in the steam, the steam will continue to release energy at a repeatable constant rate and temperature until the IC package 30 reaches the temperature of the steam.

The advantages of using non-chlorinated fluorocarbons are that they are extremely stable with respect to temperature, are colorless, odorless and nonflammable. In addition, it has low toxicity, low surface temperature, low boiling point and low heat of vaporization. Because the non-chlorofluorocarbon fluid is inert, it does not react with the flux or component materials, nor does it absorb oxygen or other gases that cause a reaction during solder reflow. As is known to those skilled in the art, the commercially available fluorocarbons used for vapor phase reflow are adjusted to vaporize at different stable reflow temperatures for different solder materials.

The vaporization temperature depends on the type of solder used. A brief list of recommended temperatures for non-chlorofluorocarbons used as vapor fluids is provided below in connection with the solder type composition used. In one embodiment, the composition of solder ball 150 is about 60% Pb (lead) and 40% Sn (tin). This composition provides strong bonding between IC packages 30 or between IC packages 30 and boards such as motherboards, sister boards or SIMM boards. 60% Pb / 40%
By using the composition of Sn, there is no need to provide a solder paste on the solder pad due to the strong adhesive force of the Sn composition of 60% Pb / 40%. Alternatively, a variety of other materials may be used as described in the table below.

Vaporization temperature and solder type fluid temperature Solder type ─────────────────────────────────── 56, 80 , 97, 101, 102 ° C and 155 ° C 100 In 37 Sn / 38 Pb / 25 In 165 ° C 70 Sn / 18 Pn / 12 In 70 In / 3O Pb 174 ° C 60 In / 40 Pb 190 ° C 90 In / 10 Ag 50 In / 50 Pb 63 Sn / 37 Pb 70 Sn / 30 Pb 60 Sn / 40 Pb 215 ° C and 230 ° C 60 Sn / 40 In 60 Sn / 40 Pb 63 Sn / 37 Pb 70 Sn / 30 Pb 62 Sn / 36 Pb / 2 Ag 240 ℃ and 253 ℃ 75 Pb / 25 In 81 Pb / 19 In 260 ℃ and 365 ℃ 96.5 Sn / 3.5 Ag

The solder balls 150 may be joined to the pads 100 by infrared or radiant heat solder reflow technology. In such a system, each component of the soldering system would be directly exposed to radiant heat from the heating element. Different components absorb heat from the radiant energy element according to the molecular structure of the element.

In a conventional radiant heat system, only the outer surface of the component is exposed to the radiant heat, and the radiant heat may not reach the inner region as efficiently as the above-described heating method by steam saturation. . However, the present invention is not affected by this typical problem by using solder balls 150 instead of leads. In fact, due to the reduced overall size, either vapor phase solder reflow or radiant heat solder reflow can be used effectively in the present invention.

The present invention also solves other problems associated with solder reflow systems. These problems include voids, coplanarity, and tombstoning.
ng), open joints, cracks in components, generation of thermal shock and thermal stress, and failures caused by them. In the present invention, solder lead is used for IC package
These problems are solved by eliminating the need for an electrical connection to 30. By using solder balls 150 instead of leads, the area around the pad area or under the leads, caused by incomplete reflow or poor welding of the soldering surface due to improper flux or poor oxidized surfaces The problems associated with voids that occur in are eliminated. Since the surface tension on both sides of the solder ball 150 is equal, the use of the solder ball 150 also reduces or eliminates coplanarity and tombstone problems.

Open joints are usually caused by coplanarity problems, while the moisture trapped in the IC package can expand and crack as the device is heated to perform reflow. In some cases, the IC package breaks at one of the corners due to increased internal pressure. Cleavage of the package causes breakage of wire bonding from the lead frame to the silicon chip. In some cases, the temperature difference between the top and bottom of the device causes a difference in expansion coefficient, which can crack the silicon chip due to warpage of the package top.

By using the present invention, the only surface temperature difference that occurs is the temperature difference between the solder ball 150 and the printed circuit board 70, which allows the use of either vapor phase solder reflow or radiant heat reflow. Thus, the present invention can be manufactured. Since the temperature difference between the components is almost negligible, the small size of the solder ball 150 and the small size of the IC package 130 can be used in any reflow system as a whole.
Further, by selecting a potting material 90 having a coefficient of thermal expansion similar or equal to the coefficients of thermal expansion of the other components of the IC package 30, the effects and problems of the heating reflow method can be minimized.

Although the board-on-chip layout of the IC package 30 as depicted in FIGS. 1 and 2 has been described using the central bonding pad 120, the principles of the present invention are based on the side view of the silicon chip 50. It should be understood by those skilled in the art that the present invention can be applied to the silicon chip 50 having the bonding pads 120 of the alternative layout such that the bonding pads 120 are arranged along.

Those skilled in the art should also note that pad 100 and bus bar 110 may be located on a single layer of printed circuit board 70. Generally, an insulating tape layer or coating may be placed on the busbar 110 to provide electrical insulation. However, an advantage of the multilayer printed circuit board 70 is that the bus bar 110 need not be insulated. The present invention eliminates the need for insulation. In addition, the multi-layer printed circuit board 70 provides a large processing room for performing wire bonding.

FIG. 3 is a simplified cross-sectional view of another embodiment of the IC package of the present invention, indicated generally at 32.
The IC package 32 includes a silicon chip 50 and a printed circuit board 70, and the circuit board is bonded to the silicon chip 50 by an adhesive layer 60. In this embodiment, the printed circuit board 70 comprises three layers: an upper layer 72, an intermediate layer 74, and a bottom layer 76. The printed circuit board 70 has an upper opening 86. As best seen in FIG. 2, routing strip 82 and busbar 110 extend into upper opening 86. After assembly, the upper opening 86 is filled with a potting material 90 as shown by the dashed line around the silicon chip 50 above the upper opening 86. Via
By 84, the pads 100 disposed on the upper surface 92 of the upper layer 72 and the lower surface 94 of the bottom layer 78 are electrically connected.

FIG. 4 is a simplified bottom view of an alternative embodiment of the IC package, indicated generally at 34. IC package 34
Is provided with a printed circuit board 70, which is joined to the silicon chip 50 by an adhesive layer (not shown). Two rows of pads 100 and 108 surrounding the chip 50 contacting the bottom surface 94 of the printed circuit board 70 are disposed on the printed circuit board 70. The first row of pads 100 is a silicon chip 50
Is located adjacent to. A second row of pads 108 is located around the first row of pads 100. Conduit 118
May electrically connect the pad 100 to the pad 108. The pad 108 is electrically connected to the pad 108 disposed on the opposite side of the printed circuit board 70 by using a via (not shown).
May be.

FIG. 5 illustrates one embodiment of a three-dimensional integrated circuit module in a simplified cross-sectional view, generally indicated at 130. Silicon chip 50, wire bonding 80
Is electrically connected to each printed circuit board 70, after which the wire connections are sealed with a potting material 90. Each IC package 30, 32 or 34 is then interconnected with another IC package 30, 32 or 34 using solder balls 150. The leads used to connect a conventional IC package to, for example, a motherboard are solder balls 15
Replaced by 0. By using the solder balls 150, the overall contours of the IC packages 30, 32 to 34 and the integrated circuit module 130 are reduced.

Although FIG. 5 shows the IC packages 30, 32 to 34 electrically connected together by solder balls 150, the IC packages 30, 32 and 34 are also included (including but not limited to columns) Those skilled in the art should note that other electrical connection means may be used.

Therefore, according to the present invention, the IC packages 30, 32 to 34 to be molded into the module 130 can be stacked, whereby the overall height can be reduced.
The number of failures can also be reduced by reducing the number of soldering materials that have varying coefficients of thermal expansion. The present invention further reduces the total number of steps, for example, when assembling a memory unit, by streamlining the assembly process not only by reducing the number of steps, but also by removing the curing steps associated with integrated circuit encapsulation. .

Further, according to the method of the present invention, the wire bonding 80 for connecting the silicon chip 50 and the printed circuit board 70 in a single step is potted by using the opening 86 in the center of the printed circuit board 70. Is what you do.
By filling the opening 86 with the potting material 90,
The wire bonding 80 between the silicon chip 50 and the printed circuit board 70 is generally protected from its environment, especially from moisture due to hermetic sealing.

This means of potting the IC package 32 of the present invention greatly reduces the overall contour by allowing the non-functional portion of the silicon chip 50, ie, the back surface, to be exposed. In the upper opening 86,
By sealing and protecting the connection between the silicon chip 50 and the printed circuit board 70, it is not necessary to completely seal the entire assembly.

Further, the use of the method and apparatus of the present invention reduces environmental impact due to the reduced overall size of IC package 30.

Although the invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. It will be apparent to those skilled in the art that various modifications and combinations of the illustrated embodiments are possible as in the other embodiments of the present invention with reference to this description. It is therefore intended that the appended claims cover such modifications and embodiments.

The following items are disclosed in connection with the above description. (1) In a high-density IC package, a substrate having an opening and first and second surfaces, and a plurality of routing stations configured together with the substrate and extending into the opening.
A strip and a plurality of pads disposed around the openings in the first and second surfaces, wherein at least one of the pads disposed on the first surface comprises at least one of the routing strips. Electrically connected to
And the plurality of pads at least one of the pads arranged on the second surface are electrically connected to at least one of the routing strips, and at least one of the pads arranged on the first surface. At least one via electrically connected to at least one of the pads disposed on the second surface, a chip bonded to the substrate, the chip having at least one bonding pad, and the at least one The package comprising wire bonding for electrically connecting a bonding pad to at least one of the routing strips, and a potting material filling the opening. (2) The high-density IC package according to (1), wherein the plurality of pads surrounding the opening form a single row of pads. (3) a plurality of pads surrounding the opening, a first row of pads adjacent to the opening, and a second row of pads adjacent to the first row of pads facing the opening; Forming a high density IC according to the above (1).
package. (4) at least one bus bar configured with the substrate and extending into the opening, wherein at least one pad disposed on the first and second surfaces of the substrate is electrically connected to the at least one pad; The high-density IC package according to the above (1), further comprising the bus bar which is electrically connected. (5) The high-density IC package according to (1), further including at least one solder ball located on at least one of the pads arranged on the first surface. (6) The high-density IC package according to (1), further including at least one solder ball located on at least one of the pads arranged on the second surface. (7) at least one solder ball located on at least one of the pads arranged on the first surface, and at least one solder ball located on at least one of the pads arranged on the second surface; The high-density IC package according to the above (1), further comprising: (8) The high-density IC package according to (1), wherein the substrate further includes a cavity, and the chip is bonded to the substrate in the cavity. (9) An integrated circuit module, comprising: a first IC package; and a second IC package that can be stacked and electrically connected to the first IC package. (10) The integrated circuit module according to claim 9,
The first and second IC packages are each further configured with a substrate having an opening and first and second surfaces, and a plurality of routing strips extending into the opening. And a plurality of pads surrounding the openings disposed on the first and second surfaces, wherein at least one of the pads disposed on the first surface is electrically connected to at least one of the routing strips. And a plurality of the pads arranged on the second surface, wherein at least one of the pads arranged on the second surface is electrically connected to at least one of the routing strips. At least one via electrically connecting at least one of the pads arranged on the first surface and at least one of the pads, and a chip bonded to the substrate, The chip having at least one bonding pad, wire bonding electrically connecting the at least one bonding pad to at least one of the routing strips, and a potting material filling the opening. Said module. (11) At least one of the pads arranged on the second surface of the first IC package is electrically connected to at least one of the pads arranged on the first surface of the second IC package. The integrated circuit module according to the above (10), wherein (12) a plurality of solder balls for electrically connecting the pads arranged on the second surface of the first IC package and the pads arranged on the first surface of the second IC package; The integrated circuit module according to the above (10), further comprising: (13) further comprising a plurality of solder balls arranged on the second surface of the second IC package,
The integrated circuit module according to (10). (14) A plurality of pads that electrically connect the pads arranged on the second surface of the first IC package and at least one of the pads arranged on the first surface of the second IC package 13. The integrated circuit module according to claim 12, further comprising: (15) The device according to (14), further comprising a plurality of columns arranged on the second surface of the second IC package.
An integrated circuit module according to claim 1. (16) The integrated circuit module according to (9), further including a third IC package electrically connected to the second IC package in a stackable manner. (17) An integrated circuit module manufactured by a process including a step of obtaining a first IC package and electrically connecting the second IC package to the first IC package in a stackable manner. (18) In the process according to (17), the first and second IC packages are each configured with a substrate having an opening and first and second surfaces, and the substrate, A plurality of routing strips extending into the portion, and a plurality of pads surrounding the opening disposed on the first and second surfaces, wherein at least one of the pads disposed on the first surface. And a plurality of pads electrically connected to at least one of the routing strips, and at least one of the pads disposed on the second surface is electrically connected to at least one of the routing strips. At least one via electrically connecting at least one of the pads arranged on the second surface and at least one of the pads arranged on the first surface; A chip bonded to a board, the chip having at least one bonding pad; wire bonding electrically connecting the at least one bonding pad to at least one of the routing strips; and filling the opening. The process further comprising a potting material. (19) Arranging a plurality of solder balls between the pads arranged on the second surface of the first IC package and the pads arranged on the first surface of the second IC package The process according to the above (17), further comprising a step. (20) arranging a plurality of columns between the pads arranged on the second surface of the first IC package and the pads arranged on the first surface of the second IC package The process according to (18), further comprising: (21) An opening (86) and first and second faces (92, 94), configured with a substrate, having a plurality of routing strips (82) extending into the opening (86). A substrate (70), a plurality of pads (100) disposed on the first and second faces (92, 94) and electrically connected to at least one of the routing strips (82); a first face (92) Pads (100, 108)
A chip (50) bonded to a substrate (70) having a bonding pad (120), a via (84) for electrically connecting a pad disposed on a second surface (94), and at least one bonding pad (120). A high density IC package (30) that includes a wire bonding (80) that electrically connects to the at least one of the routing strips (82) and a potting material (90) that fills the opening (86).

[Brief description of the drawings]

FIG. 1 is a simplified end cross-sectional view of a high density IC package of the present invention.

FIG. 2 is a simplified plan view of the high-density IC package of the present invention.

FIG. 3 is a simplified end cross-sectional view of a high density IC package of the present invention.

FIG. 4 is a simplified bottom view of the high density IC package of the present invention.

FIG. 5 is a simplified end cross-sectional view of a high density IC module having a plurality of high density IC packages oriented in a stacked configuration.

Claims (2)

[Claims] 1. A high density integrated circuit package, comprising: a substrate having an opening and first and second surfaces; and a plurality of routing strips configured with the substrate and extending into the opening. A plurality of pads disposed around the openings in the first and second surfaces, wherein at least one of the pads disposed on the first surface is electrically connected to at least one of the routing strips. A plurality of pads electrically connected and at least one of the pads disposed on the second surface is electrically connected to at least one of the routing strips; and the pad disposed on the first surface. At least one via electrically connected to at least one of the pads arranged on the second surface, and a chip bonded to the substrate The chip having at least one bonding pad; wire bonding electrically connecting the at least one bonding pad to at least one of the routing strips; and a potting material filling the opening. An integrated circuit package characterized by the above-mentioned. 2. An integrated circuit module, comprising: a first IC package; and a second IC package that can be stacked on and electrically connected to the first IC package.