JP2000150384A - Aggregate of semiconductor fine particles and manufacture thereof applied by same method - Google Patents

Aggregate of semiconductor fine particles and manufacture thereof applied by same method

Info

Publication number
JP2000150384A
JP2000150384A JP32383298A JP32383298A JP2000150384A JP 2000150384 A JP2000150384 A JP 2000150384A JP 32383298 A JP32383298 A JP 32383298A JP 32383298 A JP32383298 A JP 32383298A JP 2000150384 A JP2000150384 A JP 2000150384A
Authority
JP
Japan
Prior art keywords
semiconductor
fine particles
semiconductor fine
thin film
amorphous
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP32383298A
Other languages
Japanese (ja)
Other versions
JP3525137B2 (en
Inventor
Yutaka Wakayama
裕 若山
Shunichiro Tanaka
俊一郎 田中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Japan Science and Technology Agency
Original Assignee
Toshiba Corp
Japan Science and Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Japan Science and Technology Corp filed Critical Toshiba Corp
Priority to JP32383298A priority Critical patent/JP3525137B2/en
Publication of JP2000150384A publication Critical patent/JP2000150384A/en
Application granted granted Critical
Publication of JP3525137B2 publication Critical patent/JP3525137B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Landscapes

  • Physical Vapour Deposition (AREA)
  • Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

PROBLEM TO BE SOLVED: To manufacture an aggregate of semiconductor fine particles in a simple process which is capable of increasing the density and improving the grain size and shape accuracy of the semiconductor fine particles. SOLUTION: A amorphous crystalline semiconductor thin film 2 is formed on a substrate 1 whose interfacial energy with respect to the film 2 is increasing under a high temperature. In an atmosphere in which the surface of the film 2 can be kept clean, by heating the substrate 1 to a temperature equal to or higher than that at which the film 2 is crystallized, a plurality of semiconductor fine particles 3 are produced while crystallizing the amorphous crystalline semiconductor. An aggregate of the particles 3 to be obtained has an average grain size of 100 nm or lower, and the particles 3 are present on the substrate 1 at a high density of 50 particles/mm2 or higher.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、量子ドットや発光
材料などとして使用される半導体微粒子集合体の製造方
法、およびそれを適用した半導体微粒子集合体に関す
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for producing a semiconductor fine particle aggregate used as quantum dots or luminescent materials, and a semiconductor fine particle aggregate to which the method is applied.

【0002】[0002]

【従来の技術】ナノオーダーの半導体微粒子を利用した
量子サイズデバイスは、将来のLSI技術の候補として
期待を集めている。例えば、断面寸法が電子の量子力学
的波長と同程度の細線や箱構造を利用した量子細線デバ
イスや量子箱デバイス、量子井戸を利用した共鳴トンネ
ル効果デバイスや共鳴トンネル素子など、量子的なサイ
ズ効果やトンネル効果などを利用して、新しい半導体デ
バイス(量子サイズデバイス)を実現する試みがなされ
ている。さらに、ナノオーダーの半導体微粒子を発光材
料などとして使用することも検討されている。
2. Description of the Related Art Quantum-size devices using nano-order semiconductor fine particles are expected as candidates for future LSI technology. For example, quantum size effects such as quantum wire devices and quantum box devices using thin wires or box structures whose cross-sectional dimensions are comparable to the quantum mechanical wavelength of electrons, resonance tunnel effect devices and resonance tunnel devices using quantum wells, etc. Attempts have been made to realize a new semiconductor device (quantum-size device) by utilizing the tunnel effect and tunnel effect. Further, the use of nano-order semiconductor fine particles as a light-emitting material has been studied.

【0003】このような量子サイズデバイスや発光材料
(発光素子)をより有効に利用するためには、単位素子
サイズや発光部サイズを例えば10〜 100nm、さらには10
nm以下というように超微細化する必要がある。ところ
で、従来の半導体微粒子の製造方法としては、CVD法
などの気相成長法を利用して、基板上に半導体微粒子を
直接形成する方法が適用されている。
In order to more effectively use such a quantum size device or a light emitting material (light emitting element), the size of a unit element or the size of a light emitting portion is, for example, 10 to 100 nm, and moreover, 10 to 100 nm.
It is necessary to make it ultra-fine, such as below nm. By the way, as a conventional method of manufacturing semiconductor fine particles, a method of directly forming semiconductor fine particles on a substrate using a vapor phase growth method such as a CVD method is applied.

【0004】しかしながら、気相から半導体微粒子を直
接形成する方法では、基板上に堆積した半導体原子や半
導体分子の長距離拡散を利用して半導体微粒子を形成す
るために、基板上の半導体微粒子の数(数密度)を十分
に高めることができないという問題がある。また、得ら
れる半導体微粒子の粒径についてもばらつきが大きく、
半導体微粒子を利用した量子サイズデバイスや発光材料
の形成精度を十分に高めることができないという問題が
ある。
However, in the method of directly forming semiconductor fine particles from a gas phase, since the semiconductor fine particles are formed by using long-range diffusion of semiconductor atoms and semiconductor molecules deposited on the substrate, the number of semiconductor fine particles on the substrate is reduced. (Number density) cannot be sufficiently increased. Also, the particle size of the obtained semiconductor fine particles varies greatly,
There is a problem in that the precision of forming a quantum size device or a light emitting material using semiconductor fine particles cannot be sufficiently increased.

【0005】[0005]

【発明が解決しようとする課題】上述したように、半導
体微粒子を量子サイズデバイスや発光材料などに適用す
ることが検討されているが、従来の半導体微粒子の製造
方法は半導体微粒子の数密度を十分に高めることができ
ないと共に、得られる半導体微粒子の粒径のばらつきが
大きいというような問題を有している。
As described above, application of semiconductor fine particles to quantum size devices, light emitting materials, and the like has been studied. In addition, there is a problem that the particle size of the obtained semiconductor fine particles is large.

【0006】このようなことから、量子サイズデバイス
や発光材料などに必要とされる半導体微粒子(半導体ド
ット)を高精度かつ高密度に形成することを可能にする
技術の出現が望まれている。また、そのような技術を適
用することによって、粒径などの形状再現性に優れ、か
つ高密度の半導体微粒子集合体が求められている。
[0006] In view of the above, there is a demand for the emergence of a technology that enables the formation of semiconductor fine particles (semiconductor dots) required for quantum size devices and light emitting materials with high precision and high density. In addition, by applying such a technique, a high-density semiconductor fine particle aggregate having excellent shape reproducibility such as a particle size and the like is required.

【0007】本発明はこのような課題に対処するために
なされたもので、半導体微粒子を高精度かつ高密度に、
かつ簡易な工程で作製することを可能にした半導体微粒
子集合体の製造方法を提供することを目的としており、
さらにそのような製造方法を適用することによって、粒
径などの形状再現性に優れ、かつ高密度の半導体微粒子
集合体を提供することを目的としている。
SUMMARY OF THE INVENTION The present invention has been made to address such a problem, and it has been proposed that semiconductor fine particles can be formed with high precision and high density.
It is intended to provide a method of manufacturing a semiconductor fine particle aggregate that has been able to be manufactured in a simple process,
Furthermore, by applying such a manufacturing method, it is an object to provide a high-density semiconductor fine particle aggregate having excellent shape reproducibility such as a particle diameter.

【0008】[0008]

【課題を解決するための手段】本発明の半導体微粒子集
合体の製造方法は、請求項1に記載したように、非晶質
状態の半導体薄膜を、高温下で前記半導体薄膜との間の
界面エネルギーが上昇する基板上に形成する工程と、前
記半導体薄膜の表面を清浄に保ち得る雰囲気中にて、前
記非晶質状態の半導体薄膜が結晶化する温度以上に加熱
することにより、前記非晶質状態の半導体を結晶化させ
つつ、複数の半導体微粒子を生成する工程とを有するこ
とを特徴としている。
According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor fine particle aggregate, comprising: converting an amorphous semiconductor thin film into an interface with the semiconductor thin film at a high temperature; Forming the amorphous thin film on the substrate at a temperature higher than the temperature at which the amorphous semiconductor thin film is crystallized in an atmosphere capable of keeping the surface of the semiconductor thin film clean; Generating a plurality of semiconductor fine particles while crystallizing a semiconductor in a quality state.

【0009】本発明の半導体微粒子集合体の製造方法に
おいて、半導体薄膜には請求項2に記載したように、S
i、Ge、Se、TeおよびSiCから選ばれる少なく
とも1種を含む半導体、あるいは化合物半導体などの種
々の半導体を用いることができる。また、このような半
導体の非晶質薄膜との間で、高温下で界面エネルギーが
上昇する基板としては、例えば非晶質状態の化合物基板
などが用いられる。
In the method for producing a semiconductor fine-particle aggregate according to the present invention, the semiconductor thin film may be made of S
Various semiconductors such as a semiconductor containing at least one selected from i, Ge, Se, Te and SiC, or a compound semiconductor can be used. As a substrate whose interface energy increases at a high temperature with an amorphous thin film of such a semiconductor, for example, an amorphous compound substrate or the like is used.

【0010】また、本発明の半導体微粒子集合体の製造
方法において、非晶質状態の半導体薄膜の膜厚は請求項
3に記載したように30nm以下とすることが好ましい。さ
らに、請求項4に記載したように、非晶質状態の半導体
薄膜に対する加熱は10-5Torr以下の真空雰囲気中にて実
施することが好ましい。半導体微粒子の形成工程は、例
えば請求項5に記載したように、真空雰囲気中にて非晶
質状態の半導体薄膜に対し、その結晶化温度以上の温度
で熱処理を施すことにより実施される。
In the method for producing a semiconductor fine particle aggregate according to the present invention, the thickness of the semiconductor thin film in an amorphous state is preferably 30 nm or less. Furthermore, as described in claim 4, the heating of the amorphous semiconductor thin film is preferably performed in a vacuum atmosphere of 10 -5 Torr or less. The step of forming semiconductor fine particles is performed, for example, by subjecting an amorphous semiconductor thin film to a heat treatment at a temperature equal to or higher than its crystallization temperature in a vacuum atmosphere.

【0011】本発明の半導体微粒子集合体の製造方法
は、単一の半導体微粒子を基板上に形成することに限ら
れるものではなく、例えば請求項7に記載したように、
基板上に 2種以上の非晶質状態の半導体薄膜を積層形成
することによって、異種の 2種以上の半導体微粒子を混
在させて生成することも可能である。
The method for producing a semiconductor fine particle aggregate according to the present invention is not limited to forming a single semiconductor fine particle on a substrate.
By laminating two or more types of amorphous semiconductor thin films on a substrate, it is possible to produce a mixture of two or more different types of semiconductor fine particles.

【0012】本発明の半導体微粒子集合体の製造方法に
おいては、半導体薄膜との間の界面エネルギーが高温下
で上昇する基板上に非晶質状態の半導体薄膜を形成し、
この非晶質状態の半導体薄膜をその結晶化温度以上の温
度に加熱する。この加熱処理の過程で、非晶質半導体薄
膜の表面側から結晶化が起こると共に、基板と非晶質半
導体薄膜との界面エネルギーが上昇するため、結晶化し
た半導体の凝集が起こり、基板上に多数の半導体微粒子
が形成される。
In the method for producing a semiconductor fine particle aggregate according to the present invention, an amorphous semiconductor thin film is formed on a substrate whose interface energy with a semiconductor thin film increases at a high temperature;
The amorphous semiconductor thin film is heated to a temperature higher than its crystallization temperature. In the course of this heat treatment, crystallization occurs from the surface side of the amorphous semiconductor thin film, and the interface energy between the substrate and the amorphous semiconductor thin film increases. Many semiconductor fine particles are formed.

【0013】この際、半導体薄膜の形成から加熱処理ま
での雰囲気を、半導体薄膜の表面が清浄に保ち得る雰囲
気を維持することによって、非晶質半導体薄膜の表面側
からの結晶化が均等に起こり、さらに半導体微粒子は固
相での相変態(非晶質状態から結晶質状態)に基づい
て、原子の短距離拡散により形成されるため、高密度に
半導体微粒子を形成することができる。また、半導体微
粒子の粒径は当初の非晶質半導体薄膜の膜厚などに応じ
たものとなるため、半導体微粒子の形状バラツキを抑え
ることができ、粒径の揃った半導体微粒子集合体が得ら
れる。
At this time, by maintaining the atmosphere from the formation of the semiconductor thin film to the heat treatment so that the surface of the semiconductor thin film can be kept clean, crystallization from the surface side of the amorphous semiconductor thin film occurs uniformly. Further, since the semiconductor fine particles are formed by short-range diffusion of atoms based on the phase transformation (from an amorphous state to a crystalline state) in a solid phase, the semiconductor fine particles can be formed at a high density. In addition, since the particle size of the semiconductor fine particles depends on the initial thickness of the amorphous semiconductor thin film and the like, variation in the shape of the semiconductor fine particles can be suppressed, and a semiconductor fine particle aggregate having a uniform particle size can be obtained. .

【0014】このように、本発明の半導体微粒子集合体
の製造方法においては、半導体微粒子の粒径などの形状
再現性に優れるだけでなく、粒径や数密度を当初の非晶
質半導体薄膜の膜厚により制御することができるため、
目的に応じた半導体微粒子集合体を非晶質状態の半導体
薄膜の成膜工程および比較的低い温度での加熱工程とい
う簡易な工程で再現性よく得ることが可能となる。
As described above, in the method for producing a semiconductor fine particle aggregate of the present invention, not only is the shape reproducibility of the particle size of the semiconductor fine particles excellent, but also the particle size and number density of the initial amorphous semiconductor thin film are reduced. Because it can be controlled by the film thickness,
An aggregate of semiconductor fine particles according to the purpose can be obtained with high reproducibility by simple steps of forming a semiconductor thin film in an amorphous state and heating at a relatively low temperature.

【0015】本発明の半導体微粒子集合体は、上述した
ような本発明の半導体微粒子集合体の製造方法を適用す
ることにより得られるものであり、請求項8に記載した
ように、基板上に形成された複数の半導体微粒子を有す
る半導体微粒子集合体であって、前記半導体微粒子は平
均粒径が 100nm以下であると共に、前記基板上に50個/
mm2 以上の数密度で存在していることを特徴としてい
る。
The semiconductor fine particle aggregate of the present invention is obtained by applying the method of manufacturing the semiconductor fine particle aggregate of the present invention as described above, and is formed on a substrate as described in claim 8. A semiconductor fine particle aggregate having a plurality of semiconductor fine particles, wherein the semiconductor fine particles have an average particle diameter of 100 nm or less, and have 50 particles / particle on the substrate.
It is characterized by being present at a number density of at least mm 2 .

【0016】[0016]

【発明の実施の形態】以下、本発明を実施するための形
態について説明する。
Embodiments of the present invention will be described below.

【0017】図1は本発明を適用した半導体微粒子集合
体の製造工程の一実施形態を示す断面図である。まず、
図1(a)に示すように、基板1上に非晶質状態の半導
体薄膜2を形成する。非晶質状態の半導体薄膜2には種
々の半導体を使用することができ、例えばSi、Ge、
Se、Teなどの単体半導体、SiCなどの半導体、あ
るいはGaAs、InPなどの 3-5族半導体、ZnT
e、CdSeなどの 2-6族半導体のような化合物半導体
など、種々の半導体を用いることができる。
FIG. 1 is a cross-sectional view showing one embodiment of a manufacturing process of a semiconductor fine particle aggregate to which the present invention is applied. First,
As shown in FIG. 1A, an amorphous semiconductor thin film 2 is formed on a substrate 1. Various semiconductors can be used for the amorphous semiconductor thin film 2, for example, Si, Ge,
Elemental semiconductors such as Se and Te, semiconductors such as SiC, 3-5 group semiconductors such as GaAs and InP, ZnT
Various semiconductors such as a compound semiconductor such as a group 2-6 semiconductor such as e and CdSe can be used.

【0018】非晶質状態の半導体薄膜2の形成方法は特
に限定されるものではなく、例えばEB−PVD法、M
BE法などの種々の薄膜形成法を適用することができ
る。ただし、半導体薄膜2の形成後から後述する加熱工
程まで、その表面を清浄に保ち得る方法を使用するもの
とし、具体的には真空雰囲気下で成膜する方法を適用す
ることが好ましい。ここで言う薄膜表面の清浄な状態と
は、酸化膜や汚れなどが存在しない状態を指すものとす
る。
The method for forming the semiconductor thin film 2 in an amorphous state is not particularly limited. For example, EB-PVD, M
Various thin film forming methods such as a BE method can be applied. However, from the formation of the semiconductor thin film 2 to the heating step described later, a method capable of keeping the surface clean is used, and specifically, a method of forming a film in a vacuum atmosphere is preferably applied. Here, the clean state of the thin film surface refers to a state in which an oxide film, dirt, or the like does not exist.

【0019】また、非晶質状態の半導体薄膜2の膜厚は
30nm以下とすることが好ましい。半導体薄膜2の膜厚が
30nmを超えると、後述する加熱工程を実施した際に膜状
態で結晶化するおそれがあり、半導体微粒子を再現性よ
く形成することができない。特に、半導体微粒子の粒径
精度などを高める上で、半導体薄膜2の膜厚は10nm以下
とすることが望ましい。非晶質状態の半導体薄膜2の膜
厚の下限は、一様な膜を形成することが可能であれば特
に限定されるものではなく、例えば数原子層程度であっ
てもよい。
The thickness of the amorphous semiconductor thin film 2 is
Preferably, the thickness is 30 nm or less. The thickness of the semiconductor thin film 2 is
If it exceeds 30 nm, there is a risk that the film will be crystallized in a film state when a heating step described later is performed, and semiconductor fine particles cannot be formed with good reproducibility. In particular, the thickness of the semiconductor thin film 2 is desirably 10 nm or less in order to enhance the particle size accuracy of the semiconductor fine particles. The lower limit of the thickness of the amorphous semiconductor thin film 2 is not particularly limited as long as a uniform film can be formed, and may be, for example, about several atomic layers.

【0020】非晶質状態の半導体薄膜2の膜厚は、後に
詳述するように、生成する半導体微粒子の粒径および数
密度に大きく影響する。すなわち、半導体薄膜2の膜厚
が薄いほど、半導体微粒子の粒径を小さくすることがで
きると共に、その数密度を増やすことができる。このよ
うに、非晶質状態の半導体薄膜2の膜厚を調整すること
によって、半導体微粒子の粒径および数密度を制御する
ことが可能である。なお、具体的な粒径および数密度
は、半導体薄膜2を構成する半導体の種類によって異な
るため、半導体の種類に応じて半導体薄膜2の膜厚を制
御する。
The film thickness of the semiconductor thin film 2 in the amorphous state greatly affects the particle diameter and the number density of the generated semiconductor fine particles, as described later in detail. That is, as the thickness of the semiconductor thin film 2 is smaller, the particle diameter of the semiconductor fine particles can be reduced and the number density thereof can be increased. As described above, by adjusting the thickness of the semiconductor thin film 2 in the amorphous state, it is possible to control the particle diameter and the number density of the semiconductor fine particles. Since the specific particle size and the specific density vary depending on the type of semiconductor constituting the semiconductor thin film 2, the thickness of the semiconductor thin film 2 is controlled according to the type of semiconductor.

【0021】上述したような非晶質状態の半導体薄膜2
を形成する基板1には、半導体薄膜2との間で高温下で
界面エネルギーが上昇する基板を使用する。すなわち、
常温下での非晶質状態の半導体薄膜2と基板1との間の
界面エネルギーをe1 、これを加熱した際の界面エネル
ギーをe2 としたとき、本発明ではe1 <e2 を満足す
る基板材料を用いる。
Semiconductor thin film 2 in an amorphous state as described above
Is used, the surface energy of which increases with the semiconductor thin film 2 at a high temperature. That is,
Assuming that the interfacial energy between the amorphous semiconductor thin film 2 and the substrate 1 at room temperature is e 1 and the interfacial energy when heated is e 2 , the present invention satisfies e 1 <e 2 . Substrate material to be used.

【0022】基板1の具体的な構成材料としては、a-S
iO2 (いわゆる石英ガラスなど)、a-GeO2 などの
非晶質化合物を用いることができ、これら以外の一般的
なガラス基板を使用することも可能である。さらに、例
えば半導体基板上にSiO2やAl2 3 などの非晶質
層を設けた基板など、半導体薄膜2の形成面に半導体薄
膜2との間で高温下で界面エネルギーが上昇する層を設
けたような基板を使用することもできる。
The specific constituent material of the substrate 1 is a-S
Amorphous compounds such as iO 2 (so-called quartz glass) and a-GeO 2 can be used, and other general glass substrates can also be used. Further, for example, a layer whose surface energy increases at a high temperature between the semiconductor thin film 2 and the semiconductor thin film 2 is formed on the surface on which the semiconductor thin film 2 is formed, such as a substrate provided with an amorphous layer such as SiO 2 or Al 2 O 3 on the semiconductor substrate. A substrate as provided can also be used.

【0023】次に、基板1上に形成した非晶質状態の半
導体薄膜2に対して、その表面を清浄に保ち得る雰囲気
中で加熱処理を施す。加熱温度は、非晶質状態の半導体
薄膜2が結晶化する温度以上で、半導体薄膜2が溶融も
しくは蒸発しない温度とする。すなわち、本発明におけ
る加熱工程は、非晶質状態の半導体薄膜2の固相状態で
の相変態を利用して、半導体薄膜2から半導体微粒子3
を生成する。ここで、本発明における加熱工程は、加熱
炉やヒータなどを用いたいわゆる熱処理に限らず、例え
ばレーザアニールのような局所的な加熱であってもよ
い。
Next, the amorphous semiconductor thin film 2 formed on the substrate 1 is subjected to a heat treatment in an atmosphere capable of keeping its surface clean. The heating temperature is equal to or higher than the temperature at which the amorphous semiconductor thin film 2 is crystallized, and the temperature at which the semiconductor thin film 2 does not melt or evaporate. That is, the heating step in the present invention utilizes the phase transformation of the amorphous semiconductor thin film 2 in the solid state to remove the semiconductor fine particles 3 from the semiconductor thin film 2.
Generate Here, the heating step in the present invention is not limited to so-called heat treatment using a heating furnace, a heater, or the like, but may be local heating such as laser annealing.

【0024】加熱温度は、具体的には半導体薄膜2の種
類に応じて適宜設定する。例えば、非晶質状態の半導体
薄膜2にSiを用いた場合、a-Si(アモルファスS
i)は550℃前後から結晶化するため、それ以上の温度
でかつa-Siが溶融状態となる温度以下の範囲に加熱す
ることが好ましい。また、非晶質状態の半導体薄膜2に
Geを用いた場合、a-Geは 350℃前後から結晶化する
ため、それ以上の温度でかつa-Geが溶融状態となる温
度以下の範囲に加熱することが好ましい。加熱時間は非
晶質状態の半導体薄膜2がほぼ完全に結晶化するように
適宜設定する。
The heating temperature is appropriately set according to the type of the semiconductor thin film 2. For example, when Si is used for the amorphous semiconductor thin film 2, a-Si (amorphous S
Since i) is crystallized from around 550 ° C., it is preferable to heat to a temperature higher than that and a temperature lower than a temperature at which a-Si becomes a molten state. When Ge is used for the semiconductor thin film 2 in an amorphous state, a-Ge is crystallized from about 350 ° C., so that it is heated to a temperature higher than that and lower than a temperature at which a-Ge becomes a molten state. Is preferred. The heating time is appropriately set so that the amorphous semiconductor thin film 2 is almost completely crystallized.

【0025】また、加熱時の雰囲気は非晶質状態の半導
体薄膜2の表面を清浄に保ち得る雰囲気とする。具体的
には、半導体薄膜2の表面に酸化膜や汚れなどが存在し
ない状態を維持しつつ加熱工程を実施する。半導体薄膜
2の表面に酸化膜や汚れなどが存在していると、それら
が半導体薄膜2の表面側からの結晶化および結晶化に伴
う凝集を阻害し、半導体微粒子3を精度よく形成するこ
とができなくなる。このような清浄な表面状態は、半導
体薄膜2の形成後から加熱工程まで維持するものとす
る。
The heating atmosphere is such that the surface of the amorphous semiconductor thin film 2 can be kept clean. Specifically, the heating step is performed while maintaining a state in which an oxide film, dirt, or the like does not exist on the surface of the semiconductor thin film 2. If an oxide film or dirt is present on the surface of the semiconductor thin film 2, they inhibit crystallization from the surface side of the semiconductor thin film 2 and agglomeration accompanying the crystallization, so that the semiconductor fine particles 3 can be formed accurately. become unable. Such a clean surface state is maintained after the formation of the semiconductor thin film 2 until the heating step.

【0026】具体的な加熱雰囲気は、上述したように半
導体薄膜2の表面に酸化膜や汚れなどを生じさせないと
共に、残留原子や分子が悪影響を及ぼさない真空雰囲
気、例えば10-5Torr以下の真空雰囲気とすることが好ま
しい。また、場合によってはアルゴンやヘリウムなどの
不活性雰囲気を利用することもできる。
A specific heating atmosphere is a vacuum atmosphere in which no oxide film or dirt is formed on the surface of the semiconductor thin film 2 as described above, and a vacuum atmosphere in which residual atoms and molecules have no adverse effect, for example, a vacuum atmosphere of 10 -5 Torr or less. Preferably, the atmosphere is used. In some cases, an inert atmosphere such as argon or helium can be used.

【0027】上述したような清浄な雰囲気下で非晶質状
態の半導体薄膜2を加熱すると、図1(b)に示すよう
に、半導体薄膜2の表面側から結晶化がはじまる。図1
(b)において、2′は結晶核を示している。この際、
非晶質状態の半導体薄膜2と基板1との間の界面エネル
ギーは半導体薄膜2を形成した時点より上昇しているた
め、結晶化した半導体は表面積が小さくなるように凝集
して、図1(c)に示すように半導体微粒子3′が成長
しはじめる。
When the semiconductor thin film 2 in an amorphous state is heated in a clean atmosphere as described above, crystallization starts from the surface side of the semiconductor thin film 2 as shown in FIG. FIG.
In (b), 2 'indicates a crystal nucleus. On this occasion,
Since the interfacial energy between the semiconductor thin film 2 in the amorphous state and the substrate 1 has increased since the time when the semiconductor thin film 2 was formed, the crystallized semiconductor aggregated so as to have a small surface area, and FIG. As shown in c), the semiconductor fine particles 3 'begin to grow.

【0028】半導体の結晶化は周囲の非晶質半導体を取
り込むようにして進行するため、図1(d)に示すよう
に、当初の非晶質状態の半導体薄膜2の膜厚に応じた粒
径を有する半導体微粒子3が多数生成する。すなわち、
半導体薄膜2の膜厚が薄いほど、粒径の小さい半導体微
粒子3が得られ、かつその生成数は多くなる。言い換え
ると、半導体薄膜2の膜厚が厚いとそれに応じて半導体
微粒子3が粒成長し、その生成数は少なくなる。
Since the crystallization of the semiconductor proceeds while taking in the surrounding amorphous semiconductor, as shown in FIG. 1D, a grain corresponding to the thickness of the semiconductor thin film 2 in the initial amorphous state is formed. A large number of semiconductor fine particles 3 having a diameter are generated. That is,
As the thickness of the semiconductor thin film 2 is smaller, the semiconductor fine particles 3 having a smaller particle diameter are obtained, and the number of the generated semiconductor fine particles 3 is larger. In other words, when the thickness of the semiconductor thin film 2 is large, the semiconductor fine particles 3 grow correspondingly, and the number of the generated semiconductor fine particles 3 decreases.

【0029】この際、非晶質状態の半導体薄膜2の膜厚
が厚すぎると、結晶化した半導体を良好に凝集させるこ
とができず、薄膜状態のままで結晶化することになる。
また、非晶質状態の半導体薄膜2の表面に酸化膜や汚れ
などが存在していると、それらが半導体薄膜2の表面側
からの結晶化や結晶化に伴う凝集を阻害するため、半導
体微粒子3の形成および成長が妨げられ、半導体微粒子
3の粒径の均一性や数密度を低下させることになる。
At this time, if the semiconductor thin film 2 in the amorphous state is too thick, the crystallized semiconductor cannot be satisfactorily aggregated, and will be crystallized in the thin film state.
In addition, if an oxide film or dirt is present on the surface of the semiconductor thin film 2 in an amorphous state, they inhibit crystallization from the surface side of the semiconductor thin film 2 or agglomeration accompanying the crystallization. 3 is hindered from forming and growing, and the uniformity of the particle diameter and the number density of the semiconductor fine particles 3 are reduced.

【0030】上述したように、半導体微粒子3は固相で
の非晶質状態から結晶質状態への相変態によって、非晶
質状態の半導体薄膜2から生成されるものである。この
ような固相での相変態は原子の短距離拡散に基づくもの
であり、かつ当初の非晶質状態の半導体薄膜2の膜厚を
十分に薄くしていると共に、半導体薄膜2の表面側から
の結晶化が均等に生じるため、微小粒径の半導体微粒子
3を高密度(数密度)に生成することができる。さら
に、半導体微粒子3は当初の半導体薄膜2の膜厚などに
応じた粒径を有するため、そのバラツキを小さくするこ
とができ、粒径が揃った多数の半導体微粒子3、すなわ
ち半導体微粒子3の集合体を形成することができる。
As described above, the semiconductor fine particles 3 are generated from the amorphous semiconductor thin film 2 by a phase transformation from an amorphous state in a solid phase to a crystalline state. Such a phase transformation in the solid phase is based on the short-range diffusion of atoms, and the thickness of the semiconductor thin film 2 in the amorphous state at the beginning is sufficiently reduced, and the surface side of the semiconductor thin film 2 Since the crystallization from the particles occurs uniformly, the semiconductor fine particles 3 having a small particle diameter can be generated at a high density (number density). Furthermore, since the semiconductor fine particles 3 have a particle size according to the initial thickness of the semiconductor thin film 2 and the like, the variation can be reduced, and a large number of semiconductor fine particles 3 having a uniform particle size, that is, an aggregate of the semiconductor fine particles 3 Body can be formed.

【0031】本発明の半導体微粒子集合体の製造方法に
よれば、非晶質状態の半導体薄膜2の成膜工程および比
較的低い温度での加熱工程という簡易な工程のみによっ
て、高密度でかつ粒径が揃ったナノオーダーの半導体微
粒子3の集合体を再現性よく得ることができる。さら
に、各半導体微粒子3の粒径および数密度は、当初の非
晶質状態の半導体薄膜2の膜厚により制御することがで
きるため、粒径などの形状再現性に優れるだけでなく、
目的に応じた半導体微粒子3の集合体を再現性よく得る
ことができる。
According to the manufacturing method of the semiconductor fine particle aggregate of the present invention, the high-density and high-density particles can be formed only by the simple steps of forming the amorphous semiconductor thin film 2 and heating at a relatively low temperature. An aggregate of nano-sized semiconductor fine particles 3 having a uniform diameter can be obtained with good reproducibility. Further, since the particle diameter and the number density of each semiconductor fine particle 3 can be controlled by the thickness of the semiconductor thin film 2 in the initial amorphous state, not only the shape reproducibility such as the particle diameter is excellent, but also
An aggregate of the semiconductor fine particles 3 according to the purpose can be obtained with good reproducibility.

【0032】得られる半導体微粒子3の粒径および数密
度は、当初の半導体薄膜2の膜厚などによって異なるも
のの、上述したような条件下で非晶質状態の半導体薄膜
2から半導体微粒子3を作製した場合、平均粒径が 100
nm以下で、かつ数密度が50個/mm2 以上の半導体微粒子
3の集合体が再現性よく得られる。また、個々の半導体
微粒子3の粒径のバラツキは小さく、例えば平均粒径に
対する個々のバラツキを±20% 以内とすることができ
る。
Although the particle diameter and the number density of the obtained semiconductor fine particles 3 vary depending on the initial thickness of the semiconductor thin film 2 and the like, the semiconductor fine particles 3 are prepared from the amorphous semiconductor thin film 2 under the above-described conditions. Average particle size is 100
An aggregate of semiconductor fine particles 3 having a diameter of not more than nm and a number density of not less than 50 particles / mm 2 can be obtained with good reproducibility. Further, the variation in the particle size of the individual semiconductor fine particles 3 is small, and for example, the variation in the individual average particle size can be within ± 20%.

【0033】半導体微粒子3の粒径や数密度は半導体の
種類によっても異なるが、Siを用いた場合には特に当
初の半導体(Si)薄膜2の膜厚を例えば 3nm以下とす
ることによって、平均粒径が40nm以下で数密度が 300個
/mm2 以上というように、超微細な半導体(Si)微粒
子3を高密度に形成することができる。Geを用いた場
合には、Siに比べて粒径が小さく、かつ数密度が高い
半導体微粒子3が得られる。さらに、生成する半導体微
粒子3の平均粒径が小さいほど、個々の半導体微粒子3
の粒径のバラツキも小さくなるため、粒径の揃った超微
細な半導体微粒子3の集合体が得られる。
Although the particle diameter and the number density of the semiconductor fine particles 3 vary depending on the type of semiconductor, when Si is used, the average thickness of the semiconductor (Si) thin film 2 is particularly reduced to, for example, 3 nm or less. Ultrafine semiconductor (Si) fine particles 3 having a particle diameter of 40 nm or less and a number density of 300 particles / mm 2 or more can be formed at a high density. When Ge is used, semiconductor particles 3 having a smaller particle size and a higher number density than Si can be obtained. Furthermore, the smaller the average particle diameter of the generated semiconductor fine particles 3 is, the more individual semiconductor fine particles 3
Since the variation in the particle size of the particles is small, an aggregate of ultrafine semiconductor particles 3 having a uniform particle size can be obtained.

【0034】本発明の半導体微粒子集合体は、上述した
ような平均粒径および数密度を有し、さらには個々の粒
径の平均粒径に対するバラツキが小さい、すなわち粒径
が揃った半導体微粒子3を基板1上に多数形成したもの
であり、本発明の半導体微粒子集合体の製造方法を適用
することではじめて再現性よく得ることが可能となった
ものである。
The semiconductor fine particle aggregate of the present invention has the average particle diameter and the number density as described above, and furthermore, the individual particle diameter has a small variation with respect to the average particle diameter, that is, the semiconductor fine particles 3 having a uniform particle diameter. Are formed on the substrate 1 in a large number, and can be obtained with good reproducibility for the first time by applying the manufacturing method of the semiconductor fine particle aggregate of the present invention.

【0035】このような本発明の半導体微粒子集合体
は、半導体微粒子3を例えば量子サイズデバイスや発光
材料(発光素子)に適用する際に、ナノオーダーの粒径
やそのバラツキの少なさが有効に作用するものである。
すなわち、量子サイズデバイスや発光材料は、単位素子
サイズや発光材料サイズを例えば 100nm以下というよう
に微細化する必要があると共に、デバイス特性の再現性
などを高める上で粒径が揃っていることが求められる。
本発明の半導体微粒子集合体によれば、このような量子
サイズデバイスや発光材料などが再現性よく得られる。
The semiconductor fine particle aggregate of the present invention can effectively reduce the nano-order particle size and its small variation when the semiconductor fine particles 3 are applied to, for example, a quantum size device or a light emitting material (light emitting element). It works.
In other words, quantum size devices and luminescent materials need to be miniaturized so that the unit element size and the luminescent material size are, for example, 100 nm or less. Desired.
According to the semiconductor fine particle aggregate of the present invention, such a quantum size device and a light emitting material can be obtained with good reproducibility.

【0036】本発明の半導体微粒子集合体の製造方法に
よれば、単一の半導体微粒子の集合体に限らず、異種の
2種以上の半導体微粒子を混在させた半導体微粒子集合
体を作製することも可能である。このような 2種以上の
半導体微粒子を混在させた半導体微粒子集合体を作製す
る場合には、図2(a)に示すように、第1の半導体か
らなる非晶質薄膜2Aとそれとは異なる第2の半導体か
らなる非晶質薄膜2Bを、基板1上に積層形成する。
According to the method for producing an aggregate of semiconductor fine particles of the present invention, not only an aggregate of single semiconductor fine particles but
It is also possible to produce a semiconductor fine particle aggregate in which two or more types of semiconductor fine particles are mixed. When producing an aggregate of semiconductor particles in which two or more kinds of semiconductor particles are mixed, as shown in FIG. 2A, an amorphous thin film 2A made of a first semiconductor and a second thin film different from the amorphous thin film 2A are formed. An amorphous thin film 2B made of two semiconductors is laminated on the substrate 1.

【0037】このような第1の非晶質薄膜2Aと第2の
非晶質薄膜2Bとの積層膜4に対して、前述した実施形
態と同様な加熱処理を施す。積層膜4を加熱して半導体
微粒子を生成する場合、各非晶質薄膜2A、2Bからそ
れぞれ半導体微粒子が生成する。すなわち、図2(b)
に示すように、第1の半導体からなる微粒子3Aと第2
の半導体からなる微粒子3Bとが基板1上に混在した半
導体微粒子集合体が得られる。この際、第1の非晶質薄
膜2Aおよび第2の非晶質薄膜2Bとして用いる半導体
は、相互に固溶しないものを選択することが好ましい。
A heat treatment similar to that of the above-described embodiment is performed on the laminated film 4 of the first amorphous thin film 2A and the second amorphous thin film 2B. When semiconductor particles are generated by heating the laminated film 4, semiconductor particles are generated from each of the amorphous thin films 2A and 2B. That is, FIG.
As shown in FIG. 3, the fine particles 3A made of the first semiconductor and the second
The semiconductor fine particle aggregate in which the semiconductor fine particles 3B are mixed on the substrate 1 is obtained. At this time, it is preferable to select semiconductors used as the first amorphous thin film 2A and the second amorphous thin film 2B that do not form a solid solution with each other.

【0038】これら各半導体微粒子3A、3Bの平均粒
径、数密度、個々の粒径のバラツキなどは、単一の半導
体微粒子3を生成する場合と同様に、当初の非晶質薄膜
2A、2Bの膜厚などにより制御することができる。す
なわち、個々の平均粒径が 100nm以下で、かつ全体の数
密度が50個/mm2 以上の半導体微粒子3Aおよび半導体
微粒子3Bの集合体を得ることができる。
The average particle diameter, number density, and variation in individual particle diameters of the semiconductor fine particles 3A and 3B are the same as in the case of forming the single semiconductor fine particle 3, and the initial amorphous thin films 2A and 2B Can be controlled by the thickness of the film. That is, it is possible to obtain an aggregate of the semiconductor fine particles 3A and the semiconductor fine particles 3B each having an average particle diameter of 100 nm or less and a total number density of 50 or more / mm 2 or more.

【0039】本発明の半導体微粒子集合体は、上記した
ような 2種以上の半導体微粒子が混在した状態のものを
含むものである。異種の半導体微粒子の混在状態は、図
2に示したような 2種の半導体微粒子3A、3Bに限ら
れるものではなく、用いる半導体相互の性質によって
は、さらに 3種類以上の半導体微粒子を混在させること
も可能である。
The aggregated semiconductor fine particles of the present invention include those in which two or more kinds of semiconductor fine particles as described above are mixed. The mixed state of different kinds of semiconductor fine particles is not limited to the two kinds of semiconductor fine particles 3A and 3B as shown in FIG. 2, and depending on the properties of the semiconductor used, three or more kinds of semiconductor fine particles may be mixed. Is also possible.

【0040】[0040]

【実施例】次に、本発明の具体的な実施例およびその評
価結果について述べる。
Next, specific examples of the present invention and evaluation results thereof will be described.

【0041】実施例1 まず、非晶質SiO2 基板(石英ガラス基板)を用意
し、この非晶質SiO2基板上に真空雰囲気中にてEB
−PVD法で厚さ約 1nmの非晶質Si膜を成膜した。こ
の非晶質Si膜の表面の清浄度を保ったまま、 1×10-8
Torrの雰囲気中にて非晶質Si膜に 600℃の温度で30分
間の結晶化熱処理を施した。
Example 1 First, an amorphous SiO 2 substrate (quartz glass substrate) was prepared, and EB was placed on this amorphous SiO 2 substrate in a vacuum atmosphere.
-An amorphous Si film having a thickness of about 1 nm was formed by the PVD method. While maintaining the surface cleanliness of the amorphous Si film, 1 × 10 −8
The amorphous Si film was subjected to a crystallization heat treatment at a temperature of 600 ° C. for 30 minutes in an atmosphere of Torr.

【0042】この結晶化熱処理の過程で、非晶質Si膜
の表面側から結晶化が起こると共に、非晶質SiO2
板と非晶質Si膜との界面エネルギーが上昇するため、
結晶化したSiの凝集が起こり、非晶質SiO2 基板上
に多数のSi微粒子が生成する。Si微粒子は固相での
相変態に基づいて原子の短距離拡散により形成されるた
め、高密度にSi微粒子を形成することができる。ま
た、Si微粒子の形状バラツキは小さく、粒径が揃った
ものとなる。
In the course of the crystallization heat treatment, crystallization occurs from the surface side of the amorphous Si film and the interface energy between the amorphous SiO 2 substrate and the amorphous Si film increases.
Aggregation of crystallized Si occurs, and a large number of Si fine particles are generated on the amorphous SiO 2 substrate. Since Si fine particles are formed by short-range diffusion of atoms based on phase transformation in a solid phase, Si fine particles can be formed at a high density. In addition, the variation in shape of the Si fine particles is small, and the particle size is uniform.

【0043】上述した厚さ約 1nmの非晶質Si膜から生
成したSi微粒子の平面TEM像を模式化して図3に示
す。図3から明らかなように、非晶質SiO2 基板11
上には多数のSi微粒子12が生成しており、これらS
i微粒子12は10〜30nm程度の粒径を有していた。これ
らSi微粒子12の平均粒径は約16nmであり、各Si微
粒子12の平均粒径に対する粒径のバラツキは極めて小
さいものであった。また、数密度は約1150個/mm2 であ
り、粒径の揃った超微細なSi微粒子12が高密度に生
成していることが確認された。
FIG. 3 schematically shows a planar TEM image of Si fine particles formed from the above-mentioned amorphous Si film having a thickness of about 1 nm. As is apparent from FIG. 3, the amorphous SiO 2 substrate 11
A large number of Si fine particles 12 are generated on the
The i microparticles 12 had a particle size of about 10 to 30 nm. The average particle size of these Si fine particles 12 was about 16 nm, and the variation in the particle size with respect to the average particle size of each Si fine particle 12 was extremely small. In addition, the number density was about 1150 particles / mm 2 , and it was confirmed that ultrafine Si fine particles 12 having a uniform particle size were generated at a high density.

【0044】さらに、上述したSi微粒子の形成を、当
初の非晶質Si膜の膜厚を代えて実施した。図4に厚さ
約10nmの非晶質Si膜から生成したSi微粒子の平面T
EM像を模式化して示す。図4から明らかなように、非
晶質SiO2 基板11上に多数のSi微粒子13が生成
していることが分かる。なお、これらSi微粒子13は
厚さ約 1nmの非晶質Si膜から生成したSi微粒子12
と比べると粒径が大きく、また形成密度(数密度)が少
ない。Si微粒子13の平均粒径は約60nmであり、数密
度は約 200個/mm2 であった。粒径のバラツキはSi微
粒子13に比べてSi微粒子12の方が揃っていた。
Further, the above-mentioned formation of the Si fine particles was carried out by changing the film thickness of the initial amorphous Si film. FIG. 4 shows a plane T of Si fine particles generated from an amorphous Si film having a thickness of about 10 nm.
An EM image is schematically shown. As is clear from FIG. 4, it can be seen that many Si fine particles 13 are generated on the amorphous SiO 2 substrate 11. These Si fine particles 13 are Si fine particles 12 formed from an amorphous Si film having a thickness of about 1 nm.
In comparison with, the particle size is large and the formation density (number density) is small. The average particle size of the Si fine particles 13 was about 60 nm, and the number density was about 200 particles / mm 2 . The variation in the particle diameter was more uniform in the Si fine particles 12 than in the Si fine particles 13.

【0045】図5は非晶質Si膜の膜厚と形成されたS
i微粒子の平均粒径および数密度との関係を示す図であ
る。図3、図4および図5から明らかなように、非晶質
Si膜の膜厚を薄くすることによって、より微粒子化さ
れたSi微粒子を高密度に形成することが可能となる。
言い換えると、非晶質Si膜の膜厚によりSi微粒子の
粒径および数密度を制御することが可能であることが分
かる。
FIG. 5 shows the thickness of the amorphous Si film and the S film formed.
It is a figure which shows the relationship with the average particle diameter and number density of i microparticles | fine-particles. As is clear from FIGS. 3, 4 and 5, by reducing the thickness of the amorphous Si film, it is possible to form finer Si fine particles at a high density.
In other words, it is understood that the particle diameter and the number density of the Si fine particles can be controlled by the thickness of the amorphous Si film.

【0046】実施例2 まず、非晶質SiO2 基板(石英ガラス基板)を用意
し、この非晶質SiO2基板上に真空雰囲気中にてEB
−PVD法で厚さ約 1nmの非晶質Ge膜を成膜した。こ
の非晶質Ge膜の表面の清浄度を保ったまま、 1×10-8
Torrの雰囲気中にて非晶質Ge膜に 350℃の温度で30分
間の結晶化熱処理を施した。
Example 2 First, an amorphous SiO 2 substrate (quartz glass substrate) was prepared, and EB was placed on this amorphous SiO 2 substrate in a vacuum atmosphere.
-An amorphous Ge film having a thickness of about 1 nm was formed by the PVD method. While maintaining the surface cleanliness of the amorphous Ge film, 1 × 10 −8
The amorphous Ge film was subjected to a crystallization heat treatment at 350 ° C. for 30 minutes in an atmosphere of Torr.

【0047】この結晶化熱処理の過程で、非晶質Ge膜
の表面側から結晶化が起こると共に、非晶質SiO2
板と非晶質Ge膜との界面エネルギーが上昇するため、
結晶化したGeの凝集が起こり、非晶質SiO2 基板上
に多数のGe微粒子が生成する。Ge微粒子は固相での
相変態に基づいて原子の短距離拡散により形成されるた
め、高密度にGe微粒子を形成することができる。ま
た、Ge微粒子の形状バラツキは小さく、粒径が揃った
ものとなる。
In the course of the crystallization heat treatment, crystallization occurs from the surface side of the amorphous Ge film, and the interface energy between the amorphous SiO 2 substrate and the amorphous Ge film increases.
Aggregation of the crystallized Ge occurs, and a large number of Ge fine particles are generated on the amorphous SiO 2 substrate. Ge particles are formed by short-range diffusion of atoms based on phase transformation in a solid phase, so that Ge particles can be formed with high density. In addition, the Ge particles have a small variation in shape and have a uniform particle size.

【0048】上述した厚さ約 1nmの非晶質Ge膜から生
成したGe微粒子をTEM観察したところ、非晶質Si
2 基板上には多数のGe微粒子が生成しており、これ
らGe微粒子は 5〜20nm程度の粒径を有していた。Ge
微粒子の平均粒径は約10nmであり、各Ge微粒子の平均
粒径に対する粒径のバラツキは極めて小さいものであっ
た。また、数密度は約1300個/mm2 であり、粒径の揃っ
た超微細なGe微粒子が高密度に生成していることが確
認された。
When TEM observation of Ge fine particles formed from the above-mentioned amorphous Ge film having a thickness of about 1 nm, amorphous Si
A large number of Ge fine particles were generated on the O 2 substrate, and these Ge fine particles had a particle size of about 5 to 20 nm. Ge
The average particle size of the fine particles was about 10 nm, and the variation in the particle size with respect to the average particle size of each Ge fine particle was extremely small. In addition, the number density was about 1300 particles / mm 2 , and it was confirmed that ultrafine Ge particles having a uniform particle size were generated at a high density.

【0049】実施例1と同様に、非晶質Ge膜の膜厚を
変えてGe微粒子の生成を行ったところ、非晶質Ge膜
の膜厚を薄くすることによって、より微粒子化されたG
e微粒子を高密度に形成することができた。これによっ
て、非晶質Ge膜の膜厚によりGe微粒子の粒径や数密
度を制御することができることを確認した。
Ge particles were generated by changing the thickness of the amorphous Ge film in the same manner as in Example 1. When the thickness of the amorphous Ge film was reduced, the finer G particles were formed.
e Fine particles could be formed at a high density. Thus, it was confirmed that the particle diameter and the number density of the Ge particles can be controlled by the thickness of the amorphous Ge film.

【0050】実施例3 まず、非晶質SiO2 基板(石英ガラス基板)を用意
し、この非晶質SiO2基板上に真空雰囲気中にてEB
−PVD法で厚さ約 1nmの非晶質Ge膜を成膜し、続い
て成膜室内の真空状態を維持したままEB−PVD法で
厚さ約 1nmの非晶質Si膜を成膜した。この積層膜の表
面の清浄度を保ったまま、 1×10-8Torrの雰囲気中にて
非晶質Ge膜と非晶質Si膜との積層膜に 550℃の温度
で60分間の結晶化熱処理を施した。
Example 3 First, an amorphous SiO 2 substrate (quartz glass substrate) was prepared, and EB was placed on this amorphous SiO 2 substrate in a vacuum atmosphere.
-An amorphous Ge film having a thickness of about 1 nm was formed by a PVD method, and then an amorphous Si film having a thickness of about 1 nm was formed by an EB-PVD method while maintaining a vacuum state in the film forming chamber. . Crystallization of the amorphous Ge film and the amorphous Si film in a 1 × 10 -8 Torr atmosphere at 550 ° C. for 60 minutes in an atmosphere of 1 × 10 −8 Torr while keeping the surface of this laminated film clean Heat treatment was applied.

【0051】このような積層膜から生成した微粒子をT
EM観察したところ、非晶質SiO2 基板上には多数の
Ge微粒子と多数のSi微粒子とが混在して生成してい
ることが確認された。これらGe微粒子およびSi微粒
子の粒径は、実施例1や実施例2と同様に小さく、かつ
そのバラツキも極めて小さいものであり、粒径の揃った
超微細なGe微粒子およびSi微粒子が高密度に混在し
て生成していることが確認された。
The fine particles generated from such a laminated film are referred to as T
EM observation confirmed that a large number of Ge fine particles and a large number of Si fine particles were mixed and formed on the amorphous SiO 2 substrate. The particle diameters of these Ge fine particles and Si fine particles are as small as in Examples 1 and 2, and their dispersion is extremely small. It was confirmed that they were mixed and generated.

【0052】[0052]

【発明の効果】以上説明したように、本発明の半導体微
粒子集合体の製造方法によれば、比較的簡易な工程で量
子サイズデバイスや発光材料などとして有用な粒径の揃
った半導体微粒子を高精度にかつ高密度で形成すること
ができる。さらに、得られる半導体微粒子の粒径や数密
度は、当初の非晶質状態の半導体薄膜の膜厚により制御
することができるため、目的に応じた半導体微粒子の集
合体を再現性よく得ることが可能となる。
As described above, according to the method for manufacturing a semiconductor fine particle aggregate of the present invention, semiconductor fine particles having a uniform particle diameter useful as a quantum size device or a light emitting material can be obtained in a relatively simple process. It can be formed with high precision and high density. Further, since the particle size and number density of the obtained semiconductor fine particles can be controlled by the thickness of the semiconductor thin film in the initial amorphous state, an aggregate of semiconductor fine particles according to the purpose can be obtained with good reproducibility. It becomes possible.

【図面の簡単な説明】[Brief description of the drawings]

【図1】 本発明の一実施形態による半導体微粒子集合
体の製造工程およびそれにより得られる半導体微粒子集
合体を模式的に示す断面図である。
FIG. 1 is a cross-sectional view schematically showing a manufacturing process of a semiconductor fine particle aggregate according to an embodiment of the present invention and a semiconductor fine particle aggregate obtained thereby.

【図2】 本発明の他の実施形態による半導体微粒子集
合体の製造工程およびそれにより得られる半導体微粒子
集合体を模式的に示す断面図である。
FIG. 2 is a cross-sectional view schematically showing a manufacturing process of a semiconductor fine particle aggregate according to another embodiment of the present invention and a semiconductor fine particle aggregate obtained thereby.

【図3】 本発明の実施例1で厚さ約 1nmの非晶質Si
膜から生成したSi微粒子集合体の平面TEM像を模式
化して示す図である。
FIG. 3 shows an amorphous Si having a thickness of about 1 nm in Example 1 of the present invention.
FIG. 3 is a diagram schematically illustrating a planar TEM image of an aggregate of Si fine particles generated from a film.

【図4】 本発明の実施例1で厚さ約10nmの非晶質Si
膜から生成したSi微粒子集合体の平面TEM像を模式
化して示す図である。
FIG. 4 shows an amorphous Si having a thickness of about 10 nm in Example 1 of the present invention.
FIG. 3 is a diagram schematically illustrating a planar TEM image of an aggregate of Si fine particles generated from a film.

【図5】 非晶質Si膜の膜厚と生成したSi微粒子の
平均粒径および数密度の関係を示す図である
FIG. 5 is a diagram showing the relationship between the thickness of an amorphous Si film and the average particle size and number density of generated Si fine particles.

【符号の説明】[Explanation of symbols]

1……基板 2、2A、2B……非晶質状態の半導体薄膜 3、3A、3B……半導体微粒子 12、13……Si微粒子 DESCRIPTION OF SYMBOLS 1 ... Substrate 2, 2A, 2B ... Semiconductor thin film in an amorphous state 3, 3A, 3B ... Semiconductor fine particles 12, 13 ... Si fine particles

───────────────────────────────────────────────────── フロントページの続き Fターム(参考) 4K029 AA01 AA08 BA32 BA35 BA56 BD01 CA01 GA01 5F103 AA01 AA04 DD01 DD03 DD11 DD16 DD17 DD30 GG03 HH10 LL01 LL17 PP03 PP18 RR04 RR10  ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 4K029 AA01 AA08 BA32 BA35 BA56 BD01 CA01 GA01 5F103 AA01 AA04 DD01 DD03 DD11 DD16 DD17 DD30 GG03 HH10 LL01 LL17 PP03 PP18 RR04 RR10

Claims (10)

【特許請求の範囲】[Claims] 【請求項1】 非晶質状態の半導体薄膜を、高温下で前
記半導体薄膜との間の界面エネルギーが上昇する基板上
に形成する工程と、 前記半導体薄膜の表面を清浄に保ち得る雰囲気中にて、
前記非晶質状態の半導体薄膜が結晶化する温度以上に加
熱することにより、前記非晶質状態の半導体を結晶化さ
せつつ、複数の半導体微粒子を生成する工程とを有する
ことを特徴とする半導体微粒子集合体の製造方法。
A step of forming a semiconductor thin film in an amorphous state on a substrate whose interface energy with the semiconductor thin film is increased at a high temperature; and in an atmosphere capable of keeping the surface of the semiconductor thin film clean. hand,
Heating the semiconductor thin film in the amorphous state to a temperature higher than the crystallization temperature to crystallize the semiconductor in the amorphous state and generate a plurality of semiconductor fine particles. A method for producing a fine particle aggregate.
【請求項2】 請求項1記載の半導体微粒子集合体の製
造方法において、 前記半導体薄膜は、Si、Ge、Se、TeおよびSi
Cから選ばれる少なくとも 1種を含む半導体、あるいは
化合物半導体からなり、かつ前記基板は非晶質状態の化
合物基板からなることを特徴とする半導体微粒子集合体
の製造方法。
2. The method according to claim 1, wherein the semiconductor thin film is formed of Si, Ge, Se, Te, and Si.
C. A method for producing an aggregate of semiconductor fine particles, comprising a semiconductor or a compound semiconductor containing at least one selected from C, and wherein the substrate is a compound substrate in an amorphous state.
【請求項3】 請求項1記載の半導体微粒子集合体の製
造方法において、 前記非晶質状態の半導体薄膜の膜厚を30nm以下とするこ
とを特徴とする半導体微粒子集合体の製造方法。
3. The method according to claim 1, wherein the semiconductor thin film in an amorphous state has a thickness of 30 nm or less.
【請求項4】 請求項1記載の半導体微粒子集合体の製
造方法において、 前記非晶質状態の半導体薄膜に対する加熱を10-5Torr以
下の真空雰囲気中にて実施することを特徴とする半導体
微粒子集合体の製造方法。
4. The method according to claim 1, wherein the heating of the amorphous semiconductor thin film is performed in a vacuum atmosphere of 10 −5 Torr or less. Manufacturing method of aggregate.
【請求項5】 請求項1記載の半導体微粒子集合体の製
造方法において、 前記半導体微粒子の形成工程は、真空雰囲気中にて前記
非晶質状態の半導体薄膜に対し、その結晶化温度以上の
温度で熱処理を施すことにより実施することを特徴とす
る半導体微粒子集合体の製造方法。
5. The method of manufacturing a semiconductor fine particle aggregate according to claim 1, wherein the step of forming the semiconductor fine particles comprises the step of: forming a semiconductor thin film in an amorphous state in a vacuum atmosphere at a temperature equal to or higher than the crystallization temperature A method for producing a semiconductor fine particle aggregate, wherein the method is performed by performing a heat treatment on the substrate.
【請求項6】 請求項1記載の半導体微粒子集合体の製
造方法において、 前記基板上に平均粒径が 100nm以下の前記半導体微粒子
を50個/mm2 以上の数密度で生成することを特徴とする
半導体微粒子集合体の製造方法。
6. The method for producing a semiconductor fine particle aggregate according to claim 1, wherein the semiconductor fine particles having an average particle diameter of 100 nm or less are formed on the substrate at a number density of 50 particles / mm 2 or more. Of producing a semiconductor fine particle aggregate to be manufactured.
【請求項7】 請求項1記載の半導体微粒子集合体の製
造方法において、 前記基板上に 2種以上の前記非晶質状態の半導体薄膜を
積層形成すると共に、2種以上の前記半導体微粒子を混
在させて生成することを特徴とする半導体微粒子集合体
の製造方法。
7. The method for producing a semiconductor fine particle aggregate according to claim 1, wherein two or more types of said amorphous semiconductor thin films are laminated on said substrate, and two or more types of said semiconductor fine particles are mixed. A method for producing a semiconductor fine particle aggregate, comprising:
【請求項8】 基板上に形成された複数の半導体微粒子
を有する半導体微粒子集合体であって、前記半導体微粒
子は平均粒径が 100nm以下であると共に、前記基板上に
50個/mm2 以上の数密度で存在していることを特徴とす
る半導体微粒子集合体。
8. An aggregate of semiconductor fine particles having a plurality of semiconductor fine particles formed on a substrate, wherein the semiconductor fine particles have an average particle diameter of 100 nm or less, and
An aggregate of semiconductor fine particles, which is present at a number density of 50 particles / mm 2 or more.
【請求項9】 請求項8記載の半導体微粒子集合体にお
いて、 前記半導体微粒子は、Si、Ge、Se、TeおよびS
iCから選ばれる少なくとも 1種を含む半導体、あるい
は化合物半導体からなることを特徴とする半導体微粒子
集合体。
9. The semiconductor fine particle aggregate according to claim 8, wherein the semiconductor fine particles are Si, Ge, Se, Te and S.
An aggregate of semiconductor fine particles, comprising a semiconductor containing at least one selected from iC or a compound semiconductor.
【請求項10】 請求項8記載の半導体微粒子集合体の
製造方法において、 前記基板上に 2種以上の前記半導体微粒子が混在してい
ることを特徴とする半導体微粒子集合体。
10. The method for producing a semiconductor fine particle aggregate according to claim 8, wherein two or more kinds of the semiconductor fine particles are mixed on the substrate.
JP32383298A 1998-11-13 1998-11-13 Manufacturing method of semiconductor fine particle aggregate Expired - Fee Related JP3525137B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP32383298A JP3525137B2 (en) 1998-11-13 1998-11-13 Manufacturing method of semiconductor fine particle aggregate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP32383298A JP3525137B2 (en) 1998-11-13 1998-11-13 Manufacturing method of semiconductor fine particle aggregate

Publications (2)

Publication Number Publication Date
JP2000150384A true JP2000150384A (en) 2000-05-30
JP3525137B2 JP3525137B2 (en) 2004-05-10

Family

ID=18159104

Family Applications (1)

Application Number Title Priority Date Filing Date
JP32383298A Expired - Fee Related JP3525137B2 (en) 1998-11-13 1998-11-13 Manufacturing method of semiconductor fine particle aggregate

Country Status (1)

Country Link
JP (1) JP3525137B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002353426A (en) * 2001-05-29 2002-12-06 Oki Electric Ind Co Ltd Method of manufacturing for semiconductor device
JP2006135149A (en) * 2004-11-08 2006-05-25 Yuzo Mori METHOD OF MANUFACUTURING SUBSTRATE WITH Ge FINE CRYSTAL NUCLEI AND SUBSTRATE WITH Ge FINE CRYSTAL NUCLEI

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002353426A (en) * 2001-05-29 2002-12-06 Oki Electric Ind Co Ltd Method of manufacturing for semiconductor device
JP2006135149A (en) * 2004-11-08 2006-05-25 Yuzo Mori METHOD OF MANUFACUTURING SUBSTRATE WITH Ge FINE CRYSTAL NUCLEI AND SUBSTRATE WITH Ge FINE CRYSTAL NUCLEI
JP4665488B2 (en) * 2004-11-08 2011-04-06 森 勇蔵 Method for producing substrate with Ge microcrystal nucleus

Also Published As

Publication number Publication date
JP3525137B2 (en) 2004-05-10

Similar Documents

Publication Publication Date Title
JP4819701B2 (en) Nanowhisker growth with controlled orientation
US6652762B2 (en) Method for fabricating nano-sized diamond whisker, and nano-sized diamond whisker fabricated thereby
JPH1079376A (en) Method of depositing thin film on single crystalline semiconductor substrate
US20100065809A1 (en) Nanowire comprising silicon rich oxide and method for producing the same
JPH1197667A (en) Method of forming ultrafine particle of line and semiconductor element using the formed particle or line
JP2004179658A (en) Method for forming nanostructure of uniform and controlled-size semiconductor material on dielectric material by means of cvd method
US20210074543A1 (en) Method of forming transition metal dichalcogenidethin film and method of manufacturing electronic device including the same
KR20080104455A (en) Method for manufacturing nanowire by using stress-induced growth
JP2000315653A (en) Formation method of quantum dot of nitride semiconductor in droplet epitaxy
JP3525137B2 (en) Manufacturing method of semiconductor fine particle aggregate
JP4169145B2 (en) Method for forming hemispherical silicon microcrystals
CN113307236B (en) Single-layer or multi-layer CrTe3 film and preparation method thereof
JPH0370123A (en) Formation of crystalline semiconductor film
US5134091A (en) Quantum effective device and process for its production
JP3452764B2 (en) Method for manufacturing ultrafine projection structure
US5132247A (en) Quantum effective device and process for its production
Chang et al. Nanogrids and beehive-like nanostructures formed by plasma etching the self-organized SiGe islands
JPH0476217B2 (en)
CN115216748B (en) Preparation method of tellurium film and semiconductor device
Iriarte Growth of nickel silicide (NiSix) nanowires by silane decomposition
KR102480374B1 (en) Photoluminescence single device and manufacturing method of the same
JPH02191321A (en) Method of forming crystal
JP4854180B2 (en) Method for producing InSb nanowire structure
JP3181070B2 (en) Quantum box semiconductor device
Guliants et al. Self-assembly of spatially separated silicon structures by Si heteroepitaxy on Ni disilicide

Legal Events

Date Code Title Description
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20031021

A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A712

Effective date: 20031031

RD03 Notification of appointment of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7423

Effective date: 20031215

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313117

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20080227

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090227

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090227

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100227

Year of fee payment: 6

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110227

Year of fee payment: 7

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110227

Year of fee payment: 7

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120227

Year of fee payment: 8

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120227

Year of fee payment: 8

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130227

Year of fee payment: 9

LAPS Cancellation because of no payment of annual fees