JP2000149592A - Memory cell for defect relief and storage device utilizing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory cell for defect relief capable of being composed of redundant cells of the less number even when an ECC(error detecting/ correcting circuit) is used. SOLUTION: When an ECC is used in a multilevel memory, the least significant bit data (8 bits) in each cell includes, in redundant memory cells (4 bits), information indicating whether a defect exists or not as well as positional information of the defect, while more significant bit data (the bit data other than the least significant bit data) (8 bits) include, in a redundant memory cell (1 bit), only information indicating whether a defect exists or not. Since the more significant redundant memory cells only require 1 bit, the redundant memory cells of only 3 bits are required by storing, in the more significant redundant memory cells, information indicating whether a defect exists or not as well as positional information of the defect with respect to the least significant bit data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory cell for remedying a defect and a storage device using the same, and more particularly to a method for storing a plurality of bit data in one memory cell and using a data stored in a redundant cell for a defective bit. The present invention relates to a memory cell for repairing a defect, which corrects the error.

[0002]

2. Description of the Related Art Conventionally, in a memory cell of this kind for repairing a defect, a multi-valued memory for storing a plurality of bit data in one memory cell has been used, separately from a cell for storing original data. ECC (Error Checking and CCC) that corrects one defective bit per word using data stored in the provided redundant cell.
correcting: an error detection / correction circuit).

In this multi-valued memory, when ECC is used, as shown in FIG. 11, both the least significant bit and the most significant bit (bits other than the least significant bit) have a defect /
It is necessary to have the defect position information in the redundant memory cell.

For example, for 8-bit data, ECC bits required to remedy a 1-bit defect are as shown in FIG.
As shown in FIG. 1, 4 bits are required to specify the presence / absence / position of a defect. That is, the bit # 0 of the memory cell is replaced with the bit # 8 of the redundant memory cell.
It is necessary to add ~ # 11.

FIG. 1 shows a storage device using the above-described multi-valued memory.
It is shown in FIG. In this storage device, one word is 8 bits, and is composed of a memory cell 21 composed of a multi-valued memory, a sense amplifier 22, a latch / encoding circuit 23, an error bit specifying circuit 24, and a correction circuit 25. .

When a word read instruction is input to this storage device, the on / off state of 8 cells + ECC redundant cells at each stage of changing the word line into three stages is read out to sense amplifier 22, and the result is latched. -Input to the encoding circuit 23.

In the latch / encoding circuit 23, data read from the memory cells 21 is encoded into the least significant bit data and the most significant bit data for each memory cell. The least significant and most significant bit data (8 bits) + the least significant and most significant ECC bits (4 bits) of the output of the latch / encoding circuit 23 are input to the error bit specifying circuit 24. A correction signal specifying the presence / absence of a defect of the upper bit data and the position of the defect is output to the correction circuit 25. The number of correction signals is 8, for example, 5
If there is an error in the bit, “H” is output as the correction signal of the fifth bit, and “L” is output as the correction signals of the other bits.

The correction circuit 25 is a latch / encode circuit 2
3, the least significant bit data and the most significant bit data of the output of No. 3 and the correction signal of the error bit specifying circuit 24 are inputted, and the least significant bit data and the most significant bit data are compared with the correction signal. If there is no defect, output as it is.

[0009]

In the above-mentioned conventional multi-valued memory, when ECC is used in a memory product in which one word is 8 bits, when the number of redundant memory cells for repairing defects is 4 bits in addition to bits. There is a problem that redundant cells are required.

Accordingly, an object of the present invention is to solve the above-mentioned problems and to provide a memory cell for repairing a defect which can be constituted by fewer redundant cells even when ECC is used, and a storage device using the same. It is in.

[0011]

SUMMARY OF THE INVENTION A defect relief memory cell according to the present invention stores a plurality of bit data in one memory cell and corrects a defective bit by using data stored in a redundant cell. The memory cell for use is configured to limit the rescue range when at least a predetermined specific bit is defective in a defective cell.

A storage device according to the present invention is a storage device that uses a memory cell for defect repair which stores a plurality of bit data in one memory cell and corrects a defective bit using the data stored in the redundant cell. The defective rescue memory cell is configured to limit a remedy range when at least a predetermined specific bit is defective in a defective cell, and data read from the defective rescue memory cell is stored in each memory cell. Encoding means for encoding the data of the specific bits and the data of bits other than the specific bits every time; a parity bit created by the data of the bits other than the specific bits encoded by the encoding means; and a bit other than the specific bits By comparing the parity bits of the data with the parity bits of A specific bit error specifying unit that generates a specific bit correction signal that specifies presence / absence and a defective position of the specific bit data based on the specific bit data encoded by the encoding unit; Means, a bit error specifying means other than a specific bit for generating a correction signal for a bit other than the specific bit based on a comparison result of the parity comparing means and a correction signal for a specific bit of the specific bit error specifying means, A data switching unit for selecting and outputting any of the specific bit data encoded by the encoding unit and data of bits other than the specific bit; a specific bit error identifying unit specific bit correction signal; Select one of the bit error identification means other than the specific bit and the correction signal for a bit other than the specific bit. It includes a correction switching means for outputting, and a correction means for correcting the data from the data switching means a correction signal based on from the correction switching means.

That is, the storage device of the present invention is a multi-valued memory, which uses a memory product equipped with an ECC which corrects one defective bit per word using data stored in a redundant cell. By limiting the rescue range when at least the least significant bit is defective in a certain cell, the presence / absence of defectiveness and defective position information are given to the redundant cell for the least significant bit, and Information on only the presence or absence of a defect is stored in a redundant cell.

Thus, the number of redundant cells can be reduced. For example, ECC bits required to repair a 1-bit defect for 8-bit data require 4 bits to specify the presence / absence of a defect / fault position, but specify only the presence / absence of a defect. In this case, one bit is sufficient.

The relief range is limited as described above because the threshold voltage Vt of the cell can be set in three or more steps to realize a multi-valued memory [for example, a mask RO
M (read only memory) ion implantation amount and flash (flash) writing amount], the correspondence between each threshold voltage Vt that can be set in the cell and each output bit is determined by the adjacent threshold voltage Vt Is set so that the least significant bit is inverted, at least the least significant bit is inverted in the case of a cell having a defect due to the variation of the threshold voltage Vt. This is because the merit of the cell reduction exceeds the demerit of the reduction of the rescue rate by limiting the rescue range.

In the above description, the least significant bit is 1
This is only one example, and a circuit exhibiting the same effect can be realized by applying the same idea even when the specific bit other than the least significant bit is replaced.

[0017]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a diagram showing a configuration example of a memory cell (multi-level memory) for repairing a defect according to an embodiment of the present invention. The figure shows a case where a 2-bit 1-cell multi-valued memory is used.

In this case, when ECC is used in the multi-valued memory, the least significant bit data (8 bits) of each cell is provided with information on presence / absence of a defect / defective position in a redundant memory cell (4 bits). In the bit data (bit data other than the least significant bit data) (8 bits), only the presence or absence of a defect is given to the redundant memory cell (1 bit).

At this time, since only one bit is required for the upper-level redundant memory cell, the upper-level redundant memory cell stores the presence / absence / defective position information of the lowermost defect, so that the redundant memory cell requires only three bits. . That is, it is only necessary to add bits # 8 to # 10, which are redundant memory cells, to bits # 0 to # 7 of the memory cell.

FIG. 2 is a diagram showing another configuration example of a memory cell (multi-valued memory) for repairing a defect according to an embodiment of the present invention. The figure shows a case where a 4-bit 1-cell multi-valued memory is used.

In this case, when the ECC is used in the multi-valued memory, the least significant bit data (8 bits) of each cell is provided with information on the presence / absence of a defect / defective position in a redundant memory cell (4 bits). In the bit data (bit data other than the least significant bit data) (8 bits), only the presence or absence of a defect is given to the redundant memory cell (1 bit).

At this time, since only one bit is required for the upper redundant memory cell, the upper redundant memory cell stores the presence / absence / defective position information of the lowest defect, so that only two bits are required for the redundant memory cell. . That is, it is only necessary to add bits # 8 and # 9, which are redundant memory cells, to bits # 0 to # 7 of the memory cell.

As described above, the ECC of the unused upper bits
By using a redundant cell as a storage cell of the least significant ECC bit, in a memory product in which one word is 8 bits, a 2-bit 1-cell multi-valued memory has a 3-bit redundant cell, a 4-bit 1-cell or more multi-valued memory. In the memory, only 2-bit redundant cells can be used.

FIG. 3 is a block diagram showing the configuration of a storage device using a multilevel memory according to one embodiment of the present invention. FIG. 1 shows a configuration in the case of using a 2-bit 1-cell multi-valued memory.

Referring to FIG. 1, a storage device according to an embodiment of the present invention includes a memory cell 1 composed of a multi-valued memory, a sense amplifier 2, a latch / encoding circuit 3, a parity comparison circuit 4, a least significant error bit. The circuit includes a specifying circuit 5, a higher-order error bit specifying circuit 6, a data switching circuit 7, a correction switching circuit 8, and a correction circuit 9.

The memory cell 1 is composed of a memory cell for repairing a defect having the structure shown in FIG. 1, and when a read instruction of a word is inputted, 8 cells at each stage where the word line is changed into three stages + ECC redundant cells ON / OFF is read out to the sense amplifier 2.

The latch / encoding circuit 3 is a memory cell 1
Is encoded into the least significant bit and the most significant bit data for each memory cell, the most significant eight bit data is output to the parity comparison circuit 4 and the data switching circuit 7, and the least significant eight bit data is identified by the least significant error bit Circuit 5
And output to the data switching circuit 7. In addition, latch
The encoding circuit 3 outputs the higher-order parity bits to the parity comparison circuit 4 and outputs the lowest-order ECC bits to the lowest-order error bit specifying circuit 5.

The parity comparison circuit 4 compares the parity bit generated from the upper 8 bits of data with the upper parity bit to determine whether or not there is a defect in the upper bits, and outputs a higher bit error determination signal as a result of the determination. Output to the upper error bit identification circuit 6. The parity comparison circuit 4 compares the upper 8-bit data with the higher-order parity bit by taking an exclusive OR (EXOR).

The least significant error bit specifying circuit 5 inputs the least significant 8 bits data + the least significant ECC bit (4 bits) of the output of the latch / encoding circuit 3 and determines whether the least significant bit data has a defect and the position of the defect. The specified lower-order correction signal is converted into a higher-order error bit specifying circuit 6 and a correction switching circuit 8.
Output to

The upper error bit specifying circuit 6 receives the upper bit error determination signal from the parity comparing circuit 4 and the least significant correction signal from the lowest error bit specifying circuit 5, and outputs the upper bit error from the parity comparing circuit 4. The presence / absence of an error is determined for the upper bit by the determination signal. If there is an error, the lowest correction signal from the lowest error bit specifying circuit 5 is output to the correction switching circuit 8 as the upper correction signal, and the error-free signal is output. In all cases, the signal of "L" is output to the switching circuit 8 for correction.

The data switching circuit 7 outputs either the least significant 8 bit data or the most significant 8 bit data encoded by the latch / encoding circuit 3 to the correction circuit 9 in accordance with the least significant / high order switching address signal.

The correction switching circuit 8 switches between the lowest correction signal from the lowest error bit specifying circuit 5 and the high correction signal from the high error bit specifying circuit 6 according to the lowest / highest switching address signal. Output to the correction circuit 9.

The correction circuit 9 corrects the data from the data switching circuit 7 based on the correction signal from the correction switching circuit 8. That is, the correction circuit 9 corrects and outputs the least significant 8 bit data with the least significant correction signal if there is a defect, and outputs the least significant 8 bit data with the most significant correction signal if there is no defect. The upper 8-bit data is output as it is.

FIG. 4 is a circuit diagram showing a configuration of the upper error bit specifying circuit 6 of FIG. In the figure, a higher-order error bit specifying circuit 6 takes NANDs of the lowest-order correction signal from the lowest-order error bit specifying circuit 5 and a higher-order bit error determination signal from the parity comparison circuit 4.
8 and inverter circuits 12-1 to 12-8 which invert the outputs of the NAND circuits 11-1 to 11-8.

FIG. 5 is a timing chart showing the operation of the storage device of FIG. 3, FIG. 6 is a diagram showing the operation of the word line of the multi-valued memory according to one embodiment of the present invention, and FIG.
The sense amplifier 2 and the latch
FIG. 9 is a diagram illustrating an output result of the encoding circuit.

The operation of the storage device according to one embodiment of the present invention, that is, the operation of reading data from memory cell 1, will be described with reference to FIGS. Here, an operation of reading data from a memory cell (cell of a multi-level memory) 1 will be described for a case where the memory cell 1 is a 2-bit 1 cell. still,
Assume that the threshold voltage of the memory cell 1 is Vt, and four levels are realized per cell by setting an arbitrary potential among four levels of potentials (Vt0 to Vt3).

The potential of the word line in one cell varies in three stages (VR1, VR2, VR3) as shown in FIG. At this time, the threshold voltage Vt of the cell, the sense amplifier 2 and the latch / encode circuit 3
Is as shown in FIG. Here, Dm00
Indicates a lower bit and Dm01 indicates an upper bit.

That is, when the word potential is VR1, the output is "1" if the cell potential Vt0, and the cell potential Vt1
In this case, it becomes "0" if the cell potential Vt2, and becomes "0" if the cell potential Vt3.

When the word potential is VR2, the output is "1" if the cell potential Vt0, "1" if the cell potential Vt1, "0" if the cell potential Vt2, and the cell potential Vt3. If there is, it becomes "0".

The output when the word potential is VR3 is "1" if the cell potential Vt0, "1" if the cell potential Vt1, "1" if the cell potential Vt2, and the cell potential Vt3. If there is, it becomes "0".

The upper bit Dm01 is the cell potential Vt.
"0"("1") if 0, "0"("1") if the cell potential Vt1, and "1" if the cell potential Vt2.
(“0”), if the cell potential is Vt3, “1”
(“0”).

The lower bit Dm00 is the cell potential V
At t0, “0” (“1”), at cell potential Vt1, “1” (“0”), at cell potential Vt2, “0” (“1”), at cell potential Vt3. If there is "1"
(“0”).

In the case of the above example, for example, the cell potential Vt1
Is defective, the threshold voltage Vt of the cell is Vt0 or Vt2.
And the least significant bit is inverted.

In the case where the storage device according to one embodiment of the present invention is a memory product in which one word is 8 bits, reading of data from the storage device will be described below.

When a word read instruction is input to the above-mentioned storage device, the word line is changed into three stages at each stage.
The ON / OFF state of the cell + ECC redundant cell is read out to the sense amplifier 2, and the result is input to the latch / encode circuit 3.

The latch / encode circuit 3 encodes the data read from the memory cell 1 into the lowermost and upper bit data for each memory cell. The least significant 8 bits + the least significant ECC bits (4 bits) of the output of the latch / encoding circuit 3 are input to the least significant bit specifying circuit 5. The least significant bit identifying circuit 5 outputs a correction signal that identifies the presence or absence of the least significant bit failure and the location of the failure. The number of the correction signals is eight. For example, if there is an error in the fifth bit, "H" is output as the correction signal of the fifth bit, and "L" is output as the correction signals of the other bits.

The upper 8 bits of the output of the latch / encoder 3 and the upper parity bit are input to the parity comparator 4. The parity comparison circuit 4 determines whether or not there is a defect in the upper bit by comparing the parity bit created from the upper 8 bits of data with the upper parity bit. The parity comparison circuit 4 performs an exclusive OR (E) on the comparison between the upper 8 bits and the upper parity bit.
XOR).

The upper error bit specifying circuit 6 receives the lowermost correction signal from the lowermost error bit specifying circuit 5 and the upper bit error determination signal from the parity comparator 4 and receives the upper bit error determination signal as the upper bit error determination signal. The presence / absence of an error is determined, and if there is an error, the lowest-order correction signal from the lowest-order error bit identification circuit 5 is output as a higher-order correction signal,
When there is no error, all output signals are "L" (see FIG. 4).

The correction switching circuit 8 receives the lowest-order correction signal from the lowest-order error bit specifying circuit 5 and the high-order correction signal from the high-order error bit specifying circuit 6, and converts these signals to the lowest / highest order. The output is switched by the switching address signal.

The data switching circuit 7 receives the least significant 8 bit data and the most significant 8 bit data encoded by the latch / encoding circuit 3, and receives the least significant 8 bit data and the most significant 8 bit data according to the least significant / highly significant switching address signal. Is output.

The correction circuit 9 receives the correction signal from the correction switching circuit 8 and the data from the data switching circuit 7, and if there is a defect, the least significant 8 bit data is replaced with the least significant correction signal and the upper 8 bits. The data is corrected by the correction signal for the higher order and output, and if there is no defect, the lower 8 bits data and the upper 8 bits data are output as they are.

More specifically, if the correction signal corresponding to each bit data of each cell is "H", it means that there is an error, the bit data is inverted and output, and the corresponding correction signal is "L". "Means that it is correct, and outputs the bit data as it is. That is, the result of exclusive OR of the bit data and the corresponding correction signal is output for each cell.

As described above, the ECC of the unused upper bits
By using a redundant cell as a storage cell of the least significant ECC bit, in a memory product in which one word is 8 bits, a 2-bit 1-cell multi-valued memory has a 3-bit redundant cell, a 4-bit 1-cell or more multi-valued memory. In the memory, only 2-bit redundant cells can be used (see FIGS. 1 and 2).
reference).

FIGS. 8A to 8C are diagrams showing the relationship between the rescue rate of the present invention and the conventional rescue rate in a 2-bit 1-cell according to one embodiment of the present invention. (C) is a diagram showing the relationship between the rescue rate of the present invention and the conventional rescue rate in a 4-bit one cell according to an embodiment of the present invention.

Here, b: conventional remedy rate, c: remedy rate of the present invention, d: conventional number of bits used, e: number of used bits of the present invention, F: remedy rate of the present invention / conventional remedy rate , G: total defect rate, h: number of chips on the conventional wafer, effective chip number = total chip number− (defect number−repair number) = total chip number− (defect number−defect number × repair rate) = Total number of chips (1− (failure rate−failure rate * repair rate of the present invention)) = (d / e) * h * (1−g * (1− (c / b) * b)) = (d / E) * h * (1-g * (1-F * b)) holds. 8 and 9 show graphs obtained from the above equations, respectively.

In FIG. 8A, A1 is g = g in the present invention.
The relationship between (the rescue rate of the present invention / and the conventional rescue rate) when 20% and b = 60% and the number of effective chips is shown, and A2 indicates the case where g = 20% and b = 75% in the present invention. A3 shows the relationship between (the rescue rate of the present invention / and the conventional remedy rate) and the number of effective chips. 2 shows the relationship between the remedy rate) and the number of effective chips.

B1 is the conventional g = 20% and b = 60%
% (Repair rate of the present invention / conventional remedy rate) and the number of valid chips (92 valid chips), and B2 is g = 20% and b = 75% in the conventional case. The relationship between (the rescue rate of the present invention / the conventional rescue rate) and the number of effective chips is shown (95 effective chips), and B3 is g = 20% and b = 9 of the conventional art.
The relationship between 0% (the rescue rate of the present invention / and the conventional rescue rate) and the number of effective chips is shown (98 effective chips).
Pieces).

In FIG. 8B, A4 is g = g of the present invention.
The relationship between the number of effective chips and the remedy rate of the present invention / the remedy rate of the present invention at 50% and b = 60% and the number of effective chips are shown, and A5 indicates that at the time of g = 50% and b = 75% of the present invention. A6 shows the relationship between (the rescue rate of the present invention / and the conventional remedy rate) and the number of effective chips, and A6 shows the relationship between g = 50% and b = 90% of the present invention. 2 shows the relationship between the remedy rate) and the number of effective chips.

B4 is g = 50% and b = 60% in the prior art.
% (Repair rate of the present invention / conventional remedy rate) and the number of effective chips (80 effective chips) when B = g = 50% and b = 75% in the conventional case. The relationship between the (repair rate of the present invention / repair rate in the related art) and the number of effective chips is shown (the number of effective chips is 87.5).
= 90% (the rescue rate of the present invention / and the conventional rescue rate) and the number of effective chips (95 effective chips).
Pieces).

In FIG. 8 (c), A7 is g = g of the present invention.
The relationship between 80% and b = 60% (the rescue rate of the present invention / and the conventional rescue rate) and the number of effective chips is shown, and A8 indicates the case of g = 80% and b = 75% of the present invention. A9 shows the relationship between (the rescue rate of the present invention / and the conventional remedy rate) and the number of effective chips, and A9 indicates the case where g = 80% and b = 90% of the present invention. 2 shows the relationship between the remedy rate) and the number of effective chips.

B7 is the conventional g = 80%, b = 60%
% (Repair rate of the present invention / conventional remedy rate) and the number of effective chips (68 effective chips), and B8 represents the case of g = 80% and b = 75% of the conventional case. The relationship between (the rescue rate of the present invention / and the conventional rescue rate) and the number of effective chips is shown (the number of effective chips is 80).
The relationship between 0% (the rescue rate of the present invention / the conventional rescue rate) and the number of valid chips is shown (the number of valid chips 92).
Pieces).

In FIG. 9A, A11 represents g of the present invention.
= 20%, b = 60% (repair rate of the present invention / conventional remedy rate) and the number of effective chips, and A12 shows the case of g = 20% and b = 75% of the present invention. The relationship between (repair rate of the present invention / repair rate of the present invention) and the number of effective chips is shown.
Reference numeral 13 indicates the relationship between the (repair rate of the present invention / and the conventional rescue rate) and the number of effective chips when g = 20% and b = 90% in the present invention.

B11 is the conventional g = 20% and b = 6
The relationship between 0% (the rescue rate of the present invention / and the conventional rescue rate) and the number of valid chips is shown (92 valid chips), and B1
2 shows the relationship between the conventional g = 20% and b = 75% (the rescue rate of the present invention / and the conventional rescue rate) and the number of effective chips (95 effective chips). g = 20%,
When b = 90% (the rescue rate of the present invention / the conventional rescue rate)
And the number of effective chips (effective chip number 9
8).

In FIG. 9B, A14 represents g of the present invention.
= 50%, b = 60% (repair rate of the present invention / conventional rescue rate) and the number of effective chips, and A15 shows the case of g = 50% and b = 75% of the present invention. The relationship between (repair rate of the present invention / repair rate of the present invention) and the number of effective chips is shown.
Reference numeral 16 indicates the relationship between the (repair rate of the present invention / and the conventional rescue rate) and the number of effective chips when g = 50% and b = 90% in the present invention.

B14 is the conventional g = 50% and b = 6
The relationship between 0% (the rescue rate according to the present invention / and the conventional rescue rate) and the number of effective chips is shown (80 effective chips).
Reference numeral 5 indicates the relationship between the conventional g = 50% and b = 75% (the rescue rate of the present invention / and the conventional rescue rate) and the number of effective chips (the number of effective chips is 87.5), and B16 is Conventional g = 50
5 shows the relationship between the number of valid chips and the number of valid chips (the number of valid chips is 95) when (%, b = 90%) (the rescue rate of the present invention / and the conventional rescue rate).

In FIG. 9C, A17 represents g of the present invention.
= 80%, b = 60% (repair rate of the present invention / and conventional rescue rate) and the number of effective chips, and A18 shows the case of g = 80% and b = 75% of the present invention. The relationship between (repair rate of the present invention / repair rate of the present invention) and the number of effective chips is shown.
Reference numeral 19 denotes the relationship between the (repair rate of the present invention / and the conventional rescue rate) and the number of effective chips when g = 80% and b = 90% in the present invention.

B17 is the conventional g = 80% and b = 6
The relationship between 0% (the rescue rate according to the present invention / and the conventional rescue rate) and the number of effective chips is shown (68 effective chips).
8 shows the relationship between the conventional g = 80% and b = 75% (the rescue rate of the present invention / the conventional rescue rate) and the number of effective chips (80 effective chips), and B19 shows the conventional number of effective chips. g = 80%,
When b = 90% (the rescue rate of the present invention / the conventional rescue rate)
And the number of effective chips (effective chip number 9
2).

Therefore, as shown in FIG. 8, in a 2-bit 1-cell, when g: the total failure rate is 50% or less, the remedy ratio of the present invention / the conventional remedy ratio is close to 0.8, which is effective. Also, 4
In the bit 1 cell, as shown in FIG. 9, even if the g: total failure rate is 80% or less, the remedy rate of the present invention / the remedy rate of the related art is equal to 0.
Effective near 8

FIG. 10 is a diagram showing another example of the structure of a memory cell (multi-valued memory) for repairing a defect according to an embodiment of the present invention. In the figure, a memory product (1 cell of 2 bits) in which one word is 8 bits is arranged horizontally by 8 bits. However, the function of this configuration example is a memory product in which one word is 8 bits, and is not a memory product in which one word is 16 bits.

In this case, the conventional technique requires eight redundant cells, but if the upper bits (bits other than the least significant bit) are defective, another defective relief memory cell according to one embodiment of the present invention is used. By storing information on only the presence or absence of a defect in a redundant cell, it is possible to cope with five redundant cells.

As described above, in an apparatus using a memory product equipped with an ECC for correcting a defective bit of one bit per word using data stored in a redundant cell in a multi-valued memory, at least a defective cell is used. By limiting the rescue range when the least significant bit has a defect, the presence / absence of the defect and the defect position information are given to the redundant cell for the least significant bit, and only the presence / absence of the defect for the bits other than the least significant bit is determined. By giving information to redundant cells, the number of redundant cells can be reduced.

For example, ECC bits required to remedy a 1-bit defect for 8-bit data require 4 bits to specify the presence / absence of a defect. Is required to specify 1 bit.

The relief range is limited as described above because the threshold voltage Vt of the cell can be set in three or more stages to realize a multi-valued memory [for example, a mask RO
M (read only memory) ion implantation amount and flash (flash) writing amount], the correspondence between each threshold voltage Vt that can be set in the cell and each output bit is determined by the adjacent threshold voltage Vt Is set so that the least significant bit is inverted, at least the least significant bit is inverted in the case of a cell having a defect due to the variation of the threshold voltage Vt. This is because the merit of the cell reduction exceeds the demerit of the reduction of the rescue rate by limiting the rescue range.

It is to be noted that the least significant bit is one example in the above description, and a circuit having the same effect can be realized by applying the same concept even if it is replaced with a specific bit other than the least significant bit. can do.

[0075]

As described above, according to the present invention, 1
A plurality of bit data are stored in the memory cells and a defective bit is corrected using the data stored in the redundant cell. By limiting the rescue range in a certain case, there is an effect that even if ECC is used, it can be configured with fewer redundant cells.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration example of a defect relief memory cell according to an embodiment of the present invention.

FIG. 2 is a diagram showing another configuration example of a memory cell for repairing a defect according to an embodiment of the present invention;

FIG. 3 is a block diagram showing a configuration of a storage device using a multi-valued memory according to one embodiment of the present invention.

FIG. 4 is a circuit diagram showing a configuration of a higher-order error bit specifying circuit of FIG. 3;

FIG. 5 is a timing chart showing an operation of the storage device of FIG. 3;

FIG. 6 is a diagram showing an operation of a word line of a multi-level memory according to one embodiment of the present invention.

FIG. 7 is a diagram showing output results of a sense amplifier and a latch / encode circuit when the word line shown in FIG. 6 operates.

FIGS. 8A to 8C are diagrams showing the relationship between the remedy rate of the present invention and the conventional remedy rate in a 2-bit 1-cell according to one embodiment of the present invention.

FIGS. 9A to 9C are diagrams showing the relationship between the remedy rate of the present invention and the conventional remedy rate in a 4-bit 1-cell according to an embodiment of the present invention.

FIG. 10 is a diagram showing another configuration example of the memory cell for repairing a defect according to an embodiment of the present invention.

FIG. 11 is a diagram showing a configuration example of a memory cell for repairing a defect according to a conventional example.

FIG. 12 is a block diagram showing a configuration of a storage device using a multi-level memory according to a conventional example.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 memory cell 2 sense amplifier 3 latch / encoding circuit 4 parity comparison circuit 5 least significant bit specifying circuit 6 high order error bit specifying circuit 7 switching circuit for data 8 switching circuit for correction 9 correction circuit 11-1 to 11-8 NAND circuit 12-1 to 12-8 Inverter Circuit

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[Procedure amendment]

[Submission date] December 20, 1999 (1999.12.
20)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claims

[Correction method] Change

[Correction contents]

[Claims]

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0011

[Correction method] Change

[Correction contents]

[0011]

SUMMARY OF THE INVENTION A defect relief memory cell according to the present invention stores a plurality of bit data in one memory cell and corrects a defective bit using the data stored in the redundant cell. a memory cell, is bad
Only if the least significant bit is defective in a cell
Remedies are available .

[Procedure amendment 3]

[Document name to be amended] Statement

[Correction target item name] 0012

[Correction method] Change

[Correction contents]

A storage device according to the present invention is a storage device that uses a memory cell for defect repair which stores a plurality of bit data in one memory cell and corrects a defective bit using the data stored in the redundant cell. In the defective repair memory cell ,
Only and can be relieved if there is a defect in the lower bits, the data and the least significant bi of the least significant bit of the data read from the defective relief memory cell for each memory cell
And encoding means for encoding the Tsu bit other than DOO data, the least significant bit which is encoded by said encoding means
Before and parity bits that you created in the bit of data other than the door
Parity comparison means for determining whether a failure of the data bits other than the least significant bit by comparing the serial lowest parity bit bit other than the bit, the least significant bit which is encoded by said encoding means
The least significant bit error identification means for generating the least significant bit for correction signal identified the presence or absence of failure of the bets of data of the least significant bit data based on the defect position, and the comparison result of the parity comparator top the lowermost based on a correction signal for the least significant bits of the lower bit erroneous <br/> Ri specifying means
Least significant bit that generates a correction signal for bits other than
A bit error identification means other than bets, the least significant bit which is encoded by said encoding means
And data switching means for selecting and outputting one of the bets of data and the least significant bit other than the bit data, the least significant bit for the correction signal of the least significant bit error identification means and other than the least significant bit the bit error identifying means
Correction switching means for selecting and outputting one of a bit correction signal other than the least significant bit , and correction means for correcting data from the data switching means based on the correction signal from the correction switching means. And

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0021

[Correction method] Change

[Correction contents]

In this case, when the ECC is used in the multi-valued memory, the presence / absence of defect / defect position information is stored in the redundant memory cell (4 bits) of the least significant bit data (8 bits) of each cell. (bit data other than the least significant bit data) redundancy eye (8 bits) of the bit data
Only the presence or absence of a defect is stored in the memory cell (1 bit) .

Claims (8)

[Claims] 1. A defect repairing memory cell which stores a plurality of bit data in one memory cell and corrects a defective bit by using data stored in a redundant cell. A memory cell for remedying a defect, wherein a remedy range is limited when a set specific bit has a defect. 2. The method according to claim 1, wherein the presence / absence of the failure of the specific bit and information on the location of the failure are stored in the redundant cell corresponding to the specific bit, and the failure of the bit corresponding to each of the redundant cells corresponding to bits other than the specific bit is stored. 2. The defective relief memory cell according to claim 1, wherein information on only the presence or absence is stored. 3. The defect relief according to claim 1, wherein the redundant cell corresponding to the specific bit includes an unused area of the redundant cell corresponding to a bit other than the specific bit. Memory cell. 4. The defective relief memory cell according to claim 1, wherein said specific bit is a least significant bit. 5. A storage device using a memory cell for defect repair which stores a plurality of bit data in one memory cell and corrects a defective bit by using data stored in a redundant cell, wherein the defect relief is performed. The memory cell is configured to limit the rescue range when at least a specific bit set in advance is defective in a defective cell, and the data read from the memory cell for defective remedy is read by the specific bit for each memory cell. Encoding means for encoding the data of the non-specific bits and the data of the bits other than the specific bits; and a parity bit created with the data of the bits other than the specific bits encoded by the encoding means and a parity bit of the bits other than the specific bits. A parity comparator that compares the bits to determine whether there is a defect in the data of bits other than the specific bits. A specific bit error specifying means for generating a specific bit correction signal specifying the presence / absence and position of a defect of the specific bit data based on the specific bit data encoded by the encoding means; A bit error specifying unit other than a specific bit for generating a correction signal for a bit other than the specific bit based on a comparison result of the parity comparing unit and a correction signal for the specific bit of the specific bit error specifying unit, and encoding by the encoding unit Data switching means for selecting and outputting any of the specified bit data and bit data other than the specific bit, a specific bit error signal of the specific bit error specifying means and a signal other than the specific bit. Correction switching for selecting and outputting one of the bit correction signals other than the specific bit of the bit error specifying means. And a correction unit for correcting data from the data switching unit based on a correction signal from the correction switching unit. 6. A method for storing the presence / absence of a failure of the specific bit and failure position information in the redundant cell corresponding to the specific bit, and determining whether a failure of the bit corresponding to each of the redundant cells corresponding to a bit other than the specific bit exists. 6. The storage device according to claim 5, wherein information on only the presence or absence is stored. 7. The storage device according to claim 5, wherein the redundant cell corresponding to the specific bit includes an unused area of the redundant cell corresponding to a bit other than the specific bit. . 8. The storage device according to claim 5, wherein said specific bit is a least significant bit.