JP2000149586A - Semiconductor storage device, application apparatus using the same, and relief method of semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor storage device capable of relieving a defect product by replacing a defect address detected after being assembled and mounted with a relief address, and its application apparatus. SOLUTION: A 256M synchronous DRAM is composed of a memory array, an address buffer, a latch circuit, a predecoder, a relief circuit, a decoder, or the like. Each of relief circuits 7 and 8, respectively, for rows and columns is composed of a defect address storing circuit 21 for storing a defect address detected after assembly, an address comparison and selection circuit 22 for comparing an input address with the stored defect address and selecting the input address if they do not coincide with each other, while selecting a relief address if they coincide with each other, and the like. In normal writing and readout operations, it is possible to select any normal memory cell in the memory array by the input address or any redundant memory cell in the memory array by the relief address, thereby conducting the writing and readout operations.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a rescue technique for a semiconductor memory device, and more particularly to a semiconductor memory device suitable for a rescue method in which a defective address detected after assembly is replaced with a rescue address, an application device using the same, and a semiconductor device. The present invention relates to a technique which is effective when applied to a rescue method of a storage device.

[0002]

2. Description of the Related Art For example, as a technique studied by the present inventor, a remedy method of a DRAM as an example of a semiconductor memory device stores a defective address by cutting a fuse corresponding to a defective address to be relieved in a probe test stage. Then, a technique is considered that includes a rescue circuit that compares the input address with the stored defective address, and when they match, selects a rescue address corresponding to the input address and performs rescue.

[0003] As a technique relating to a rescue method for a semiconductor memory device such as a DRAM, for example, 19
"Advanced Electronics I-9 Ultra LSI Memory" P181, published by Baifukan on November 5, 1994.
To P183.

[0004]

In the above-described rescue method for a DRAM or the like, a defective address can be relieved at a probe inspection stage, but it is difficult to remedy a defect after assembly. For example, if there is a detection failure at the probe inspection stage or a new defect occurs at each stage until the assembly is completed, the product is discarded because there is no remedy for defective products found after assembly. There must be.

[0005] In particular, in a memory module, a memory card, or the like in which a semiconductor memory product is mounted on a substrate,
Even if one semiconductor memory is defective, there is a problem that a defective product must be replaced, which may lead to a decrease in reliability. Further, even if the product specification of the semiconductor memory is satisfied, the compatibility between the semiconductor memory and the system may be poor due to noise or the like in the mounted system, and the semiconductor memory may be defective.

Therefore, an object of the present invention is to focus on a defective product found after mounting after assembling, and to replace a defective address detected after mounting with a rescue address after this assembling so that the defective product can be rescued. An object of the present invention is to provide a storage device, an application device using the same, and a method for relieving a semiconductor storage device.

[0007] The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0008]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, the semiconductor memory device according to the present invention is applied to a circuit for relieving a defective address detected in an inspection step after assembly, and includes a defective address storage circuit for storing a defective address detected after assembly. The input address is compared with the defective address stored in the defective address storage circuit, and if they do not match, the input address is selected. If they match, the rescue address corresponding to the input address is selected. And an address comparison and selection circuit for selecting

In this configuration, after detecting a defective address, a special timing which is not used at the time of normal writing / reading is inputted, and an electrically rewritable EEP is inputted.
A defective address storage circuit such as a ROM is operated to input a previously detected defective address and store it in the defective address storage circuit.

The stored defective address is compared with an input address input during normal writing / reading by an address comparison / selection circuit. If the defective address does not match the input address, the input address is selected as it is. On the other hand, if they match, the rescue address is selected without selecting the input address as it is. At this time, in the latch circuit immediately before the address comparison and selection circuit, the defective address is latched in a signal state that can be easily compared with the input address, so that the address selection time is not delayed.

Furthermore, a first semiconductor memory device which is applied to an application device such as a memory module, a memory card, an IC card, or the like in which the semiconductor memory device is mounted on a substrate, or has a memory array including a plurality of memory cells. And a second semiconductor storage device having a rescue circuit for replacing a defective address detected after mounting the first semiconductor storage device with a rescue address. A storage device and an application device are mounted on a system such as a personal computer.

Further, according to the semiconductor memory device rescue method of the present invention, after assembling the semiconductor memory device or mounting the semiconductor memory device on a substrate, a memory capacity check and a defective address are remedied according to an inspection / rescue program. Automatically, or if installed in the system, incorporate an inspection and rescue program into the system's startup program, check memory capacity, repair defective addresses, and start up from the start of the system. Until completion is automatically performed.

Therefore, according to the semiconductor memory device, the applied device, and the rescue method, it is possible to reduce a product defect rate due to rescue of defective products found after assembly.
Furthermore, the reliability of the system by relieving defective products after the system is mounted can be ensured. In addition, as the remedy address memory range is increased as the rescue range for defective products, the product defect rate of failure in units of mats in addition to bit defects can be significantly reduced.

[0015]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, the same members are denoted by the same reference numerals, and the description thereof will not be repeated.

(Embodiment 1) FIG. 1 is a block diagram showing a semiconductor memory device according to Embodiment 1 of the present invention, and FIG. 2 is a block diagram showing a relief circuit in the semiconductor memory device of this embodiment. 3 is a circuit diagram showing an address comparison / selection circuit, FIG. 4 is an explanatory diagram showing input signals of the address comparison / selection circuit, and FIG. 5 is a flowchart showing a test / repair method for a semiconductor memory device.

First, an example of the configuration of the semiconductor memory device according to the present embodiment will be described with reference to FIG.

The semiconductor memory device of the present embodiment is, for example, a 256M synchronous DRAM and has a word line W
A memory array 1 composed of a plurality of memory cells arranged at the intersections of L and bit lines BL, an address buffer 2 for selecting an arbitrary memory cell in the memory array 1, and a row / column latch circuit 3, 4, predecoders 5, 6, relief circuits 7, 8 and decoders 9, 10,
Read / write sense amplifier 11, main amplifier 12, input buffer 13, and output buffer 14
And a main control circuit / clock generation circuit 15,
Refresh counter 16 and internal voltage generating circuit 17
It is composed of

In this synchronous DRAM, an address Add is input from the outside, and a row address and a column address are generated by an address buffer 2, and the row address is passed through a row-related latch circuit 3, a predecoder 5, and a rescue circuit 7. The input address or the rescue address is input to the decoder 9, and the column address is input to the decoder 10 via the column latch circuit 4, the predecoder 6, and the rescue circuit 8, and the row / column system is input. , Any normal or redundant memory cell in memory array 1 is selected. At the time of writing, the input data I
/ O is written to the selected memory cell in the memory array 1 via the input buffer 13 and the main amplifier 12,
On the other hand, at the time of reading, data is read from the selected memory cell in the memory array 1 as output data I / O via the sense amplifier 11, the main amplifier 12, and the output buffer 14.

In the synchronous DRAM, in addition to the clock CLK, control signals such as a row address strobe signal RAS and a column address strobe signal CA
S, write enable signal WE, chip select signal C
S is input, and the main control circuit / clock generation circuit 15 issues a command based on these control signals,
An internal control signal is generated, and the operation of the internal circuit is controlled by the command and the internal control signal. Further, a power supply voltage Vcc and a ground voltage Vss are supplied as external power supplies,
The internal voltage is generated by the internal voltage generation circuit 17.

The synchronous DR configured as described above
The AM employs a rescue method in which a defective address detected after assembly is replaced with a rescue address, in addition to the rescue at the probe inspection stage. The rescue method after this assembly is performed by the row / column rescue circuits 7 and 8 shown in FIG. 1, and an input address or a rescue address is selected via the rescue circuits 7 and 8. . Although the rescue circuit in the probe test stage is not shown, it is connected between the predecoders 5 and 6 and the decoders 9 and 10 similarly to the rescue circuits 7 and 8 after the assembly.

Next, with reference to FIGS. 2 to 4, a description will be given of the row-type and column-type relief circuits 7 and 8 which replace the defective address after assembly with the relief address, which is a feature of the present embodiment. FIGS. 2A and 2B show an example of the configuration of the relief circuits 7 and 8, wherein FIG.
The signal paths at the time of reading are respectively shown.

In FIG. 2, the rescue circuits 7 and 8 store a defective address storage circuit 21 for storing a defective address detected after assembly, and an input address and a defective address stored in the defective address storage circuit 21. Compare and select the entered address if they do not match,
If they match, an address comparison and selection circuit 22 for selecting a relief address corresponding to the input address, and a defective address which is connected immediately before the address comparison and selection circuit 22 and is stored in the defective address storage circuit 21 are input. A defective address latch circuit 23 that latches the signal to a signal state that is easy to compare with the defective address and does not delay the address selection time, and a power supply voltage booster circuit 24 that generates a voltage for rewriting the defective address storage circuit 21. Have been. The defective address storage circuit 21 is, for example, an electrically rewritable EEPROM or the like.

From the storage of the defective address in the relief circuits 7 and 8, the relief operation by comparing the defective address with the input address is as follows.

(1) After detecting a defective address, a special timing which is not used at the time of normal writing / reading, for example, a timing obtained by modifying the CBR timing in the test mode, etc., is inputted, and an electrically rewritable EEP is inputted.
The defective address storage circuit 21 composed of a ROM or the like is operated. This defective address can be detected by a memory tester or the like when it becomes defective after assembly.

(2) While the defective address storage circuit 21 is operating, a previously detected defective address is input from an external address input terminal, and this defective address is stored in the defective address storage circuit inside the chip. 21 is stored.

(3) The defective address once stored is compared with the input address input during normal writing / reading by the address comparison / selection circuit 22, and if the defective address does not match the input address, the input address is changed. Let it be selected as it is.

(4) On the other hand, if the defective address matches the input address, the rescue address is selected without selecting the input address as it is.

(5) At this time, the defective address once stored is compared with the input address in the defective address latch circuit 23 immediately before the address comparison / selection circuit 22 to be compared with the input address input during normal writing / reading. It is latched in a signal state that is easy to compare, so that the address selection time is not delayed.

(6) When the input address is selected, an arbitrary normal memory cell in the memory array 1 is selected by the input address, and a rescue address replacing the defective address is selected. Is selected, an arbitrary memory cell for redundancy in the memory array 1 can be selected by this rescue address to perform writing / reading.

FIG. 3 shows an example of a circuit configuration of the address comparison / selection circuit 22, and shows an example of three external input addresses. FIG. 4 shows an input example of an address comparison / selection signal in the address comparison / selection circuit 22.

In FIG. 3, the address comparison / selection circuit 22
Are exclusive OR gates EX corresponding to external three input addresses A0, A1 and A2 for comparing the defective address of defective address latch circuit 23 with an external input address.
OR1 to EXOR3 and exclusive OR gate EXOR1
OR gate OR1 which outputs "0" when the outputs of EXOR3 are all "0", when "0" is input to all external input addresses, and when the defective address matches the input address OR gate OR2 and NOR gate NOR2 for distinguishing address "0" from
AND gates AND1 to AND which output address "0" when the defective address and the input address match
And 4.

The rescue circuits 7 and 8 including the address comparison / selection circuit 22 are provided only when the synchronous DRAM is set to the defective address storage mode, the power supply voltage boosting circuit 24 of the internal circuit, the storage circuit operation instruction circuit 25, and the defective address storage. The circuit 21, the defective address latch circuit 23, the address comparison and selection circuit 22 and the like operate, and based on the defective addresses A0 to A2 stored in the defective address storage circuit 21 and the input addresses of A0 to A2 input from outside. A0
The signal after the address input conversion of A3 is output. Note that, in a normal operation mode, these internal circuits are not operated. Also, the memory circuit operation instruction circuit 2
5 is in the OFF state at the time of normal writing / reading, the data of the defective address storage circuit 21 whose operation is controlled by the storage circuit operation instruction circuit 25 is not changed.

As shown in FIG. 4, the storage failure address in the external three input addresses is A0 / A1 / A2 = 0/0 /
0, 1/0/0, 0/1/0, 1/1/0, 0/0 /
There are eight combinations of 1, 1/0/1, 0/1/1, 1/1/1, and in the case of address selection by the corresponding external input address and internal relief address, 3
There is a street.

The case (1) is a case where the storage failure address matches the external input address. In this case, the rescue address address “0” is selected and designated. For example,
In the example of A0 / A1 / A2 = 1/0/0, the designated address is "1" by the A0 address input signal "1", the A1 address input signal "0", and the A2 address input signal "0" of the external input address. Are designated, and the A0 address input converted signal "0", the A1 address input converted signal "0", the A2 address input converted signal "0", and the A3 address signal "0" of the internal relief address are used to specify the designated address. “0” is selected.

Case (2) is a case where the storage failure address does not match the external input address. In this case, the external input address is directly selected as the internal address. For example, in the example of A0 / A1 / A2 = 1/0/0, the A0 address input signal “0” of the external input address,
The designated address "2" is designated by the A1 address input signal "1" and the A2 address input signal "0".
"2" at the designated address is selected by the A0 address input converted signal "0", the A1 address input converted signal "1", the A2 address input converted signal "0", and the A3 address signal "0" of the internal rescue address. Is done.

Case (3) is a case where the external input address is "0" input. In this case, "8" is selected because it is necessary to distinguish it from the relief address "0". For example, in the example of A0 / A1 / A2 = 1/0/0, the A0 address input signal “0” of the external input address,
The designated address “0” is designated by the A1 address input signal “0” and the A2 address input signal “0”,
"8" of the designated address is selected by the A0 address input converted signal "0" of the internal rescue address, the A1 address input converted signal "0", the A2 address input converted signal "0", and the A3 address signal "1". Is done.

In the other combinations, as in the above case, as in the above case, the rescue address address "0" is selected based on the comparison between the defective memory address and the external input address (1). Case (2) to select, Case (3) to select “8” because it is necessary to distinguish it from the relief address “0”
Can be selected.

Next, based on FIG.
An inspection / repair method by software control including a rescue program incorporated in an inspection program for AM selection will be described.

(1) After assembling the synchronous DRAM, the memory capacity of the memory array 1 is automatically checked according to an inspection / repair program (step 501).
This check item is the same as the inspection item in the normal inspection.

(2) As a result of this check, if a defective address is detected, the defective address is stored in the defective address storage circuit 21 of the rescue circuits 7 and 8 and relieved (step 502). This rescue method is as described above. On the other hand, if no defective address is detected, it is a non-defective product.

(3) After this relief, the memory capacity of the memory array 1 is checked again (step 503). In this re-check, the processing from the rescue process of step 502 is repeated until all the defective addresses are replaced with the rescue addresses. As a result, defects can be remedied after assembly, and defective products can be remedied to be non-defective products.

Therefore, according to the semiconductor memory device of the present embodiment, the assembling relief circuits 7, 8 including the defective address storage circuit 21, the address comparison and selection circuit 22, and the like are provided, so that it becomes clear after the assembling. The defective address to be replaced can be replaced with the rescue address, and the product defect rate due to the remedy for the defective product can be reduced. In addition, as the remedy address memory range is increased as a remedy range for defective products, it is considered that, in addition to the bit property defect, the product defect rate of failure in units of mats can be significantly reduced.

That is, by replacing the defective address with another rescue address, it is not necessary to select the defective address in the current product. Further, at present, the defect can be repaired only at the stage before the assembling, but can also be repaired after the assembling as in the present embodiment. Furthermore, the current product is highly likely to be determined to be defective after assembly, and there is no remedy for a defective product after assembly, so 100% of defective products cannot be remedied and have been discarded. , It is possible to cope with this.

(Embodiment 2) FIG. 6 is a block diagram showing a memory module mounted with a semiconductor memory device according to Embodiment 2 of the present invention.

As shown in FIG. 6, for example, the memory module according to the present embodiment has a memory array, an address buffer, and a row / column latch circuit obtained by removing a relief circuit from the semiconductor memory device of the first embodiment. , Pre-decoder, decoder, sense amplifier, main amplifier, input buffer, output buffer, main control circuit / clock generation circuit, refresh counter, internal voltage generation circuit, etc.
2 and a defective address detected after mounting the synchronous DRAMs 31 and 32 is replaced with a repair address.
A rescue ROM 33 having a rescuing circuit after mounting similar to that of the first embodiment is mounted on a module substrate 34.

That is, in the rescue ROM 33, FIG.
As shown in detail in (a), the same as in the first embodiment,
Defective address storage circuit 21, address comparison and selection circuit 2
2. A rescue circuit including a defective address latch circuit 23 and a power supply voltage booster circuit 24 is provided.

In this configuration, the synchronous DRAM
By incorporating the rescue program into the inspection program of the memory module on which the rescue ROM 33 is mounted, first, the synchronous DRAMs 31, 32,
After the rescue ROM 33 is mounted, the memory capacity of the memory arrays of the synchronous DRAMs 31 and 32 is automatically checked in accordance with the inspection and rescue program. As a result of this check, if a defective address is detected, the defective address is replaced The data is stored in the defective address storage circuit 21 of the ROM 33 and relieved.

After this rescue, the memory capacity of the memory array of the synchronous DRAM is rechecked. In this recheck, the processing from the rescue step is repeated until all defective addresses are replaced with the rescue address. DRAMs 31, 32, rescue ROM
Defect relief can be performed on a memory module in which 33 is mounted on a module substrate 34.

At the time of normal writing / reading, the address inputted from the outside is compared with the defective address stored in the defective address storage circuit 21 of the rescue ROM 33 by the address comparison / selection circuit 22, and the defective address and the input address are compared. If the address does not match, an arbitrary normal memory cell in the memory array of the synchronous DRAM 31, 32 is selected by the input address. On the other hand, if the defective address matches the input address, the synchronous DRAM 31 is selected by the repair address. , 32, select an arbitrary memory cell for redundancy, and
Reading can be performed.

Therefore, according to the memory module of the present embodiment, the synchronous ROM 33 having the mounted relief circuit is mounted on the module substrate 34 on which the synchronous DRAMs 31 and 32 are mounted. By replacing the defective address found after mounting the eggplant DRAMs 31 and 32 with the rescue address, it is possible to reduce the product defect rate due to the remedy of the defective product. In addition, as the rescue address memory range is increased as a remedy range for defective products, the product failure rate of failure in the unit of mats and the product of the synchronous DRAMs 31 and 32 is greatly increased in addition to the defectiveness of bits in addition to the bit failure. It is thought that it can be reduced.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the embodiment, and various modifications may be made without departing from the gist of the invention. It goes without saying that it is possible.

For example, in the first embodiment,
The case where the present invention is applied to a 256M synchronous DRAM has been described, but the present invention is not limited to this.
The present invention can be widely applied to synchronous DRAMs which tend to have a large capacity such as M or 1G, and the effect of the present invention is further increased by adopting such a large capacity configuration. Furthermore, the present invention is effective not only for synchronous DRAM but also for other semiconductor memories such as general-purpose DRAMs, Rambus DRAMs, and SRAMs, and can be applied to products such as system LSIs including these semiconductor memories. It is.

In the second embodiment, the memory module in which the synchronous DRAM and the rescue ROM are mounted has been described. However, the present invention can be applied to other application devices in which a semiconductor memory such as a memory card and an IC card is mounted. Can be widely applied. Further, when the product is commercialized as an application device such as a memory module, a memory card, or an IC card, it is possible to incorporate a rescue circuit in a semiconductor memory without independently providing a rescue ROM.

Further, the defective address storage circuit of the rescue circuit built in the synchronous DRAM and the rescue ROM, which is a feature of the present invention, is not limited to the EEPROM, but may be another ROM such as an EPROM or a PROM in which data can be rewritten. It is needless to say that is also applicable.

When a commercialized semiconductor memory, application device, or the like is mounted on a system such as a personal computer that checks the capacity of the mounted memory when the power is turned on, this system is started up. Inspection and rescue programs are incorporated into the program, and from the start of the system to memory capacity check, remedy of defective addresses, and completion of the start can be automatically performed.

When mounted in the system as described above, the reliability of the system can be ensured by relieving defective products after the system is mounted. That is, at present, there is a problem that a defective semiconductor device must be replaced with a defective semiconductor memory even after one system is mounted, which may lead to a decrease in reliability. Countermeasures become possible. In addition, even if the product specifications of the semiconductor memory are satisfied, the compatibility between the semiconductor memory and the system may be poor due to the noise of the mounted system or the like, which may cause a failure. Becomes possible.

[0058]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

(1) By having a storage circuit for a defective address and a circuit for comparing and selecting an input address and a defective address as a rescue circuit for a defective address detected after assembly,
Since defective products found after assembling can be rescued, it is possible to reduce the defective rate of semiconductor memory products due to defective product rescue.

(2) In the above (1), a memory module, a memory card, a semiconductor memory device mounted on a substrate,
When applied to an application device such as an IC card, a defective product found after mounting can be rescued, so that the defect rate of the applied product due to the remedy of the defective product can be reduced.

(3) In the above (1) and (2), when the semiconductor memory device and the applied device are mounted on a system such as a personal computer, defective products after mounting the system can be rescued. It is possible to secure the reliability of the system by relieving defective products.

(4) In the above (1) to (3), as the rescue address memory range is increased as a rescue range for defective products, in addition to bit defects, defects in mat units and product units are determined. It is possible to significantly reduce the defective rate.

(5) According to the above (1) to (4), in a semiconductor memory device, an application device in which the semiconductor device is mounted, and a system in which these devices are mounted, after the semiconductor memory device is assembled and mounted in the application device, In addition, defective products detected after mounting on the system can be relieved with high reliability.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a semiconductor memory device according to a first embodiment of the present invention;

FIGS. 2A and 2B are block diagrams showing a relief circuit in the semiconductor memory device according to the first embodiment of the present invention;

FIG. 3 is a circuit diagram showing an address comparison and selection circuit in the semiconductor memory device according to the first embodiment of the present invention;

FIG. 4 is an explanatory diagram showing input signals of an address comparison and selection circuit in the semiconductor memory device according to the first embodiment of the present invention;

FIG. 5 is a flowchart showing an inspection / repair method for the semiconductor memory device according to the first embodiment of the present invention;

FIGS. 6A and 6B are block diagrams showing a memory module on which a semiconductor memory device according to a second embodiment of the present invention is mounted;

[Explanation of symbols]

 1 Memory Array 2 Address Buffer 3,4 Latch Circuit 5,6 Predecoder 7,8 Rescue Circuit 9,10 Decoder 11 Sense Amplifier 12 Main Amplifier 13 Input Buffer 14 Output Buffer 15 Main Control Circuit / Clock Generation Circuit 16 Refresh Counter 17 Voltage generation circuit 21 Defective address storage circuit 22 Address comparison and selection circuit 23 Defective address latch circuit 24 Power supply voltage booster circuit 25 Storage circuit operation instruction circuit 31, 32 Synchronous DRAM 33 Rescue ROM 34 Module board EXOR1-EXOR3 Exclusive OR gate OR1, OR2 OR gate NOR1 NOR gate AND1 AND4 AND gate

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (reference) G11C 11/401 G11C 11/34 362S 371D F term (reference) 5B015 JJ11 KB41 NN09 5B018 GA03 GA06 HA21 JA22 KA13 KA17 MA24 NA02 NA10 5B024 AA03 AA15 BA29 CA07 CA15 EA01 5B035 AA11 BB09 CA29 CA31 5L106 AA01 AA02 CC09 DD25

Claims (9)

[Claims] 1. A memory array comprising a plurality of memory cells, and a relief circuit for replacing a defective address detected after assembling the memory array with a relief address,
The rescue circuit compares a defective address storage circuit storing a defective address detected after the assembling with the input address and a defective address stored in the defective address storage circuit. An address comparison and selection circuit for selecting the input address and selecting a relief address corresponding to the input address when the input address matches. 2. The semiconductor memory device according to claim 1, wherein a signal which makes it easy to compare a defective address stored in said defective address storage circuit with said input address immediately before said address comparison and selection circuit. A semiconductor memory device having a latch circuit for latching in a state. 3. The semiconductor memory device according to claim 1, wherein said defective address storage circuit is an electrically rewritable ROM. 4. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is a semiconductor memory,
Alternatively, the semiconductor storage device is a system LSI including a semiconductor memory. 5. An applied device using the semiconductor memory device according to claim 1, wherein the semiconductor memory device is mounted on a substrate, and a defective address detected after mounting by the rescue circuit. An application device characterized by being a memory module, a memory card, or an IC card, which can be replaced with a relief address. 6. A second semiconductor memory device comprising: a first semiconductor memory device having a memory array including a plurality of memory cells; and a relief circuit for replacing a defective address detected after mounting the first semiconductor memory device with a relief address. A semiconductor memory device and a memory module, a memory card, or an IC card mounted on a substrate, wherein the rescue circuit includes a defective address storage circuit that stores a defective address detected after mounting; The defective address is compared with the defective address stored in the defective address storage circuit. If they do not match, the input address is selected, and if they match, the repair address corresponding to the input address is selected. An application device, comprising: an address comparison / selection circuit. 7. A rescue method for a semiconductor memory device, comprising: a memory array including a plurality of memory cells; and a rescue circuit for replacing a defective address detected after assembling the memory array with a rescue address. Automatically checking the memory capacity of the memory array according to an inspection / rescue program after assembling the semiconductor memory device or mounting the semiconductor memory device on a substrate. As a result of this check, if a defective address is detected, A step of storing the defective address in a defective address storage circuit of the rescue circuit to rescue the memory, and a step of rechecking the memory capacity of the memory array after the rescue; Until the address is replaced with the relief address. A method for relieving a semiconductor memory device, comprising: 8. A second semiconductor device comprising: a first semiconductor memory device having a memory array composed of a plurality of memory cells; and a relief circuit for replacing a defective address detected after mounting the first semiconductor memory device with a relief address. A semiconductor memory device mounted on a substrate, the method for repairing the first semiconductor memory device, wherein after the first semiconductor memory device is mounted on the substrate, the semiconductor memory device A step of checking the memory capacity of the memory array, a step of storing the defective address in a defective address storage circuit of the rescue circuit when a defective address is detected as a result of the check, and relieving the memory after the rescue. Re-checking the memory capacity of the array. In this re-checking step, all of the defective addresses are replaced with a repair address. A method for relieving a semiconductor memory device, wherein the processing from the step of relieving is repeated until replacement. 9. The rescue method for a semiconductor memory device according to claim 7, wherein when the semiconductor memory device is mounted on a system, the test and rescue program is added to a start-up program of the system. A method for relieving a semiconductor memory device, comprising: automatically starting from the start of the system, checking the memory capacity, relieving a defective address, and completing the start of the system.