JP2000149576A - Nonvolatile semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory which makes it possible to suppress the increase of the read time of a multivalued memory and realize a high speed read and the reduction of the write disturbance. SOLUTION: In reading, specified voltages are applied to word lines and source lines to set the voltage of the bit line BL according to the threshold voltage of a selected memory cell, the level change of a node ND0 is detected with a stepwise varying level type read signal VBLA3H applied to the gate of a high-withstand voltage transistor N1, thereby judging the voltage of the bit line BL. Since the voltage setting is once applied to a word line having a large time constant and the level-varying read voltage is applied to the gate of the transistor N1 having a small time constant, the read can be speeded up. In writing, a higher voltage than a power voltage can be applied to the bit line, thereby reducing the write disturbance.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device, and more particularly to a multivalued nonvolatile semiconductor memory device capable of storing data of two bits or more in one memory cell (storage element).

[0002]

2. Description of the Related Art In a conventional multi-valued memory, for example, a so-called NAND type multi-valued memory composed of a memory column in which a plurality of memory cells are connected in series between a bit line and a source line, a word is read when data is read. The line voltage is changed in any number of steps. Each time the potential of the word line and the bit line is stabilized, the bit line potential is sensed, and the data stored in the selected memory cell is read in accordance with the bit line potential.

[0003]

By the way, in the above-mentioned conventional nonvolatile multi-valued memory, the lengths of word lines and bit lines are increased with an increase in the storage capacity of the semiconductor memory device, and these signal lines are driven. In this case, the load capacity is increasing. As a result, the time constants of the word lines and the bit lines are increased, and when driving, the waiting time until the potential is stabilized becomes longer. As the number of values further increases, the number of bits of data stored in each memory cell increases, and the number of steps for setting the word line voltage at the time of reading increases, so that a long time is required for reading. Also, to reduce write disturb,
It is necessary to apply a write voltage according to the write data to the bit line.However, in order to reduce the size of the data latch circuit, standard transistors are used in this circuit, and therefore a high voltage higher than the power supply voltage must be applied. Not be able to
There is a disadvantage in that the range of voltages that can be applied to the bit lines is narrowed, and there is a limit in reducing write disturb.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a nonvolatile semiconductor memory capable of suppressing an increase in the read time of a multilevel memory and realizing high-speed read and write disturbance reduction. It is to provide a device.

[0005]

In order to achieve the above object, a nonvolatile semiconductor memory device according to the present invention has a threshold voltage according to the amount of charge stored in a charge storage layer insulated from the surroundings. Is controlled, a control terminal is connected to a word line, and an input / output terminal is a nonvolatile semiconductor memory device including storage elements connected to a source line and a bit line, respectively. A read bias means for holding a source line voltage, applying a predetermined word line voltage to the word line, and setting the bit line to a level corresponding to a threshold voltage of the storage element; a read node; A data transmission circuit connected between the read line and the read node for transmitting data corresponding to the bit line voltage to the read node according to an input level of a read signal; A transistor and a read signal having a plurality of levels that sequentially change are applied to a control terminal of the data propagation transistor at the time of reading, a level change of the read node is detected, and data read to the bit line is read. Reading means for determining.

More specifically, the nonvolatile semiconductor memory device of the present invention holds the source line at a predetermined source line voltage at the time of reading, applies a predetermined word line voltage to the word line, Read bias means for setting a bit line to a level corresponding to a threshold voltage of the storage element; a read node connected between the bit line and the read node; A data propagation transistor for transmitting data corresponding to a bit line voltage to the read node; a read potential holding circuit for amplifying a potential of the read node at the time of reading and holding the amplified potential; A first node set to a first level according to the potential held by the read potential holding circuit A second node set to a second level in accordance with the applied potential, and two inverters having an input terminal and an output terminal connected to each other, and a connection point of one of the input / output terminals is a first node. A first data latch circuit connected to the first node via a gate, and a connection point of the other input / output terminal connected to the second node via a second gate; And an output terminal are connected to each other, and one connection point of the input / output terminal is connected to the first inverter through a third gate.
And a connection point of the other input / output terminal is connected to the second node via a fourth gate, and a plurality of connection points are provided according to the number of bits of storage data of the storage element. A second data latch circuit, and after the voltage of the read node is held by the read voltage holding circuit in verification after reading and writing, the first and second data latch circuits are operated in accordance with the held voltage. And a latch data setting circuit for setting the respective latch data.

In the present invention, preferably, the data propagation transistor is constituted by a high breakdown voltage transistor.

Further, in the present invention, preferably, the read bias means includes a source line voltage applying means for applying the source line voltage to the source line, and a word line for applying the word line voltage to the word line. And voltage erasing means for erasing data stored in the memory element before writing, and erasing means for controlling the threshold voltage to be distributed within a predetermined range.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a circuit diagram showing one embodiment of a nonvolatile semiconductor memory device according to the present invention, and is a circuit diagram showing a configuration of a bit line potential setting circuit for setting a bit line potential. As shown, this bit line potential setting circuit
A plurality of nMOS transistors N1 to N13, which are turned on / off according to an input signal, and pMOS transistors P1 to P
7. It is composed of inverters INV1 and INV2 and a NAND gate NAND1. The nMOS transistors N1 and N2 are high breakdown voltage transistors that can withstand a voltage higher than the power supply voltage V _CC . Here, the transistor N1 is a data transmission transistor that transmits read data to a node ND0 which is a read node in accordance with a bit line potential at the time of reading.

As shown, the transistor N2 is connected between the bit line BL and the node ND0, and its gate is connected to the input terminal of the signal TRN. Node ND0
Is connected to the node ND1 via the transistor N13. The gate of the transistor N13 is connected to the input terminal of the signal RD1. The node ND1 is connected to a data latch circuit (shown in FIG. 2) described later.

The transistors N1 and P1 are connected in series between the bit line BL and the node ND4. A node ND3 is formed by a connection point between the transistors N1 and P1. The transistor P2 is connected between the node ND4 and the input terminal of the signal VBL3. The gate of the transistor N1 is connected to the input terminal of the signal VBLA3H, and the gate of the transistor P1 is connected to the input terminal of the signal VBL3D. Further, the gate of the transistor P2 is connected to the node ND2.

A transistor P3 is connected between the node ND2 and the input terminal of the signal VBL3. Node ND
2 and node ND0, transistors P4 and N3, N
4 are connected in series. The gate of the transistor P3 is connected to the node ND4, the gates of the transistors P4 and N3 are both connected to the input terminal of the signal VBL3D, and the gate of the transistor N4 is connected to the input terminal of the signal VBLP3.

One input terminal of NAND gate NAND1 is connected to node ND1, and the other input terminal is connected to signal V.
It is connected to the input terminal of BLP. Inverter INV
The input terminal of No. 1 is connected to the output terminal of NAND gate NAND1, and its output terminal is connected to node ND5. The input terminal of the inverter INV2 is connected to the node ND5.

Transistors P6 and P7 are connected in series between node ND4 and the input terminal of signal VBL2.
The gate of the transistor P6 is connected to the input terminal of the signal VBLA2B, and the gate of the transistor P7 is connected to the inverter I via the transistors P5 and N5 connected in series.
It is connected to the output terminal of NV2. Transistor P5
Is connected to the input terminal of the signal VBLP2D, and the gate of the transistor N5 is connected to the input terminal of the signal VBLP2.

Transistors N7 and N8 are connected in series between node ND0 and the input terminal of signal VBL1.
The gate of the transistor N7 is connected to the input terminal of the signal VBLA1, and the gate of the transistor N8 is connected to the node ND5 via the transistor N6. The gate of the transistor N6 is connected to the input terminal of the signal VBLP1.

Transistors N10 and N11 are connected in series between node ND0 and ground potential GND. The gate of the transistor N10 is connected to the input terminal of the signal VBLA0, and the gate of the transistor N11 is connected to the node ND5 via the transistor N9. The gate of the transistor N9 is connected to the input terminal of the signal VBLP0.

A transistor N12 is connected between the node ND0 and the ground potential GND. The gate of the transistor N12 is connected to the input terminal of the signal BLDIS.

FIG. 2 shows the configuration of the data latch circuit connected to node ND1. As shown in the figure, the data latch circuit includes latch circuits 10, 20, 30, 40.
And other circuits are provided.

The latch circuit 10 includes inverters 12 and 14. The input terminal of inverter 12 is connected to node ND1. The inverter 14 is a pMOS
It comprises transistors P21 and P22 and nMOS transistors N20 and N21. Connected in series between the transistors P21, P22 and N20, N21 of the supply line of the power supply voltage V _CC and the ground potential GND.
The gates of the transistors P21 and N21 are connected, and the connection point forms the input terminal of the inverter 14, and the connection point between the drains of the transistors P22 and N20 forms the output terminal of the inverter 14. The gate of the transistor N20 is connected to the input terminal of the control signal RD1ST, and the gate of the transistor P22 is connected to the inverted signal of the control signal RD1ST.
It is connected to the input terminal of RD1ST.

As described above, the input terminal of the inverter 12 is connected to the node ND1. Further, the input terminal of the inverter 14 is connected to the output terminal of the inverter 12, and the output terminal of the inverter 14 is connected to the node ND1. Further, a transistor P20 is connected between the node ND1 and a supply line of the power supply voltage V _CC , and a gate of the transistor P20 is connected to an input terminal of the signal DATRSTB.

At the time of reading, the inverter 14 operates by holding the control signal RD1ST at a high level. The potential of the node ND1 is latched by the latch circuit 10 constituted by the inverters 12 and 14. Since the potential of the node ND1 is held at the same potential as the bit line BL, the latch data of the latch circuits 30 and 40 is set according to the potential of the node ND1, and the storage data of the selected memory cell is set according to the latch data. Is read.

Transistors N22 and N23 are connected in series between node ND1 and ground potential GND. The gate of the transistor N22 is connected to the node ND6, and the gate of the transistor N23 is connected to the input terminal of the signal DAT. Further, the node ND1 and the ground potential GND
Are connected in series between the transistors N24 and N25. The gate of the transistor N24 is connected to the node ND7, and the gate of the transistor N25 is connected to the input terminal of the signal DATC. Transistor N26 is connected between nodes ND6 and ND8, and has its gate connected to the input terminal of signal RD2. Transistor N27 is connected between nodes ND7 and ND8, and has its gate connected to the input terminal of signal RD2C. Transistor N28 is connected between node ND8 and ground potential G.
ND, and its gate is connected to the node ND1.

A transistor N36 is connected between the node ND6 and the ground potential GND, and a gate of the transistor N36 is connected to an input terminal of the signal LATST. The transistor N3 is connected between the node ND7 and the ground potential GND.
7 is connected, and the gate of the transistor N37 is connected to the signal LA.
It is connected to the input terminal of TSTC.

The latch circuit 20 includes inverters INV3 and INV4 whose input terminals and output terminals are connected to each other. One terminal of the latch circuit 20 is connected to a node ND6 via a transistor N30, and the other terminal is connected to a node ND7 via a transistor N31. The gates of the transistors N30 and N31 are connected to the input terminal of the signal LATA.

The latch circuit 30 comprises inverters INV5 and INV6 whose input terminals and output terminals are connected to each other. One terminal of the latch circuit 30 is connected to the node ND6 via the transistor N32, and the other terminal is connected to the node ND7 via the transistor N33. The gates of the transistors N32 and N33 are connected to the input terminal of the signal LAT0.

The latch circuit 40 includes inverters INV7 and INV8 whose input terminals and output terminals are connected to each other. One terminal of the latch circuit 40 is connected to the node ND6 via the transistor N34, and the other terminal is connected to the node ND7 via the transistor N35. The gates of the transistors N34 and N35 are connected to the input terminal of the signal LAT1.

Node ND6 is connected to data input / output terminal IO via transistor N38, and node ND7 is connected to data input / output terminal / IO via transistor N39. The gates of the transistors N38 and N39 are connected, for example, to the column signal line Y1.

FIG. 3 shows the configuration of one page of memory cells consisting of a plurality (here, N + 1) of memory cells connected to the bit line BL. Here is the so-called NA
1 shows an example of an ND type multi-valued memory. As shown, N + 1 memory cell bit lines BL and source lines SL
Are connected in series between

As shown, (N + 1) memory cells MC0, MC1,..., MCn, MCn + 1,.
Are controlled by word lines WL0, WL1,.
WLN, WLn + 1,..., WLN. The memory cell MC0 is connected to the source line side select transistor NTS.
Is connected to the source line SL, and the memory cell MCN is connected to the bit line BL via the select transistor NTB on the bit line side. The gate of the transistor NTS is connected to the input terminal of the source line control signal SSG, and the gate of the transistor NTB is connected to the input terminal of the bit line control signal DSG.

As shown in FIG. 1, the bit line BL is connected to a node ND0 via a transistor N2, and the node ND0 is connected to a node ND1 via a transistor N13. On the other hand, the source line SL
Are maintained at a predetermined potential at the time of reading.

Each of the memory cells MC0, MC1,
..., MCn, MCn + 1, ..., MCN can, for example, the threshold voltage V _th are both held at a predetermined erase level by collective erasing. By programming after erasure, each memory cell is held at a different level according to write data. FIG. 4 is a distribution diagram showing the relationship between storage data and the distribution of threshold voltage _Vth in a quaternary memory capable of storing 2-bit data in one memory cell.

As shown, the threshold voltages of the memory cells in the erased state are distributed around V _th3 . The storage data of the memory cell corresponding to this is “11”. By programming, the threshold voltage of the memory cell becomes V _th2 ,
It is set to be distributed in three regions centered on V _th1 and V _th0 . Each area is "1" of data
0 ”,“ 01 ”, and“ 00. ”At the time of reading, if it is possible to detect which of the four regions including the erase region the threshold voltage of the selected memory cell has, The stored data can be read.

FIG. 4 shows the threshold voltage V of the four-valued memory.
_Although the example of the distribution of _th is shown, as the number of values increases, the number of bits that can be stored in each memory cell increases, and the number of distributions of the threshold voltage _Vth of the memory cell also increases. For example, in the case of an eight-valued memory, the threshold voltage _Vth of each memory cell is controlled so as to be distributed in eight regions. In this case, the read voltage applied to the word line WL at the time of reading becomes a plurality of levels, and the number of times of reading increases.

In the nonvolatile semiconductor memory device of this embodiment, the source line SL and the selected word line are held at a predetermined voltage after the bit line BL is discharged to the ground potential GND at the time of reading. As a result, the bit line BL is held at a level corresponding to the threshold voltage of the selected memory cell, so that the latch data of each latch circuit is set in a latch circuit portion to be described later according to the bit line potential. The data stored in the memory cell is read. In the verification after writing, unlike the data latch circuit of the conventional multi-valued memory, the data loaded in the latch circuit is not destroyed, so that the verification can be easily performed repeatedly. By gradually reducing the increase ΔV _pgm of the program voltage, the distribution of the threshold voltage V _th can be narrowed. On the other hand, at the time of writing, FIG.
Can set the bit line BL to four different levels in accordance with the write data. When the number of levels increases further than binary, the number of steps of the voltage applied to the bit line can be increased, and the optimum number of steps of the bit line voltage is determined based on the disturb characteristic of the memory cell. You can also.

The respective operations of the present embodiment will be described below with reference to FIGS. 5 to 8 based on signal changes at each stage of reading, data loading, before programming, verifying, and writing in the present embodiment. .

[0036] Read Operation Figure 5 shows signal waveforms at the time of reading. Hereinafter, FIG.
The read operation in the present embodiment will be described with reference to the waveform diagram of FIG. 1 and the circuit diagrams of FIG. 1, FIG. 2, and FIG. In the multi-level memory according to the present embodiment, at the time of reading, the bit line is discharged to a low voltage, for example, the ground potential GND, then the source line is held at a predetermined high voltage, and a fixed level voltage is applied to the selected word line. . In addition, a pass voltage is applied to the unselected word lines to sufficiently conduct the unselected memory cells connected to the unselected word lines. For this reason, the bit line is driven via the selection transistor whose fixed voltage is applied to the gate by the source line which is at a high voltage, and the other non-selection transistor which is in a conductive state.
The potential of the bit line differs depending on the threshold voltage of the selected memory cell. For example, when the threshold voltage of the selected memory cell is high, the equivalent resistance of the selected memory cell is large and the potential of the bit line is low. Conversely, when the threshold voltage of the selected memory cell is low, the equivalent resistance of the selected memory cell is low, and the potential of the bit line increases. Therefore, the threshold voltage of the selected memory cell can be detected according to the driven bit line potential, and the data stored in the selected memory cell can be read.

Here, it is assumed that 2-bit data is stored in each memory cell shown in FIG. 3, and the threshold voltage V _th of each memory cell is set to 4 as shown in FIG. Are distributed in two different ranges. That is, when the storage data of the memory cell is “00”,
The threshold voltage is set to the highest level, and the threshold voltages of the memory cells are set to be lower in the order of "01", "10", and "11" for the stored data.

As shown in FIG. 5, after reading is started, first, the signals TRN and BLDIS are held at a high level. Accordingly, transistors N2 and N2 shown in FIG.
12 turns on, and the bit line BL and the node ND0 are discharged to the ground potential GND. When the source line SL and the selected word line are each set to a predetermined potential, the potential of the bit line BL is set according to the threshold voltage of the selected memory cell. That is, the potential of the bit line BL is determined by the data stored in the selected memory cell.

Specifically, the word line W shown in FIG.
Assuming that Ln is a selected word line, for example, a voltage VSL is applied to the source line SL, and a voltage VR substantially equal to the source line voltage VSL is applied to the selected word line WLn. A voltage V _pass higher than the voltage VR by about 2 V is applied to word lines other than the selected word line WLn. A voltage VSG higher than the source line voltage VSL by about 2 V is applied to the gates of the transistors NTS and NTB on the source line side and the bit line side, respectively. The signal VBL3 shown in FIG.
For example, a voltage higher than L by about 1 V is maintained.

In the above-mentioned bias state, _assuming that the threshold voltage of the selected memory cell MCn is V _thn , the potential VBL of the bit line BL becomes (VSL−V _thn ). Further, assuming that the threshold voltage of the high breakdown voltage transistor N2 shown in FIG. 1 is V _THR , the level of the voltage VBLA3H applied to the gate of the high breakdown voltage transistor N1 is set as in the following equation.

[0041]

## EQU1 ## 0 ≦ VBLA3H−V _THR ≦ VSL

Then, (VBLA3H-V _THR > VB
At the time of L), the transistor N1 turns on, and the potential of the node ND3 formed at the midpoint of the connection between the transistor N1 and P1 changes from VBL3 to the bit line potential VBL.

The source line SL has a source line potential V in advance.
SL, the source line side select transistor NT
A similar result can be obtained by raising the signal SSG input to the gate of S from low level to about 2 V from the source line potential VSL.

When the signal VBLP3 is held at the high level when the node ND0 is held at the ground potential GND, the transistor N4 to which the signal VBLP3 is applied to the gate is turned on, and the node ND2 is at the low level.
However, the node ND2 is connected to the signal VBL3D by the transistors N4 and P4 to which the signal VBL3D is applied to the gate.
It only drops to about the same potential. When the node ND2 goes low, the transistor P2 turns on and the node N2
D4 and ND3 are held at substantially the same potential as signal VBL3.

As shown in FIG. 5, first, the signal VBLA3
Since H is maintained at 0 V, the high breakdown voltage transistor N1 is turned off. Now it is increased signals VBLA3H stepwise, as described above, (VBLA3H-V _THR> VB
At the time of L), the transistor N1 turns on, and the potential of the node ND3 formed at the midpoint of the connection between the transistor N1 and P1 changes from VBL3 to the bit line potential VBL. Since the potential at the node ND4 is lower than the potential of the signal VBL3, the transistor P3 whose gate is connected to the node ND2 is turned on, and the potential at the node ND2 changes from the potential of the signal VBL3D to the signal VB3.
It rises to the potential of L3. Here, by setting the signal VBLP3 to the high level, the transistor N4 is turned on, the node ND0 rises from 0V to (V _CC -V _th). In this state, by setting the control signal RD1 applied to the gate of the transistor N13 to a high level, the transistor N13 is turned on, and the level of the node ND0 is reflected on the node ND1.

At this time, as shown in FIG.
The signal RD1ST input to 0 is held at a high level. In response, inverter 14 is activated, and node ND1 is held at the level by latch circuit 10 including inverters 12 and 14. Note that since the signal DATRSTB is held at a high level, for example, at the level of the power supply voltage V _CC during reading, the transistor P20 shown in FIG. 2 is kept off.

After the potential of the node ND1 is held by the latch circuit 10, the latch data of the latch circuits 20, 30 and 40 are set according to the held potential. If the potential level of the node ND1 is detected from a low level to a high level while changing the level of the signal VBLA3H stepwise, the bit line B
The L potential VBL can be known, and data stored in the selected memory cell can be read.

First, the latch circuit is initialized. Signals LATSTC, LATA, LAT0, and LAT1 are all held at a high level. In response, transistor N37 turns on, and node ND7 is held at ground potential GND. Further, the respective terminals of the latch circuits 20, 30 and 40 and the transistors N30 to N35 between the nodes ND6 and ND7 are both turned on, and in the latch circuit 20, the terminal on the node ND6 side is at a high level and the terminal on the node ND7 side is at a low level. Respectively. Similarly, in the latch circuits 30 and 40, the terminal on the node ND6 side is held at a high level, and the terminal on the node ND7 side is held at a low level. Hereinafter, this state of latch circuits 20, 30, and 40 is referred to as a state in which data "1" is latched (loaded). The opposite state, that is, a state in which the node ND6 is held at a low level and the node ND7 is held at a high level in these latch circuits is referred to as a state in which data "0" is latched.

Data "1" is latched by latch circuits 20, 30 and 40 by initialization. Signal VB
LA3H is set to the initial voltage V _RD1 and the node ND1
Is held by the latch circuit 10, the signal D
ATC and LATA are set to high level. here,
For example, if data "00" is stored in the selected memory cell, the threshold voltage is held at a high level, and the potential of the bit line BL is at the lowest level. Therefore, the signal VBLA3H is applied to the gate. The transistor N1 turns on, and the nodes ND3 and ND4 are kept at low level. In response, transistor P3 turns on, and node ND2 is held at substantially the same level as signal VBL3. Therefore, when the signal VBLP3 is held at a high level, the transistor N4 is turned on and the node ND0
Is held at a high level. Further, since the signal RD1 is held at a high level, the transistor N13 is turned on,
Node ND1 is held at the high level.

Next, the signals DATC and LATA are held at the high level, and the latch data of the latch circuit 20 becomes "1".
Therefore, the potential of the node ND1 does not change. Next, the signals RD2 and LAT0 and RD2 and LAT1 are each held at a high level. Thereby, the latch circuit 3
The latch data of 0 and 40 are both set to “0”. Then, the signals RD2 and LATA are held at the high level, and the latch data of the latch circuit 20 is also held at "0". This means that the reading has been completed.

Next, the signal VBL applied to the gate of the high withstand voltage transistor N1 is substantially similar to the operation described above.
A3H is set to a voltage V _RD2 higher than the previous V _RD1, and the latch data of the latch circuits 20, 30 and 40 are respectively set according to the potential of the bit line BL. in this case,
When “0” is set in the latch circuit 20 in the previous read operation and the read operation is completed, the node ND1 is held at the low level. Therefore, even if the RD2 and RD2C are set to the high level, the latch circuits 30 and 40 will be reset. Latch data does not change. The node 1 goes high only when the storage data of the selected memory cell is "01", and when the signals RD2C and LAT0 are held at high level, the latch circuit 30
Holds the data “1” set first in
When the signals RD2 and LAT1 are held at the high level, the data “0” is set in the latch circuit 40.

[0052] Finally, set to a higher voltage V _RD3 the signals applied VBLA3H to the gate of the transistor N1, a latch according to the potential of the bit line BL circuits 20 and 30
And 40 latch data are respectively set. In this case, when the storage data of the selected memory cell is “10”,
The node ND1 goes high, and the signals RD2 and LAT
When “0” is at a high level, data “0” is stored in the latch circuit 30.
Is set, and when the signals RD2C and LAT1 are at the high level, the data "1" initially set in the latch circuit 40 is held as it is.

If the node ND1 does not go high even when the signal VBLA3H is set to one of the voltages V _RD1 , V _RD2 and V _RD3 , the first set data “1” remains in the latch circuits 30 and 40. After completion of the reading, data "11" is read from these latch circuits.

As shown in FIG. 5, the signals BLDIS and TRN are set to voltages slightly higher than the ground potential GND during a period from when the potential of the source line SL is raised until the potential VBL of the bit line BL is stabilized. As a result, the transistors N2 and N12 shown in FIG. 1 are slightly turned on, and a small current flows through each of them. As a result, it is possible to prevent a bit line, which should have a low potential, from rising in voltage due to capacitive coupling with an adjacent bit line.

Operation after Loading Data FIG. 6 is a timing chart showing an operation performed after programming data is loaded into the latch circuits 30 and 40 and before programming. Hereinafter, the illustrated operation will be described with reference to FIG. 6 and the circuit diagrams of FIGS.

In loading data, input / output terminals IO,
A signal corresponding to the write data is input to / IO. After the levels of the input terminals IO and / IO are determined, one of the column signal line Y1 and the signals LAT0 and LAT1 is set to a high level. Thereby, the latch data of the latch circuit 30 or 40 is set. Then, after the data loading is completed, the operation shown in FIG. 6 is performed. As shown in FIG. 6, first, the signals LATSTC and LATA are set to a high level. In response, the transistor N37 shown in FIG. 2 is turned on, and the node ND7 is held at a low level, so that the latch circuit 20 holds data "1". The latch data “1” of the latch circuit 20
Means that writing is insufficient in programming performed after data loading.

After the latch data of the latch circuit 20 is set, the signals DATC and LAT0 and the signal DAT
C and LAT1 are each set to a high level. The latch data of the data latch circuits 30 and 40 are both "1".
At this time, in FIG. 1, the node ND7 is held at the low level, so that the transistor N7 is not turned on and the node ND1 is held at the high level. That is, the latch circuit 3
The node ND1 is held at a high level only when the latch data of 0 and 40 are both "1", that is, in the inhibit state. Otherwise, the node ND1 is held at a low level. Next, the signals RD2 and LATA are held at a high level. When the node ND1 is at the high level, the transistors N26 and N28 are both turned on in FIG. 2, and the latch data of the latch circuit 20 is set to "0". This means that writing is sufficient.

After data loading, usually, writing (Writ
e), but before that, if there is a memory cell that has not been deeply erased by performing verification, an erase operation is performed and all memory cells are completely erased,
That is, the control is performed so that the threshold voltages _Vth of all the memory cells are distributed in a range around the voltage _Vth3 as shown in FIG.

Write Operation FIG. 7 is a timing chart when a voltage is applied to the bit line at the time of writing in the nonvolatile semiconductor memory device of this embodiment. Hereinafter, the write operation of the multi-level memory of the present embodiment will be described with reference to FIG. 7 and the circuit diagrams of FIG. 1 and FIG. At the time of writing, the signal VBL1 shown in FIG. 1 is, for example, 1.8 V, the signal VBL2 is, for example, 3.8 V, the signal VBL3 is, for example, 4.5 V, and the signal VB is shown.
L3D is held, for example, at about the power supply voltage V _CC . Here, the power supply voltage V _CC is, for example, 3.3 V.

First, all bit lines are precharged to the level of signal VBL3. Then, when writing data "00" to the selected memory cell, the transistor N11 shown in FIG. 1 is turned on, and the transistors P2, P7 and N8 are turned off. Similarly, when writing data "01" to the selected memory cell, only transistor N8 is turned on, transistors P2, P7 and N11 are turned off, and when writing data "10", transistor P7 is written.
Is turned on, and the transistors P2, N6 and N11 are turned off. Then, when writing data "11" to the selected memory cell, only the transistor P2 is turned on, and the other transistors N11, N8 and P7 are turned off.

Hereinafter, the setting of the bit line potential in the writing will be described in more detail with reference to FIG.
First, since the signal BLDIS is held at the high level, the node ND0 is discharged to the level of the ground potential GND. Then, the signal DATRSTB is held at the low level. Accordingly, the transistor P shown in FIG.
20 turns on, and the node ND1 is maintained at a high level, for example, the level of the power supply voltage V _CC . When the signal VBLP3 is held at a high level, the transistor N4 turns on,
Since the node ND2 is held at the low level, the transistor P2 is turned on, and the node ND4 is held at the high-level potential set by the signal VBL3. When the signal VBLA3H is set to the high level, the transistor N1 is turned on, and the bit line BL is held at the high level, for example, at the potential set by the signal VBL3.

After the precharge of the bit line BL is completed, both the signals DATC and LATA are held at the high level as shown in FIG. At this time, when the latch data of the latch circuit 20 is "0", that is, in the prohibited state, the node ND7 is held at the high level, and the transistor N24,
Since both N25 are turned on, the node ND1 is held at the low level. In other cases, the node ND1 is kept at the high level.

Next, the signals DAT and LAT0 and the signal DA
T and LAT1 are each held at a high level. When both the latch data of the latch circuits 30 and 40 are “0”, the node ND1 is held at the high level. At other times, that is, the data “1” is stored in one or both of the latch circuits 30 and 40. When latched, the transistors N22 and N23 turn on, and the node ND1 is discharged to low level.

Then, the signals VBLP and VBLP0 are held at the high level, and the potential of the node ND1 is changed to the potential of the node ND5.
Is reflected in Further, the potential of the node ND5 is applied to the gate of the transistor N11 through the transistor N9. After the signal VBLP0 switches to low level,
The transistor N9 is turned off, and the gate potential of the transistor N11 is kept set by the gate capacitance. Next, in substantially the same manner as described above, the latch circuit 3
According to the latch data of 0 and 40, the gate potential of the transistor N8 is set and held. However, at this time, if the voltage applied to the gate of the transistor N8 decreases due to the signal VBLP1, the current hardly flows because the source potential is high. To prevent this, the signal V
When opening BLP1, a voltage slightly higher than the power supply voltage V _CC ,
For example, it is desirable to supply a voltage higher than the power supply voltage V _CC by the threshold voltage of the transistor N6.

Next, the gate voltage of the transistor P7 is set according to the latch data of the latch circuits 30 and 40. The voltage VBL2 is a voltage exceeding the power source voltage V _CC, the N-well in p-type substrate (PSub) can be set voltage independently, pMOS transistors P5, P6
And the signal VBL2 is applied using P7. Since turning off the transistor P7, it is necessary to apply a power supply voltage V _CC or more voltage to the gate, wherein the lift gate voltage by capacitive coupling using the standard transistor.
Hereinafter, this will be described. In FIG. 1, the gate potential of the transistor P7 does not fall below the signal VBLP2D. The signal VBLP2D is substantially (VBLP2-V
Is set to _CC), in the state of the signal VBLP2 is V _CC, by switching the signal VBLP from a low level to a high level, the output terminal is high level of the inverter INV2, for example, a low level from the level of the power supply voltage V _CC, for example , To the ground potential GND. VBL At the same time signal VBLP2D from (VBLP2-V _CC)
When lifted to P2, the gate voltage of transistor P7 rises due to capacitive coupling, and at the same time charges are confined in the gate. Thereafter, signal VBLP2 is lowered to ground potential GND.

[0066] The signal VBLP2D even when a voltage of the signal VBL2 on the bit line BL (VBLP2-V _CC)
To VBLP2 is the same, but since it has been pulled low through transistors N5 and P5, the gate of transistor P7 is (VBLP2
Most does not rise from -V _CC).

The circuit for applying the signal VBL3 to the bit line BL is used again by the circuit used at the time of reading. However, when the leakage current from the bit line BL is sufficiently small at the time of programming, the operation described below can be simplified. .

Before programming, the signals BLDIS and VBLP
3 are set to the high level, the node ND0 is discharged to the ground potential GND, and
Since the transistor N4 is turned on, the node ND2 is set to a low level on the order of the signal VBL3D. For this reason,
The pMOS transistor P2 whose gate is connected to the node ND2 turns on. Further, by setting the signal VBLA3H to a high level and turning on the transistor N1,
Bit line BL is raised to the level of signal VBL3. In this method, the bit line BL is supplied from the data latch circuit side.
Is precharged to the signal VBL3, but the source line S
By raising L, the bit line BL can be precharged.

If the leak current of the bit line BL is sufficiently small, the signal VBLA3H may be lowered to a low level and the transistor N1 may be turned off. When the leakage current of the bit line BL cannot be ignored, the bit line BL is set to the signal VBL.
In order to maintain the three levels, it is necessary to keep applying the voltage. In this case, for example, by holding the signal VBLA3H at a high level at a preset timing, the transistor N1 is turned on and a charge current is supplied to the bit line BL.

When the bit line BL is held at the ground potential GND, the signal VBL1 or the signal VBL2, any one of the signals VBLA0, VBLA1 and VBLA2B and the signal TRN are held at a high level, so that the node ND0 And a bit line BL is supplied with a charge current. At the same time, the potential of the node ND4 is also changed to the signal VBL3.
To the ground potential GND or one of the signals VBL1 and VBL2, so that the transistor P3 is turned on. Therefore, the node ND2 is raised to the level of the signal VBL3, and the transistor P2 is turned off. As described above, the ground potential GND, the signals VBL1, VB
The potential of either L2 or VBL3 is applied, so that voltage fluctuation due to leak current can be prevented.

The bit line potential setting circuit shown in FIG. 1 is a standard transistor except for the high voltage transistors N1 and N2. In this circuit, since the gate voltage and the source-drain voltage of the transistor are all divided, the transistors N1 and N1
Since the voltage applied to each transistor except for the transistor No. 2 is equal to or lower than the power supply voltage V _CC , the transistor can be prevented from being destroyed by a high voltage. The withstand voltage in other places, for example, in a pn junction composed of a well and a drain portion, is the power supply voltage V
_What is necessary is just to make it about 2 to 3 times of _CC .

The bit line potential setting circuit shown in FIG.
Four levels of voltages can be set on the bit lines. Further, when the number of levels increases, the number of stages may be increased, and even if the number of stages remains at four, no problem can be solved. In this case, the optimum number of stages may be determined based on the disturbance characteristics of the memory cells.

FIG. 8 is a waveform diagram showing changes in voltage levels of bit lines and word lines in the case of local self-boosting in this embodiment. Here, in the memory cell of one page shown in FIG. 3, the bit line voltage and the word line voltage when programming is performed on the memory cell MCn as a selected memory cell will be described with reference to FIG. In FIG. 8, V _pgm is the selected word line WL.
n, V _pass1 and V
_pass2 is a pass voltage applied to another word line, VBL
1, VBL2 and VBL3 are voltages applied to the bit lines. As shown in the figure, at the time of writing, a voltage (V _pass1 + α) slightly higher than the pass voltage V _pass1 is applied to the selection transistor on the bit line side, that is, the gate of the transistor NTB shown in FIG. 3 (signal DSG). ).

As shown, in the memory cell located on the source line SL side of the selected memory cell MCn, the channel may be cut off, so that the word line WLn-1 is connected to the ground potential GND.
Is held. On the drain side, the memory cell receives the signal VB
It is necessary to pass L2, the word line WLn + 1 is held at slightly higher voltage [Delta] V _P from the ground potential GND. This voltage ΔV _P largely depends on how much the threshold voltage V _th of the memory cell is reduced at the time of erasing.

It is necessary to boost the channel so that the word line WLn + 1 is turned off from the word lines WLn + 2 to WLN.
It is necessary to increase the word line voltage of the word line WLn + 2 and the like.

In the erase operation, the signal TR shown in FIG.
Since N and VBLA3H are held at ground potential GND, the data latch circuit shown in FIG. 2 is electrically disconnected from bit line BL even if bit line BL is set to a high voltage. Are not broken by the high voltage of the bit line BL.

FIG. 9 is a waveform diagram showing signal waveforms at the time of write verification in this embodiment. Hereinafter, the write verify will be described with reference to FIG. 9 and the circuit diagrams of FIG. 1 and FIG.

Verify is an operation performed after writing, and is an operation for verifying whether or not the threshold voltage of a selected memory cell is set to a desired level according to write data. At the time of verification in the present embodiment, the determination as to whether the bit line potential VBL is at the high level or the low level is the same as that at the time of reading, but the fact that the verify voltage applied to the word line WL is variable indicates that the reading is performed. It is different from the time.

As shown in FIG. 9, first, the signal VBLA3H
At the lowest level V _VR1 , the signal DATC and the signal L
ATA is set to high level. At this time, if the selected memory cell has already been sufficiently written, the node ND1 becomes low level and does not change thereafter. Since the signals DAT and LAT0 and the signals DAT and LAT1 are sequentially set to the high level, the node ND1 goes to the low level except when the selected memory cell writes data "00". Next, the signals RD2 and LATA are set to a high level, and if writing is sufficient, data "0" is set in the latch circuit 20.

The same determination as described above is made based on the signal VBLA3H
Is repeated at the levels V _VR2 and V _VR3 . In all cases, when the latch data of the latch circuit 20 is set to “0”, it is determined that the writing has been sufficiently performed, and the writing in the page is performed. Has ended.

In the above-described write verify, unlike other multi-valued memory devices, the data loaded in the latch circuit is held without being destroyed in the verify operation. There is no need to load the write data into the latch circuit every time read verification is performed.
It is possible to easily realize that the read verify is repeated a required number of times. Therefore, during programming, the threshold voltage _Vth distribution can be gradually narrowed by gradually decreasing the increase ΔV _pgm of the program voltage applied to the selected memory cell at the time of writing. Becomes

In the NAND flash memory, the threshold voltage V _th of all memory cells is set to a low level due to erasure before writing, for example, a negative voltage V _th3 lower than the ground potential GND as shown in FIG. Since the data is controlled so as to be distributed within the center range, the threshold voltage of the memory cell is raised to the higher side when writing is performed, and therefore, the increase in the program voltage V _pgm applied to the word line WL is increased. While ΔV _pgm is large, it is necessary to end the distribution of the threshold voltage in a slightly lower state. Therefore, at the time of verification, the program voltage V _pgm applied to the word line may be started from a low level as shown in FIG. As a result, the determination is made in a state close to the time of reading at the final stage of the verification, so that AGL is performed.
(ArrayGround Line) and other problems can be reduced.

FIG. 10 shows an improved ISP in this embodiment.
The schematic diagram of P (Incremental Step Pulse Programming) is shown. FIG. 10A shows a level change of the program voltage V _pgm at the time of writing. FIG. 7B shows the word line voltage at the time of verification.

As shown in FIG. 11A, in order to speed up the writing, the word line WL is used in the first writing.
The increase ΔV _pgm of the level of the voltage applied to is set _relatively large. Thereafter, the increase Δ in the program voltage V _pgm
Since V _pgm is gradually set smaller, the increase width of the threshold voltage is narrowed, and the threshold voltage can be controlled with high accuracy. As shown in FIG. 2B, the word line voltage at the time of verification is set to a low level first, and then set to be gradually higher. At the final stage of the verification, the state is almost the same as that of the normal reading, so that it is possible to reduce various problems such as AGL as described above.

FIG. 11 shows how the threshold voltage _Vth of the memory cell changes to the level set by the write data by the above-described programming. Note that in FIG. 11, and
Of the write operation shown in FIG. That is, at the initial stage of programming, the word line voltage at the time of verification is set to be the lowest. In the middle stage of programming, and in the last stage of programming, the word line voltage at the time of verification is set to be the highest, and a voltage slightly higher than that at the time of normal reading is applied to the word line. As a result of programming, the threshold voltage _Vth of each memory cell is set to a level according to data to be stored in the memory cell. Further, the threshold voltage V _th of each memory cell is controlled to be distributed within a narrow range except for the lowest distribution range corresponding to the erased state as shown in FIG.

[0086]

As described above, according to the nonvolatile semiconductor memory device of the present invention, it is not necessary to change the word line voltage at the time of reading in the multi-valued memory, and the word line and the bit line having a large time constant need not be changed. The number of times of changing the potential need only be once. Instead, it is possible to detect the bit line potential by changing the gate potential of the high breakdown voltage transistor in the bit line potential setting circuit in a stepwise manner, thereby realizing high-speed reading. In addition, it is possible to apply a high voltage equal to or higher than the power supply voltage to the bit line at the time of writing, and there is an advantage that reduction of write disturbance can be realized.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing one embodiment of a nonvolatile semiconductor memory device according to the present invention, and is a circuit diagram showing a configuration of a bit line potential setting circuit.

FIG. 2 is a circuit diagram showing a configuration of a data latch circuit of the nonvolatile semiconductor memory device of the present invention.

FIG. 3 is a circuit diagram illustrating a configuration of a NAND nonvolatile memory according to the present invention.

FIG. 4 is a distribution diagram showing a distribution of threshold voltages of quaternary memory cells;

FIG. 5 is a timing chart showing a read operation of the multilevel memory of the present invention.

FIG. 6 is a timing chart showing an operation after data loading of the multi-valued memory of the present invention and before programming.

FIG. 7 is a timing chart showing a write operation of the multilevel memory of the present invention.

FIG. 8 is a timing chart showing changes in word line and bit line voltages during local self-boost in the multi-valued memory of the present invention.

FIG. 9 is a timing chart showing write verification of the multilevel memory of the present invention.

FIG. 10 is a timing chart showing a word line voltage at the time of writing and verifying in the multilevel memory of the present invention.

FIG. 11 is a distribution diagram showing a change in threshold voltage of a memory cell at the time of programming in a multi-valued memory of the present invention.

[Explanation of symbols]

10, 20, 30, 40 ... latch circuit, 12, 14 ... inverter, MC0, MC1, ..., MCn, MCn + 1,
..., MCN ... memory cells, INV1, INV2, ..., I
NV8: Inverter, NAND1: NAND gate, V
_CC : power supply voltage, GND: ground potential.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 29/788 H01L 27/10 434 29/792 29/78 371 F-term (Reference) 5B025 AA01 AB01 AC03 AD04 AD05 AD05 AE05 5F001 AA01 AB02 AD41 AD44 AD53 AE02 AE03 AE08 AE30 AF06 AF20 AG40 5F083 EP02 EP22 EP76 GA01 GA30 LA10 PR42 PR52 ZA08 ZA21

Claims (12)

[Claims] A threshold voltage is controlled in accordance with the amount of charge stored in a charge storage layer insulated from the surroundings, a control terminal is connected to a word line, and input / output terminals are connected to a source line and a source line, respectively. A non-volatile semiconductor storage device including a storage element connected to a bit line, wherein at the time of reading, the source line is held at a predetermined source line voltage, and a predetermined word line voltage is applied to the word line.
Read bias means for setting the bit line to a level corresponding to a threshold voltage of the storage element; a read node; and a read node connected between the bit line and the read node;
A data propagation transistor for propagating data corresponding to the bit line voltage to the read node in accordance with an input level of a read signal; and a plurality of levels sequentially changing to a control terminal of the data propagation transistor when reading. Applying a read signal, detecting a level change of the read node,
A non-volatile semiconductor memory device having read means for determining data read to the bit line. 2. The nonvolatile semiconductor memory device according to claim 1, wherein said data transmission transistor is constituted by a high breakdown voltage transistor. 3. The read bias means includes source line voltage applying means for applying the source line voltage to the source line, and word line voltage applying means for applying the word line voltage to the word line. 2. The nonvolatile semiconductor memory device according to 1. 4. The nonvolatile semiconductor memory device according to claim 1, further comprising a level holding circuit for holding a voltage level of said read node at the time of reading. 5. A threshold voltage is controlled in accordance with the amount of charge stored in a charge storage layer insulated from the surroundings, a control terminal is connected to a word line, and input / output terminals are connected to a source line and a source line, respectively. A non-volatile semiconductor storage device including a storage element connected to a bit line, wherein at the time of reading, the source line is held at a predetermined source line voltage, and a predetermined word line voltage is applied to the word line.
Read bias means for setting the bit line to a level corresponding to a threshold voltage of the storage element; a read node; and a read node connected between the bit line and the read node;
A data propagation transistor for propagating data corresponding to the bit line voltage to the read node according to an input level of a read signal; and a read potential for amplifying a potential of the read node at the time of reading and holding the amplified potential. A holding circuit, a first node set to a first level according to the potential held by the read potential holding circuit, and a second level set to a second level according to the potential held by the read potential holding circuit And an inverter having an input terminal and an output terminal connected to each other, and one of the connection points of the input / output terminals is connected to the first node.
A first data latch circuit connected to the first node through a gate of the first data latch, and a connection point of the other input / output terminal connected to the second node through a second gate; A terminal and an output terminal are connected to each other, and two inverters are connected to each other.
Is connected to the first node through a gate of the storage element, and the connection point of the other input / output terminal is connected to the second node through a fourth gate. And a plurality of second data latch circuits provided in response to the read voltage and the read voltage holding circuit holding the voltage of the read node in the verify after read and write. 1
And a latch data setting circuit for setting latch data of the second data latch circuit, respectively. 6. The nonvolatile semiconductor memory device according to claim 5, wherein said data transmission transistor is constituted by a high breakdown voltage transistor. 7. The read bias means includes source line voltage applying means for applying the source line voltage to the source line, and word line voltage applying means for applying the word line voltage to the word line. 6. The nonvolatile semiconductor memory device according to 5. 8. The nonvolatile semiconductor memory according to claim 5, further comprising an erasing means for erasing data stored in said memory element before writing, and controlling said threshold voltage to be distributed within a predetermined range. apparatus. 9. The nonvolatile semiconductor memory device according to claim 5, further comprising a data load means for setting an initial value in said first and second data latch circuits before reading. 10. The nonvolatile semiconductor memory according to claim 9, wherein said data load means sets said initial value in said second data latch circuit in accordance with a threshold voltage of said erased storage element. apparatus. 11. The non-volatile semiconductor memory device according to claim 5, further comprising control means for terminating the read operation when the latch data of the first data latch circuit changes during the read operation. 12. The nonvolatile semiconductor memory device according to claim 5, further comprising a write voltage setting means for supplying a voltage higher than a power supply voltage to said bit line at the time of writing.