JP2000147566A - Electro-optical display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the yield by providing a drive circuit which drives at least either a first thin film transistor on a second thin film transistor. SOLUTION: The gate G1 of the first transistor Tr1 is connected to a selection line VG, and the drain D1 is connected to a signal line VD. In such a case, the source of the first transistor Tr1 is connected to the gate electrode of the second transistor Tr2. Then, the drain of the second transistor Tr2 is connected to a voltage supply line VLC, and the source is connected to a pixel electrode. At the time of driving, a signal VG is inputted to the selection line, and a pure digital signal VD is inputted to the signal line. On the other hand, the signal VLC where in a positive and a negative voltage signals appear alternately is inputted to the voltage supply line. At this time, the voltage V1 of the source side of the first transistor Tr1 increases as shown by a solid line, and then, the voltage V1 drops, and thereafter attenuates. On the other hand, the second transistor Tr2 becomes on-state, and then the pixel electrode is charged.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electro-optical display device in which pixels are arranged in a matrix, such as a liquid crystal display, and more particularly to an active-matrix type electro-optical display device. The present invention relates to a new pixel and a display device, and a manufacturing method and a driving method thereof, for solving the problem of image quality deterioration caused by variations in the image quality and problems inherent in the device.

[0002]

2. Description of the Related Art In recent years, a thin film transistor type liquid crystal display (TFT LCD), which has become widespread, has characteristics that it has better saturation and contrast, a wider viewing angle, and is easier to see than the previous simple matrix type liquid crystal display. In recent years, with the colorization of liquid crystal displays, they have been produced with particular emphasis in recent years.

The circuit of a pixel cell of a conventional TFTLCD is as follows.
In the structure as shown in FIG. 2A, a thin film transistor (TFT) is provided at an intersection of wirings extending vertically and horizontally, the gate electrode is used as a selection line (also referred to as a gate line), and the drain region is used as a signal line (drain). And the source region was connected to the pixel electrode. The structure itself was the same as that already employed in DRAMs, and it was thought that its reliability was fully recognized. There were some analog parts in the operation, and in fact, there were various problems.

The signals input to the selection line and the signal line are shown in FIG.
(B), the respective V _G, indicated by V _D. If a direct current is applied to the liquid crystal for a long time, the characteristics will be degraded by electrolysis, so periodically (usually every frame)
The voltage signal applied to the signal line is inverted so that the voltage applied to the liquid crystal is inverted.

FIG. 1 also shows a change in the voltage (V _LC ) of the pixel electrode when such a signal is applied. From this, the problem associated with the conventional active system can be read.

[0006] First, a voltage pulse is applied to the selected line, so have a voltage applied to simultaneously signal line, the transistor is turned ON, the voltage of the pixel electrode begins to rise (in the t ₁ region). However, its operation is generally slow. In particular, a TFT using amorphous silicon has a low mobility, and in some cases, a pulse of a selection line may be cut off before reaching a required voltage. In the case of the polysilicon TFT, the situation is improved, but even in a high-speed operation in which the pulse width is less than 1 μsec, the state cannot be followed. In normal operation, one frame is 30 msec.
In a display having 480 selection lines (480-line display), the pulse width is about 50 μsec. However, in order to obtain a higher definition or higher gradation image, it is necessary to increase the frame frequency.
Therefore, in the case of a product having a higher added value, the condition that the pulse width is 1 μsec or less is required as described above.

Next, at the same time when the pulse of the selection line is cut off, the voltage of the pixel electrode drops by ΔV as shown in the figure.
This is caused by the parasitic capacitance caused by the overlap between the gate electrode and the source region, and is called “dive voltage”. This effect is more remarkable as the parasitic capacitance is larger. Therefore, in a pixel using an amorphous TFT having a large parasitic capacitance, as shown in FIG. 2A, a capacitor is purposely inserted in parallel with the pixel to reduce the jump voltage effect. However, providing such a capacitor causes an increase in the load on the TFTs and peripheral circuits, and the wiring of the capacitor reduces the aperture ratio, resulting in a dark screen.

[0008] In a polysilicon TFT, such a problem is not remarkable. This is because a self-alignment process can be employed in the fabrication. But still,
In the current technology, ΔV of about 1 V exists, and in the future, if higher image quality is required, it will be a big problem.

[0009] Next, since the cut pulse selection line until the next pulse (region of t ₂₎ depending on the voltage of the pixel electrode discharge, gradually decreases. The main cause of this discharge is T
The discharge is from the FT. Then, a pulse is again applied to the selection line. At this time, since the voltage of the signal line is inverted, the voltage of the pixel electrode is also inverted. And
As described above, the voltage of the pixel electrode changes gradually.

Further, when the pulse of the selection line is cut off, the minus voltage increases by ΔV. And
Thereafter, it gradually approaches zero due to discharge. As described above, the voltage of the pixel electrode is asymmetric, and thus causes problems such as flicker and deterioration of liquid crystal.

Further, it should be noted that such a complicated change in voltage may vary greatly depending on individual pixels. For example, the rise of the voltage at t ₁ may include the mobility of the TFT, the channel width, the channel length, the thickness of the active region, the magnitude of the gate voltage (voltage of the selection line) and the magnitude of the drain voltage (voltage of the signal line). Affected by factors. The mobility of a TFT greatly depends on the manufacturing process,
It is unlikely that the same panel will be significantly different, but it is conceivable that future large-screen liquid crystal displays will have much greater location dependence. The thickness of the active region will also become a major problem as the screen size increases. The channel width and the channel length usually have a deviation of about 10% due to an error in the mask process. The gate voltage decays as the selection line extends, with a difference of more than 10% near and farthest from the driver. The same applies to the drain voltage.

The jump voltage depends on the parasitic capacitance of the TFT. This is due to a 20% error in a non-self-aligned process and a 10% difference in a self-aligned process in the current process. In addition, since the jump voltage is proportional to the gate voltage, the fact that the gate voltage differs depending on the location of the panel as described above means that the jump voltage has a synergistic effect of the parasitic capacitance error and the gate voltage error. Is brought.

On the other hand, the decrease in pixel voltage due to discharge is caused by TF
It largely depends on the channel length and channel width of T and the characteristics of the active region. As a result, the pixel voltage is
It varies widely, from the solid line to the dotted line. Strict quality control is required to fabricate the device so that the voltage difference as described above falls within the intended range, but as a result, the product yield is significantly reduced. With low value-added products that may have low performance like the current, even if the yield is profitable, to produce high value-added products required in the future at the current product level, It is impossible to make a profit.

At present, in the TFTLCD, the gradation display is performed by controlling the voltage of the signal line to an appropriate level.
It seems that the gradation display is impossible even at 16 gradations. The threshold voltage of a normal TN liquid crystal is about 5 V,
If this is divided into 16 equal parts, the result is 300 mV. Considering the rise of the voltage and its variation, the magnitude and the variation of the dive voltage, and the variation of the discharge, an error of about 300 mV occurs unless the aperture is narrowed down sufficiently. It is a mess.

From such a viewpoint, the present inventors have proposed a digital gray scale display method instead of the conventional analog gray scale display. In this method, gradation is displayed by controlling the time for applying a voltage to the liquid crystal. For example, Japanese Patent Application Nos. 3-169305 and 3-169.
306, Japanese Patent Application No. 3-169307, Japanese Patent Application No. 3-2098
69, etc. However, for that purpose, a high-speed operation that is 20 to 300 times faster than the current driving speed is required. To do so, the NMOS T
It is no longer possible to drive only with FT.
It was necessary to convert to OS. However, even if such a method is adopted, it is difficult at present to prevent gradation disturbance due to variations in the characteristics of each TFT.

For example, even if an intermediate display is to be performed by setting the voltage state to 45% of one frame, 110% of the target voltage is applied to a certain pixel, and to another pixel. If only 90% of the voltage is applied, then 1.1 × 45% = 49.5 in the former case
% And the latter, 0.9 × 45% = 40.5%, the brightness of which differs by 20% or more, and in fact, the eight gradations are the best.

In order to solve this problem, for example, as described in Japanese Patent Application No. 3-209870 of the present inventors, the characteristics of each pixel are previously input to an external storage device. There is a method in which an image signal is subjected to arithmetic processing by this data and sent to the pixel. However, this method involves a complicated arithmetic processing of the data, and therefore, the load on the peripheral drive circuit is large, and the individual pixels have to be processed. The time required to inspect and enter the correction data is enormous (1
If it takes 1 second to inspect and input a pixel, 640 × 48
0 panel takes 85 hours), which contributes to cost increase.

[0018]

SUMMARY OF THE INVENTION The present invention has been made in order to compensate for the above-mentioned drawbacks of the current TFT LCDs or the digital gradation type LCDs having improved TFT LCDs. First, the present invention proposes a structure in which the characteristics of the LCD panel are not directly affected by each TFT. The fact that the characteristics of the individual TFTs are not directly reflected in the image quality means that the allowable range of the variation of the TFTs is widened, so that the yield can be increased and the cost of the product can be reduced. In addition, the present invention proposes a structure particularly suitable for a digital gray scale driving method, and refers to the driving method. In addition, the present invention proposes a structure suitable for obtaining high added value by other high-speed operations, including the above-mentioned digital gradation method. Then, a process suitable for manufacturing the above-described structure will be described.

[0019]

The idea of the present invention is that a constant voltage should be supplied whenever the pixel electrode is in a voltage state. Therefore, it is avoided to apply a voltage that decreases due to the discharge with time as in the related art. For that purpose, a driving circuit as shown in FIG.

[0020] The circuit has two transistors, the first transistor Tr ₁ gate (G ₁₎ to the select line V _G, the drain (D ₁₎ is connected to the signal line V _D. This state is the same as the conventional TFT LCD,
In the present invention, the source of Tr ₁ is changed to the second transistor Tr.
Connect to the _second gate electrode. The drain of the Tr ₂ is connected to the voltage supply line V _LC. The source of the Tr ₂ is connected to a pixel electrode. As described above, the feature of the present invention is that the mechanism of indirectly transmitting the signal of the signal line to the pixel electrode is employed, and the signal of the signal line is directly connected to the pixel as in the related art. In this case, the operation time is extremely limited, but the time is provided by connecting indirectly to the pixel.

That is, the signal on the signal line itself is
Since it is not applied to the elementary electrodes, Tr₁Signal passing through
Even if it fluctuates more than what was specified,
Tr _TwoIf it is within the range suitable for controlling the pixel electrode
Always take a constant value.

That is, as described above, the width of the signal pulse on the selection line is extremely short, usually 70 μsec. In a special case where digital gradation is performed, one tenth to several hundredths thereof is used. There is only one width. In such a short time, the voltage held in the pixel electrode often becomes largely different due to variations in the characteristics of each TFT.

On the other hand, analyzing the operation of the present invention,
Since the width of the voltage pulse applied to r ₁ is also such a very short time, its source voltage will also differ greatly, but the voltage will not be applied to the pixel electrode, second TFT, because it is being applied to the gate electrode of Tr _2, to some extent, TF
Even if there is variation for each T, it is sufficient that the voltage of the source of the TFT having the worst characteristic is sufficient to control Tr ₂ .

If the conditions can be set in such a manner, T
By controlling the ON / OFF of r _2, capable of supplying a constant voltage from the voltage supply line V _LC in the pixel electrode. That is, the magnitude of the voltage applied to the pixel electrode does not involve the signal of the signal line. Signal line signal is ON or OFF
It just tells you.

Further, the Tr_TwoOperation itself is Tr₁Compared to
It should be noted that everything can be slow enough. You
That is, Tr₁After the ON / OFF operation of
Tr _TwoCan also work. That
Is Tr₁By Tr_TwoCharges close to the gate electrode
And then again Tr₁At the signal
Tr for a long enough time to be sent_TwoWill react
I just need. Therefore, for example, a digital floor of about 32 gradations
When adjusting the tone, Tr_TwoThe Amorpha
Use slow-moving devices such as silicon TFTs.
Both are possible.

Further, in the configuration of FIG. 1A, the load on Tr ₁ is significantly reduced as compared with the conventional TFT. In the conventional method, all electric charges sent to the pixel electrode have to pass through the TFT. Moreover, at most 70 μs
c had to be passed in a short time. However,
In the present invention, the charge passing through Tr ₁ is charge corresponding to the capacitance between the gate and drain of Tr ₂ . For example, the size of the pixel is 300 μm × 300 μm and the thickness is 6 μm.
μm, and the size of the gate electrode of Tr ₂ is 10 μm.
Assuming that m × 10 μm and the thickness of the gate insulating film is 0.2 μm, the capacitance of the former is actually 30 times that of the latter,
Further, the size of the gate electrode is made smaller, for example, 5 μm.
If it is × 5 μm, it will be as much as 120 times.

Obviously, the conventional method imposes an excessive load on the TFT. On the other hand, in the present invention,
Burden tr ₁ 1 30 to 120 minutes in a conventional TFT, or it requires below. This makes it possible to the speed of the Tr ₁ 30 to 120 times, or more as compared with the conventional method. For example, as long as a conventional method is adopted, it is impossible to perform digital gradation with an amorphous silicon TFT. This is because the mobility of amorphous silicon is extremely small, so that a high-speed operation involving large charge transfer as in the related art cannot be performed.

However, in the present invention, this is not a problem at all because the amount of charge is much smaller than in the prior art. Therefore, the amorphous silicon TFT can be driven at a speed about 100 times that of the related art, and 64 or more digital gradations can be performed. Since the fabrication temperature of the amorphous silicon TFT is lower than that of the polysilicon TFT, the productivity is excellent and the production cost is suppressed.

On the other hand, the operation speed of Tr ₂ is not less than 1/100 of that of Tr ₁ , preferably 2/100.
It is sufficient if the value is 1/0 or more. In this case, Tr ₂
Is the same as in the prior art, but the speed may be low. For example, when performing 32 digital gray scales, an amorphous silicon TFT may be used for Tr ₂ . In that case, the switching speed of Tr ₂ becomes
70 μs, same as conventional amorphous silicon TFT
Assuming that c, the minimum period of the digital gradation is 1/32 of 33 msec, that is, about 1 msec. However, since the operation speed of Tr ₂ is only 7% thereof, it operates without any problem.
Of course, it is needless to say that a polysilicon TFT can secure a sufficient capacity.

Further, in order to provide a margin for the operation of the Tr ₂ for more high grayscale display may be increased and the channel width of the Tr _2, but in that case, a load of the Tr ₁ T
Gate of r ₂ - it is necessary to note that the drain capacity increases. For example, when the channel width is increased by a factor of 5, the driving capability of Tr ₂ is increased by a factor of 5, but the load on Tr ₁ is also increased by a factor of 5.
The operation speed of Tr ₁ becomes 20%.

An example of the driving method shown in FIG. 1A will be described with reference to FIG. First, a signal is sent to the selection line and the signal line as in the conventional case. However, the signal input to the signal line is a pure digital signal. On the other hand, a signal that alternates between positive and negative is sent to the voltage supply line. This signal is repeated at the same cycle as the selection line. In this example, the signal on the voltage supply line is set to 0 while a pulse is applied to the selection line. Select lines, signal lines, V _G in each diagram the signal voltage supply line, V _D, shown in V _LC.

At this time, a change in voltage at each point of the circuit is examined. The voltages at points V ₁ and V ₂ in FIG.
V ₁ and V ₂ of FIG. First, the voltage V on the source side of Tr _{1
In the case of 1} , the voltage rises as shown by the solid line due to the signals on the selection line and the signal line, and there is a slight voltage drop due to the jump voltage due to the cutoff of the pulse on the selection line, and thereafter, the voltage attenuates due to discharge.

On the other hand, the voltage on the source side of Tr ₂ , that is, the voltage on the pixel electrode, turns on Tr ₂ because V ₁ is in a voltage state. Next, since a voltage is applied to the voltage supply line, the pixel electrode is charged by the voltage. Here, it must be noted that since Tr ₂ is already in the ON state, its charging is substantially determined by the ON resistance of Tr ₂ and the capacitance of the pixel electrode, and the rise is extremely fast. It is.

In the present invention, normally, a signal is sent to the voltage supply line after a certain period of time has passed after the pulse on the selection line has expired. Of course a voltage may be applied to the pulse expires at the same time the voltage supply line but in particular by using a slow TFT operation speed to Tr _2, digital (particularly the invention human invention such as Japanese Patent Application No. 3 163870, 3-1
63871, 3-163872, 3-168733
This is not a sensible method when a high gradation display is to be performed by the method described in (1).

For example, consider the case of displaying 64 digital gradations. The pulse repetition cycle of the selection line is at least 500 μsec. The width of the selection pulse is 480
In the row matrix, the time is 1 μsec. However, as described above, the load on Tr ₁ is small, so that it can be driven sufficiently. Further, even if the voltage on the source side of Tr ₁ does not rise sufficiently, there is no problem as long as a voltage sufficient to drive Tr ₂ is supplied. Therefore, until Tr ₁ it does not cause any problems. In other words, when the pulse on the selection line is cut off ( ₁ μsec after the pulse on the selection line is sent), the source side of Tr ₁ is in a sufficiently high voltage state.

The driving capability of Tr ₂ is the lowest.
Assume that it takes 70 μsec to turn on. However, a TFT having better characteristics may be present in a panel. TFT corresponding to Tr ₂ of a certain pixel
May be turned on in 60 μsec. Such a difference is caused by a superposition of a difference in mobility caused by a subtle difference in the film quality of the activation layer, and a difference in channel width and channel length due to a subtle difference in the photomask.

If such various characteristics of the TFT
On the panel equipped with
Or during the duration of the selection pulse
Line V _LCIf a voltage is applied to a certain pixel,
After μsec, charging is completed, and charging is completed at a certain pixel
It takes 70 μsec to complete. The difference is 10μ
sec, seems to be small enough,
This is 2% of the minimum repetition period of 500 μsec.

In order to achieve 64 gradations, the pulse duration for each pixel must be kept within 1.6%, but when such a large difference of 2% occurs, in fact, the 64th gradation is required. Displaying the key is no longer meaningful. Of course, T
It can be dealt with by adjusting the characteristics of the FT, but it is not the intention of the present invention that the yield is reduced as a result.

On the other hand, 80 μm after the pulse of the selection line is cut off.
In the case where a voltage is applied to the voltage supply line after sec or 100 μsec, since all the Trs ₂ are already in the ON state, all the pixels are brought into the voltage state at almost the same time without any problem. Regarding the time required for charging at this time,
The parameters related to the pixel are the pixel capacity and the O ₂ of Tr ₂ .
N resistance. Since the ON resistance is about 10 ⁶ Ω and the capacitance of the pixel electrode is about 10 ⁻¹³ F, this time constant is 100 n
sec.

Therefore, no matter how much the time constant varies for each pixel, if the variation is within 50% of the time constant, the difference is 100 nsec, which is extremely small compared to the repetition period of 500 μsec (0.02 sec).
%), And satisfies the above-mentioned condition of 64 gradations (variation: within 1.6%). Therefore, such a method of supplying the voltage to the voltage supply line after a certain delay is advantageous for high gradation display.

The same consideration must be taken when turning off the voltage on the voltage supply line. In this process, it is desired to release the voltage of the voltage supply line before the pulse is applied to the selection line. By doing so, the electric charge held in the pixel can be reliably discharged.

For example, even when a selection pulse is applied,
If the voltage is still applied, Tr ₁Was not selected
(That is, when no signal comes to the signal line)
Has Tr_TwoThe charge on the gate electrode of the
Dynamically Tr_TwoIs in the OFF state, and eventually
As a result, charge is left in the pixel.

In order to avoid such a situation, it is desirable that the voltage of the voltage supply line is set to 0 and all the charges of the pixel are discharged before the pulse comes to the selection line. That is,
There is a time τ between when the voltage of the voltage supply line is set to 0 and when the selection pulse is applied. However, since the time required for this charge release is about the same as the time constant described above, it is not necessary to be so nervous.

In the second cycle, the voltage of the voltage supply line is made negative, and an alternating current is performed. Again, a negative voltage is supplied to the voltage supply line after a certain time has elapsed after the selection pulse has expired. According to the conventional method, the polarity of the signal on the signal line is inverted to perform the AC conversion.
It is not necessary to invert the polarity of the signal on the signal line as shown in FIG.

Further, as is apparent from the figure, the voltage fluctuation due to the jump voltage as in the prior art is limited to V ₁ , and the voltage applied to the pixel has no such fluctuation.
Also, there is no attenuation due to spontaneous discharge. This is because in the conventional method, the voltage applied to the pixel is static electricity held by the pixel electrode, whereas in the present invention, the voltage applied to the pixel is always supplied from a constant voltage supply line. It is because it was done. This difference is exactly the feature of the present invention.

For the purpose of considering the variation of the element, T
The case where the characteristic of r ₁ is not good is shown by a dotted line in the figure. That is, since the characteristics of the element are not good, the source voltage of Tr ₁ has a poor rise and does not reach the voltage of the drain, and the parasitic capacitance is large and the influence of the jump voltage is large.
Further, it shows that the spontaneous discharge is large. When such a TFT and a TFT having a characteristic shown by a solid line are mounted on the same panel, the conventional method cannot be used due to severe color unevenness, but the present invention does not cause any problem.

That is, even if the TFT has the characteristic shown by the dotted line, the final source voltage (when the voltage of the voltage supply line becomes 0) controls Tr _2. This is because there is no effect on the pixel electrode if it is sufficient.

As shown in the figure, even when V ₁ is indicated by a dotted line, V ₂ has almost no effect.
Conventionally, the fact that how to reduce variations in the voltage of the V ₁ is was the biggest problem. As a result, the yield did not increase, and the production cost was high. According to the present invention, a panel that has been regarded as defective in the past can be sufficiently used.

For example, even if the panel includes many TFTs having the characteristics shown by the dotted line at V ₁ in FIG. 1B, for example, the voltage is the threshold voltage of Tr ₂ . As described above, the voltages of the selection line and the signal line may be set high. As a matter of course, the voltage should not be set too high to destroy a good TFT.

In fact, in our prototype, 10 lines
In a small panel of 10 rows (100 elements)
If the height of the lus is 15V and the voltage of the signal line is 10V
Come, V ₁Is 90% or more of TFTs with 5V or more
It was very easy to do. Yield in this process
Was 95% or more. In this case, TF
Increase the gate voltage and drain voltage of T by 5V
And 5 V or more could be achieved in 99% of TFTs. I
Some TFTs can be destroyed by such operations
Was.

However, if the conventional method was adopted, even such a panel would not even display black and white. That is, in the above panel, V
₁ is 60% in the range of ± 0.9V with an average value of 7.2V
There was only. In that case, a TFT of 40% is not suitable for displaying only eight gradations. If 90% or more of the TFTs have V ₁ =
If the panels were selected to fall within the range of (7.2 ± 0.9) V, the yield was significantly reduced. Of course, this prototype was under poor conditions, so it is possible to increase the yield by optimizing the conditions, but it takes a lot of effort to produce a larger display. .

In the present invention, at least two TFs are assigned to one pixel.
Since the T must be formed, there is a concern that the yield will be reduced accordingly. However, the characteristics required for the TFT are lower than those of the conventional method as described above because the standard is loose. It rarely leads to a reduction in yield.

In the case of FIG. 1, a selection line and a voltage supply line are provided for each column. For this reason, the number of wirings is doubled as compared with the conventional method, and the aperture ratio of the pixel may be reduced. Actually, even in the existing liquid crystal display device, the wiring is formed in parallel with the selection line, and this is used as the additional capacitance wiring. In particular, an amorphous silicon TFT which has a problem with the parasitic capacitance in the TFT is used. It is not a disadvantage that the wiring density increases and the aperture ratio decreases as compared with the conventional technology, but when the terminal connection is taken into account, it is certainly twice as large. Density is required. To solve this problem, a method as shown in FIG. 3 can be adopted.

FIG. 3A shows a structure in which the voltage supply lines of two adjacent pixel columns are shared. With this structure, the wiring density can be reduced by 25% as compared with the method of FIG.
% And the mounting density can be suppressed to 1.5 times the mounting density of the conventional ideal active matrix method. Similarly,
It is possible to provide one voltage supply line for every three adjacent pixel columns, or to share one voltage supply line for many more columns. Although it is possible for all the pixel columns to share the voltage supply line, in that case, the pixel needs to have a special structure and special driving.

The driving example of FIG. 3A will be described with reference to FIG. V _G, V _G 'is the signal above and below the selected line, respectively, V _D is a signal of the signal line, V _LC represents the signal of the voltage supply line, also, the solid lines in V _1, V _2, FIG. 3
The broken line of the voltages at points V ₁ and V ₂ (upper pixels) in (A) indicates the voltage at the points V ₁ ′ and V ₂ ′ (lower pixels). The signal on the selection line and the signal on the signal line are the same as those in the conventional or FIG. However, unlike the case of FIG. 1, the signal of the voltage supply line is not in the voltage state while the pulses of the upper and lower two signal lines continue. That is, it is necessary to move the electric charges of the upper and lower two pixels.

First, a pulse is sent to the upper selection line. This
At the time, since a signal is coming to the signal line, the T
FT (Tr₁) Is turned on and V₁Is a voltage state
You. Therefore, the second TFT (Tr_Two)Also
It is turned on. Next, a pulse is sent to the lower selection line.
However, at that time, since the signal line is not in the voltage state,
V ₁'Is not in a voltage state. Therefore, the lower pixel
TFT (Tr₁’) Remains OFF,
In addition, the second TFT (Tr_Two’) Is also OFF
Keep.

On the other hand, after the pulses on both selection lines are interrupted,
A signal is sent to a common voltage supply line. As a result, a voltage is supplied to the pixel electrodes of the upper through Tr ₂ is in the ON state, the pixel becomes a constant voltage state. On the other hand, in the lower pixel, T
Since r ₂ ′ is in the OFF state, the pixel electrode is not in the voltage state.

In this manner, after one cycle has elapsed, a pulse is again sent to the selection line of this pixel. Immediately before or at the same time, the pulse of the voltage supply line is cut off.
Flowing through r ₂ , the upper pixel is no longer in a voltage state.

Now, the upper pixel is not selected from the pulse of the selection line and the signal of the signal line, but the lower pixel is selected. Therefore, Tr ₁ is still in the OFF state, also, Tr ₂ also maintain the OFF state. On the other hand, Tr ₁ ′
Is in the ON state, and Tr ₂ ′ is maintained in the ON state. Thereafter, a voltage is applied to the voltage supply line, and a voltage is applied to the lower pixel electrode via Tr ₂ ′ in the ON state. No voltage is applied to the upper pixel electrode.

In FIG. 3, V₁And V₁’Voltage comparison
Therefore, two TFTs, Tr₁And Tr ₁’Transistor
It is shown that the characteristics are significantly different. Tr₁Is
The rise of the pressure is good, the drop of the dive voltage is small,
The spontaneous discharge is also small and shows extremely excellent characteristics. On the other hand, T
r₁'Have poor properties across all of these.
Normally, TFTs having such greatly different characteristics are provided with the same data.
When formed on the display, the unevenness is severe and
It could not be used for displays that require precise movement
It is.

However, in the present invention, for example, Tr ₁ ′
Even if the characteristics of the other were inferior to others, for one cycle,
If it is equal to or higher than the threshold voltage of the second TFT Tr ₂ ′,
Desirably, if the voltage is higher than the voltage applied to the voltage supply line, a constant voltage can be supplied to the pixel electrode, and therefore, there is no problem such as unevenness. That is, a panel (TFT), which was conventionally determined to be defective, can be used. For that purpose, the voltage of the signal line and the voltage of the selection line may be adjusted so that the TFT with the worst characteristics satisfies the above conditions. In this way, a panel that has been previously determined to be defective can be used, resulting in an improvement in yield and a reduction in manufacturing cost.

Referring to FIG. 4, an example in which the present invention can sufficiently use a TFT having a poor characteristic which has been considered to be extremely unusable in the past will be described. FIG.
In (A) is is shown a circuit for use in the present invention, (designated .C ₃ which functions as a capacitor.) Required TFT and pixel It is known that the parasitic capacitance of the TFT is present in addition to Therefore, such a parasitic capacitance often causes a problem in a liquid crystal display.

A typical problem is the jump voltage already described many times. This is because the parasitic capacitance C ₁ between the TFT gate and the source of the capacitance of the pixel electrodes in the circuit of a capacitor (the conventional source side, in the present invention the second TFT,
Gate and drain capacitance) and the gate wiring tr ₂ are capacitively coupled, is intended to vary the voltage. The voltage width Δ
V is represented by ΔV = C ₁ V _G / (C ₁ + C ₂ ) in the example of FIG. In the present invention, the size of C ₂ is determined by the size of the gate electrode of Tr ₂ , the thickness of the gate insulating film, and the dielectric constant. In particular, in the present invention, the first TFT, Tr ₁
It is advantageous to set this capacity to a small value in order to reduce the driving load of the device. For example, 1% of the capacity of the pixel
It may be as follows. By using such a small load, it is possible to operate at a speed 100 times higher than the conventional one.

However, in such a case, Tr
_In some cases, the parasitic capacitance of ₁ cannot be ignored. Typically, the magnitudes of C ₁ and C ₂ may be equal. In the conventional TFT, since C ₁ was about one order of magnitude smaller than the pixel capacitance even when any, there was a variation in the voltage problem, so much was not that the ratio is increased. For example, when C ₁ and C ₂ are the same, so that the half of the voltage of the voltage applied to the gate electrode varies. FIG. 4B shows an example thereof.

In the figure, an N-channel type TF
Voltage V _G applied to the gate electrodes of T and Tr ₁ (solid line)
And a voltage V _D (broken line) applied to the signal line (drain wiring). Further, a change in the voltage on the source side is shown below. For example, V _G is 30V and V _D is 20
Let's say V. While a voltage is applied to the gate electrode,
The voltage increases and eventually becomes constant at 20V. However, at the same time the gate voltage is 0, the above jump voltage effect, half the voltage of the voltage V _G is lost,
Descend. That is, a voltage drop of 15 V occurs, and as a result, only a voltage of 5 V remains.

This is not fatal to the present invention. Because the TFT with the worst characteristics
If a voltage of about 5 V remains even after the
Since the voltage is equal to or higher than the threshold voltage of r _2, a voltage can be supplied to the pixel. Of course, T
Due to the FT, the voltage drop is small, and a voltage of 10 V or more may be applied to the gate electrode of Tr _2. However, any TFT applies the voltage equally applied to the voltage supply line to the pixel. Therefore, there is no problem such as uneven color. In the conventional method, if the characteristics of the TFTs are different, this directly leads to the deterioration of the image quality. If the voltage is increased to match the TFT with the worst characteristic, an excessive voltage may be applied to the liquid crystal in the pixel having the TFT with the best characteristic. In the present invention, there is no such concern. This is because the highest voltage is applied to the gate electrode of the Tr _{2 based on} the worst TFT, but the withstand voltage is several times to ten and several times higher than that of the liquid crystal material.

In the present invention, such a view that such a voltage drop is not particularly problematic has been introduced. However, this is a serious problem from another viewpoint. That is, the idea is that the power consumption increases because pulses of extremely high voltage are exchanged. If a voltage as high as 30 V leaks, it may seriously damage other drive circuits and devices, and may also damage human bodies. Therefore,
FIG. 4C shows a method for solving this problem.

In FIG. 4C, a positive voltage is applied to the gate electrode and a negative voltage is applied to the drain. In this case, the potential difference between the gate electrode and the drain electrode becomes 10
Because of V, the same TFT driving capability as in the case of FIG. 4B is expected. For example, the V _G 5V, a V _D -
Let's say 5V.

Next, looking at the change in the voltage on the source side, while the voltage is being applied to the gate electrode, the voltage initially increases negatively and eventually becomes equal to the drain voltage. Then, when the voltage of the gate electrode becomes 0, the negative voltage of the source voltage increases conversely due to the effect of the parasitic capacitance. Its magnitude is 2.5 V, which is half of the gate voltage, and eventually the voltage on the source side is -7.5 V. if,
If Tr ₂ is a P-channel transistor or a depletion transistor driven by a negative voltage, the voltage of the selection line and the signal line can be used as a single voltage of 5 V, extremely low power consumption, and safety. Is also resolved.

It should be noted that in this case, even if the voltage of the signal line is 0, a voltage of -2.5 V is applied to the source due to a change in the gate voltage. A normal amorphous silicon TFT may cause little problem at such a voltage, but if the threshold voltage of Tr ₂ is small due to the polysilicon TFT, it will be turned on. Therefore, even if it is intended to have no signal, a signal state may occur. To avoid such problems, a negative voltage to the signal state, the non-signal state positive voltage Tr ₁
May be applied to the drain. In that case, the signal state is as shown in FIG. 4C, but in the non-signal state, the voltage on the source side is +2.5 V and Tr
_{If 2} is a P-channel type or a depression type, there is no reaction.

In the present invention, unlike the conventional method, the electric charge stored in the capacitor of the pixel cannot be directly removed by the pulse of the selection line. Therefore, as described above, a method of discharging by setting the voltage of the voltage supply line to 0 when Tr ₂ is in the ON state is used. Although a method of this degree is sufficient, a more aggressive discharge can be achieved by connecting the pixel electrode to a third electrode controlled by a selection line as shown in FIG.
TFT ₃ and Tr ₃ may be provided. In this case, Tr
₃ discharges the charge stored in the pixel electrode while the pulse is applied to the selection line. However, in this case, the pixel voltage may undergo unexpected fluctuations due to the jump voltage due to the parasitic capacitance of Tr ₃ . However, there is no problem if the parasitic capacitance is sufficiently smaller than the capacitance of the pixel electrode.

Further, as shown in FIG. 5B, a structure in which a natural discharge is promoted by a resistor in parallel with the pixel may be adopted. At this time, the value of the resistor R may be set so that, for example, the time constant with the pixel is about one frame.
Specifically, 33ms if used in normal mode
ec, when performing digital gradation, 500 μs for 64 gradations, for example, so as to attenuate faster.
In the case of c, 256 gradations, if the image is designed to be attenuated in about 125 μsec, a clear image can be obtained without any afterimage or blurring of the image.

In the case where display is performed in a state where charges are stored in the pixel electrodes as in the related art, it is difficult to provide a circuit in which the voltage (charge) attenuates in such a short time. It was difficult to implement because it provided qualification. That is, even if such a resistor is provided, it is inevitable that the resistance value will vary by about 20%, so that the voltage attenuates at a different speed during one frame, and after one frame is completed. The voltage magnitudes differed by about 20%.

However, in the present invention, since the voltage of the pixel electrode is the voltage of the voltage supply line, it is constant for most of the time, so that the display variation due to the difference in the resistance value may not be a problem.

In FIG. 5B, the resistor is provided in parallel with the pixel electrode. However, if such a wiring is formed, an additional wiring must be formed, so that the aperture ratio is reduced. Must.

As described in the description related to FIG. 4, in the present invention, a combination of NMOS and PMOS (CMOS) and a combination of enhancement type and depletion type are used.
Efficient operation can be performed.

FIG. 6 shows a combination of the enhancement type and the depletion type. That is, using an enhancement type TFT as Tr ₁ ,
A depression type TFT is used as Tr ₂ . The operation at this time is shown in the figure below.

[0078] Here, in the voltage representation of the signal line V _D,
A positive signal is ON, and a negative signal is OFF. Initially, the voltage of the signal line when the pulse of the selection line is applied to transmit ON information to the pixel is positive. At this time,
Voltage V ₁ was becomes positive, greatly reduced by the effect of jump voltage. For example, the selection pulse is 10 V, and the voltage of the signal line is ± 8 V. Further, the magnitude of the jump voltage is set to half of the selection pulse. That is, it is 5V. Therefore, V ₁ is 3V. If charging is not sufficient during the duration of the selection pulse, it will be less.

Since Tr ₂ is an NMOS depletion type, if V ₁ is positive, it is ON. After this,
Although a positive voltage is applied to the voltage supply line, the pixel electrode is immediately positively charged because Tr ₂ is in the ON state. Before the next selection pulse comes, the voltage of the voltage supply line becomes 0, and the voltage of the pixel electrode immediately becomes 0. In the future, it is assumed that a negative voltage is applied to the signal line as indicated by the solid line. Then, V ₁ shows a negative value. Then, the effect of the jump voltage is added, and a voltage of -13 V is applied. Then Tr
₂ is in the OFF state. Therefore, even if a negative voltage is supplied to the voltage supply line, the pixel is not charged.

[0080] If, as shown by a dotted line, V ₁ is once continued signal line to a positive voltage is applied, as indicated by the dotted line, since a positive signal in the same way as the first cycle is shown, Tr ₂ is O
Therefore, the pixel electrode is immediately charged by the negative voltage supplied to the voltage supply line.

FIG. 7 shows the case of CMOS. Here, Tr ₁ is an NMOS and Tr ₂ is a PMOS, but this may be reversed. The lower part of FIG. 7 shows an example of the operation. Here, the voltage display signal lines V _D, positive signals are OFF, the negative signal is turned ON. At first, in order to transmit OFF information to the pixel, the voltage of the signal line when the pulse of the selection line is applied as shown by the solid line is positive. At this time, the voltage of V ₁ was becomes positive, greatly reduced by the effect of jump voltage. For example, the selection pulse is 10 V, and the voltage of the signal line is ± 8 V. Further, the magnitude of the jump voltage is set to half of the selection pulse. That is, it is 5V. Therefore, V ₁ is 3V. If charging is not sufficient during the duration of the selection pulse, it will be less.

Since Tr ₂ is a PMOS, if V ₁ is positive, it is in the OFF state. Thereafter, a positive voltage is applied to the voltage supply line, but since Tr ₂ is in the OFF state,
The pixel electrode is not charged. Before the next selection pulse comes, the voltage of the voltage supply line becomes zero. In the future, it is assumed that a negative voltage is applied to the signal line as indicated by the solid line. Then
V ₁ was a negative value. Then, the effect of the jump voltage is added, and a voltage of -13 V is applied. Then Tr ₂ is O
The state becomes the N state. Therefore, a negative voltage is supplied to the voltage supply line, and the pixel electrode is immediately charged by this voltage.

If the pixel is to be turned on over these two periods, a voltage may be applied to the signal line as indicated by the dotted line. That, V ₁ are each as indicated by the dotted line, becomes a negative signal, Tr ₂ continues the ON state. Accordingly, the pixel electrode is charged by the voltage supplied to the voltage supply line at first to be positive and secondly to be negative.

An example of a signal when digital gradation is performed using the present invention will be described with reference to FIG. As a circuit,
As shown in FIG. 7, a CMOS type using NMOS for Tr ₁ and PMOS for Tr ₂ is employed. The example in FIG.
In the case of two-gradation display, higher gradation display can of course be performed. For details, refer to Japanese Patent Application No. 3-209869 of the present inventors.

There are several types of digital gray scales. The most suitable method for reducing the load on the driving device is to realize the time during which the voltage is applied to the liquid crystal pixels by the sum of a plurality of pulses. In the example of FIG. 8, the shortest pulse width applied to the liquid crystal pixels is 33 msec.
1/32 of c and about 1 msec. This is expressed as T ₀ in FIG. Of course, that time may be slightly reduced. For example, as described above, as the operation of the Tr ₂ which is a feature of the present invention is carried out uniformly, when a time delay applied voltage to the pixel is shorter than the time of course Become. For example, 70 to 90% of 1 msec may be used.

However, the minimum repetition period of the pulse of the selection line is about 1/32 of one frame period (for example, 33 msec), and it is not desirable that the period be extremely small or large.

In FIG. 8, after the pulse is first applied to the selection line, the pulse is applied again T ₀ seconds later. Thereafter, the interval between pulses applied to the selection line is 16T ₀ , 2T
₀ , 8T ₀ , 4T ₀ and one frame ends.
The pulse width of the selection line is determined in consideration of the number of rows of the LCD matrix. Here, assuming that the number of lines is 480, 1
The minimum time allowed per row is 2 μsec, but it is 1 μsec to avoid pulse overlap.
This is 30 to 70 μs of the conventional ordinary analog display method.
Fast enough compared to ec. However, although such high-speed operation is required, there is no problem if the load is significantly smaller than that of the conventional method. This is also a feature of the present invention. The pulse height of the selection line was 10 V.

On the other hand, a positive or negative signal is input to the signal line. When a positive signal is input, the voltage supplied to the pixel is set to 0, and when the signal is negative, the pixel is set to a voltage state. The voltage of the signal applied to the signal line was ± 8V.

The Tr ₁ has such a characteristic that the fluctuation of the jump voltage (voltage drop) is attenuated to 25% of the gate voltage, and the voltage after the time T ₀ is attenuated to 90% (50% after the lapse of the time 16T ₀ ). What had it was used. This characteristic is rather bad and cannot be used in a conventional TFT LCD. However, as will be described below, the present invention is sufficiently usable.

[0090] As shown in V ₁ of the in Figure 8, the source side voltage of the Tr ₁ is during the first T ₀ and the next 16T ₀ is a positive voltage, during the subsequent 2T ₀ and 8T ₀ Indicates a negative voltage. Then, during the last 4T ₀ , the voltage becomes positive again.

On the other hand, a pulse signal synchronized with the selection line is sent to the voltage supply line. The timing is set so that its duration is proportional to the interval between the selection pulses, for example, 10 μsec after the end of the selection pulse between the first selection pulse and the next selection pulse, and the next selection pulse starts. The processing may be completed 10 μsec before the start, and may be started 160 μsec after the end of the second selection pulse, and may be ended 160 μsc before the start of the third selection pulse. In this way, the duration of each pulse is represented by a clean integer ratio.

However, even if such a troublesome operation is not performed, it is also possible to simply start a certain time after the end of the selection pulse and end it a certain time before the start of the next selection pulse. There is virtually no problem.

For example, after the end of the selection pulse, 10 μs
If the pulse on the voltage supply line is started after c, and the pulse on the voltage supply line is ended after 10 μsec before the start of the next selection pulse, the duration of the pulse on the first voltage supply line is: 0.98 msec, the duration of the next pulse is 15.8 msec, and the ratio is:
1: 16.12, which is different from the ideal ratio of 1:16, but the difference is 12% of the minimum pulse width, and there is almost no problem in 16-gradation display. Therefore, here, the latter method is adopted as shown in FIG.

It is needless to say that alternating display can be performed by inverting the sign of the pulse of the voltage supply line for each frame. It is desirable that the potential of the counter electrode is always kept at the ground level. The pixel electrode voltage is determined by V ₁ and V _LC , and the first two periods, T ₀ and 16
At T ₀ , V ₁ is positive, so the voltage V ₂ of the pixel is 0, but during the subsequent 2T ₀ and 8T ₀ , V ₂ is in a voltage state because V ₁ is negative. However, the last 4T ₀
Then, V ₂ becomes 0 again.

After all, since the voltage state was only 10T ₀ (10 μsec) during this 31T ₀ (31 μsec), the display of the eleventh stage of the 32 stages (the display of the first stage has no voltage state at all) State). As described above, according to the present invention, digital gradation can be accurately performed.

In the present invention, the number of columns of the matrix is the same as the conventional one, but the number of rows is larger by the number of the voltage supply lines. Further, in connection with the driver circuit, it is almost impossible to perform the connection uniformly as in the conventional mounting using TAB, and therefore, a special mounting method must be used. TFT is self-aligned polysilicon TF
When T is used, a peripheral circuit such as a driver can be formed at the same time when a driving circuit of a pixel is formed, so that there is no need to worry about a decrease in yield due to connection of each wiring.

However, the amorphous silicon TF
If a T or polysilicon TFT other than the self-aligned type is used, a driver IC must be separately connected to each terminal. Alternatively, even in the case of a self-aligned polysilicon TFT, a high-speed driver is required to perform a high gradation display such as 256 gradations.
But it can't work. Therefore, an external driver IC is required.

In such a case, for example, as shown in FIG. 9, the driver IC 904 connected to the selection line is placed on the left side of the panel 901 and the driver IC 904 connected to the voltage supply line.
905 may be mounted on the right side of the panel, and only the terminals of the selection lines may be exposed on the left side, and only the terminals of the voltage supply lines may be exposed on the right side.

In FIG. 9, the matrix 902 is divided into upper and lower parts, and driver ICs 03 connected to signal lines are connected to the upper and lower parts of the panel, respectively, as is often done in the prior art. In this way, there are apparently two independent panels.
This means that the number of selection lines and voltage supply lines of each panel can be reduced by half. This makes it possible to increase the width of the selection pulse, which is particularly effective when performing high gradation display.

If the present invention is not carried out, a known TFT
A fabrication technique may be used. The details will be described in the following embodiments.

[0101]

Embodiment 1 FIGS. 10 and 11 show a method of fabricating two TFTs for one pixel in advance and connecting each electrode with a metal wiring. FIG. 10 is a cross-sectional view of the manufacturing process, and FIG. 11 is a top view (a plan view) of the manufacturing process. The TFT to be manufactured in advance is
Both may be the same type of TFT,
And NMOS TFTs, and different types of TFTs, such as depletion type and enhancement type TFTs.
It may be. In the figure, a planar type TFT is shown, but a staggered type or an inverted staggered type may be used.
An impurity region (source, drain) may be formed by using a self-aligned method or a non-self-aligned method.

When analog gray scale or digital gray scale is performed by a conventional method, it is desirable to adopt a self-aligned method because parasitic capacitance of the TFT becomes a problem. Since the self-alignment method cannot be adopted, the parasitic capacitance has been reduced by making full use of an extremely fine mask alignment technique.However, in the present invention, even if the parasitic capacitance is appropriately present, it is rather determined by the parasitic capacitance. In some cases, effective operation can be expected. As described above, this can be a feature of the present invention. Of course, it is needless to say that a smaller parasitic capacitance is desirable because the load on the peripheral circuit is smaller.

FIG. 1 shows a state in which such a TFT is manufactured.
0 (A) and FIG. 11 (A). Here, already 2
One TFT, 107 and 108, is shown. Here, 101 is a substrate such as glass, and 102
Is a blocking layer for preventing mobile ions such as sodium from entering the TFT from the substrate, and silicon nitride, aluminum oxide or the like is suitable.

Reference numeral 103 denotes an insulating film made of silicon oxide or the like provided for the purpose of preventing formation of such an interface state between the blocking layer and the semiconductor of the TFT. Reference numeral 104 denotes a semiconductor film. In the figure, since a planar method is employed, an impurity region is formed here. The thickness of the coating was preferably from 20 to 100 nm. When the self-alignment method is adopted, it is desired that this film is finally made of polysilicon. Reference numeral 105 denotes an insulating film functioning as a gate insulating film, and a silicon oxide film formed by a sputtering method or a silicon oxide film formed by an ECR-CVD method is suitable for the purpose. The thickness is 50-200n
m was preferred. Reference numeral 106 denotes a gate electrode. When a self-alignment method is used for introducing impurities, a semiconductor material such as silicon doped with a high concentration of impurities or a heat-resistant metal such as chromium or tungsten is suitable for the purpose. At the stage of FIGS. 10A and 11A, these gate electrodes are exposed.

Next, as shown in FIGS. 10B and 11B, holes are formed in the source region and the drain region of the TFT 107, a metal film is formed, and etching is performed. Connect to At the same time, the source region is connected to the other TFT by the metal wiring 109.
108 is connected to the gate electrode. At this time, the TFT 10
Since the gate electrode of No. 8 is exposed, the step of drilling is unnecessary.

Thereafter, an interlayer insulating film 111 is formed, and as shown in FIGS. 10C and 11C, the TFT 1
A hole is formed in the gate electrode 07 and the drain region of the TFT 108, a metal film is formed, and the gate electrode of the TFT 108 is connected to the signal line 113, and the drain region of the TFT 108 is connected to the voltage supply line 112. An interlayer insulating film having good insulating properties is suitable for implementing the present invention. This is because, in the present invention, it is desired that the gate electrode of the TFT functioning as Tr ₂ holds electric charge for one frame. It is not necessary that there be no charge leakage, but too much leakage is a significant obstacle to practicing the present invention.

Finally, after forming the surface flattening film 114, as shown in FIGS. 10 (D) and 11 (D),
A hole is formed in the source region of the FT 108, and the pixel electrode and its wiring 115 are formed of a transparent conductive material such as ITO (indium oxide-tin oxide alloy). Through the above steps, a pixel capable of implementing the present invention could be manufactured.

Embodiment 2 FIG. 12 shows this embodiment.
FIG. 12 is a cross-sectional view illustrating an example in which the present invention is implemented using two inverted staggered TFTs.

As shown in FIG. 12A, the glass substrate 2
01, inverted stagger type TFTs 209 and 210 are formed. Here, reference numeral 202 denotes a blocking layer for preventing invasion of mobile ions from the substrate, and silicon nitride or the like is suitable. A gate electrode 203 is formed of a metal such as aluminum or a semiconductor material such as silicon. In particular, when the yield is improved by a low-temperature process, aluminum having low conductivity can be selected. When aluminum is used, it is desirable that, of the gate electrodes, the gate electrode of the TFT 209 is already formed so as to be connected to the selection line at the time of patterning. On the other hand, TFT
The gate electrode 210 is in an electrically insulated state.
Further, it was convenient to form an oxide film having a thickness of 10 to 30 nm on the surface of the gate electrode by an anodic oxidation method or another method.

Reference numeral 204 denotes a gate insulating film. It is preferable to use a gate insulating film which also functions as an interlayer insulating film. Regarding the activation region of the TFT, the TFT 209 is formed by forming the I-type amorphous silicon film 205 on the TFT 2.
In No. 10, an N-type amorphous silicon film 206 was formed. Polysilicon may be used instead of amorphous silicon. Then, an N ⁺ -type microcrystalline silicon film 207 is provided on both TFTs with the etching stopper 20.
8 was used as a source and a drain. With such a configuration, the TFT 209 operates as an enhancement type TFT, and the TFT 210 operates as a depression type TFT.

If a circuit as shown in FIG. 7 is to be formed by implementing CMOS, the active regions (ie, 205 and 206) are both I-type, and the source and drain are P-type and N-type. What should I do? In the case of CMOS, if amorphous silicon is used, P-channel TF
Polysilicon is preferred because the mobility of T is significantly smaller. However, as in the case of the depletion type, it is difficult to produce polysilicon at a low temperature unless a special method such as laser annealing is used. For example,
When aluminum is used for the gate electrode, care must be taken because if the process temperature is 550 ° C. or more, the aluminum is deteriorated.

At the stage shown in FIG. 12A, the gate electrode of the TFT 210 has no electrical connection with the outside due to the interlayer insulating film 204. Next, FIG.
As shown in (B), the drain of the TFT 209 is connected to the signal line 211 by forming and patterning a metal film, while a hole is formed in the gate electrode of the TFT 210 to form a metal wiring 212. , The source of the TFT 209 and the gate of the TFT 210 are connected.

Further, after forming the interlayer insulating film 213,
A hole is formed in the drain of the TFT 210, and a metal wiring 214 connected to the voltage supply line is formed as shown in FIG. Finally, after forming the flattening film 216, the pixel electrode 217 is formed with a transparent conductive material.
(D)), the fabrication of the pixel embodying the present invention ends.

Embodiment 3 FIG. 13 shows the present embodiment.
FIG. 13 also illustrates an example in which the present invention is implemented using two inverted staggered TFTs. FIG. 13 is a top view. FIG.
As shown in (A), a metal wiring 301 functioning as a selection line and also functioning as a gate electrode of a first TFT and a metal wiring 301 'functioning as a gate electrode of a second TFT are formed on a glass substrate. It is formed by patterning the same film. Before patterning, it was convenient to form an oxide film having a thickness of 10 to 30 nm on the surface of the metal film by an anodic oxidation method or another method.

Further, after forming a gate insulating film also functioning as an interlayer insulating film, a semiconductor film 302 was formed.
Further, a contact hole 304 is formed in a gate electrode of the second TFT, and a high-concentration impurity-doped semiconductor film 305 serving as a source / drain electrode of the first TFT,
A high-concentration impurity-doped semiconductor film 303 was formed as source and drain electrodes of the TFT. At this time, these two semiconductor films 303 and 305 may be of the same material, the same film, the same conductivity type, or different conductivity types.
If different conductivity types are used, CMOS conversion is possible.

The first T of the semiconductor film 305
The portion functioning as the source of the FT is connected to the gate electrode of the second TFT via the contact hole 304.
Thus, FIG. 13A is obtained. Next, FIG.
As shown in FIG. 7, a metal film is formed and patterned, so that the drain of the first TFT is connected to the signal line 306.
Connect to Further, after forming an interlayer insulating film, FIG.
As shown in (C), a contact hole 307 is opened in the drain of the second TFT and a contact hole 309 is opened in the source of the second TFT, and the second TFT is connected to the voltage supply line 308 and the pixel electrode 310, respectively. Thus, the fabrication of the pixel embodying the present invention is completed.

The following is a summary of the case where the above steps are implemented in a CMOS circuit. The number in [] is the number of cells. (1) Formation of selection line 301 and gate electrode 301 '[1] (2) Formation of gate insulating film (interlayer insulating film) (3) Formation of semiconductor layer 302 [2] (4) Etching stopper (not shown) [3] (5) Formation of contact hole 304 [4] (6) Formation of semiconductor layer 305 [5] (7) Formation of semiconductor layer 303 [6] (8) Formation of signal line 306 [7] ( 9) Formation of interlayer insulating film (10) Formation of contact holes 307 and 309 [8] (11) Formation of voltage supply line 308

[9] (12) Formation of Pixel Electrode 310 [10] That is, it can be manufactured through ten mask steps.

Embodiment 4 FIG. 14 shows an example of an actual circuit for implementing the present invention. FIG. 14A shows a cross-sectional view thereof, and FIG. 14B shows a top view thereof. This circuit is manufactured as follows.

First, a wiring 402 serving as a gate electrode of a first TFT and also functioning as a selection line is formed on a substrate 401. After forming the wiring, an oxide film having a thickness of about 10 to 200 nm may be formed on the surface of the wiring by an anodic oxidation method or the like. Further, the side surface of the gate electrode or the selection line may be tapered as shown in the figure. By adopting such a tapered cross section, the step can be reduced, the adhesion of the film laminated thereon can be increased, and the fine processing can be performed with good reproducibility.

In particular, when the gate electrode also serves as the selection line as in this example, in order to reduce the resistance of the selection line, it is necessary to increase its width or increase its thickness. And in order to shorten the channel length,
Increasing the width of the selection line is problematic. Therefore,
It is required to increase the thickness of the selection line,
If the thickness of the selection line is too large, the film formed thereon will be hindered by the step. From such a meaning, such a tapered cross section is preferable.

On the selection line (gate electrode of the first TFT) 402, a gate insulating film 403 is formed.
The gate insulating film also functions as an interlayer insulating film, and it is desirable that the surface thereof be planarized by an etch-back method after or during the formation.

Then, on such a flat gate insulating film, a film 405 of amorphous silicon or polysilicon or an intermediate state thereof is formed as an active semiconductor film of the first TFT. Its thickness is 20 ~
It is set to 100 nm. Further, a film such as silicon nitride is formed thereon and patterned, and this is used as an etching stopper 406. In particular, when etching a multi-layer coating of the same material, if the lower layer coating is extremely thin as described above, there is a risk that the lower layer coating may be cut accidentally, so it is not possible to provide such an etching stopper. It makes sense. The channel length of the TFT is substantially determined by the width of the etching stopper.

Next, for example, an N ⁺ -type microcrystal silicon film is formed and patterned to serve as the drain 408 of the first TFT, the source of the first TFT, and the gate electrode of the second TFT. The formed wiring 407 is formed. According to the present invention, the operation characteristics are greatly affected by the electric charge accumulated in the wiring 407. Therefore, if the capacitance of the wiring in this portion is large, the first
The load on the TFT (Tr ₁ ) increases. Therefore,
From the viewpoint of high-speed operation, it is desirable to arrange such that the surface area is as small as possible in this way. Forming as an integral body as in this embodiment further emphasizes the advantages of the present invention. Become.

From this state, the signal line 409 is formed of a metal material such as aluminum. Since the drain of the first TFT is exposed, a sufficient contact can be obtained simply by forming a metal wiring thereon.

Next, an insulating film 410 which functions as a gate insulating film of the second TFT and further functions as an interlayer insulator is formed. The material is preferably silicon oxide or the like. Then, a film 411 of polysilicon or an intermediate state between amorphous silicon and polysilicon is formed thereon as the activation semiconductor film 411. Its thickness is 20 to 100 nm. Further, a film of silicon nitride or the like is formed thereon and patterned, and this is used as an etching stopper 412.

Then, for example, a P ⁺ type microcrystalline silicon film is formed, and this is patterned,
A source and a drain 413 of the second TFT are formed. In this state, since the source region and the drain region are exposed, the voltage supply line 414 is placed on the drain.
Is formed of a metal material such as aluminum, and a good contact can be obtained only by forming the pixel electrode 415 with a film of a transparent conductive material such as ITO on the source.

The above steps are summarized as follows. Here, the number in [] is the number of masks. (1) Formation of selection line 402 [1] (2) Formation of gate insulating film (interlayer insulating film) 403 (3) Formation of semiconductor layer 405 [2] (4) Formation of etching stopper 406 [3] (5) Formation of semiconductor layers 407 and 408 [4] (6) Formation of signal line 409 [5] (7) Formation of gate insulating film (interlayer insulating film) 410 (8) Formation of semiconductor layer 411 [6] (9) Etching Formation of stopper 412 [7] (10) Formation of semiconductor layer 413 [8] (11) Formation of voltage supply line 414

[9] (12) Formation of pixel electrode 415 [10]

That is, it can be manufactured through ten mask steps. A feature of the above method is that a circuit can be manufactured without forming a contact hole even once. Connection of wiring by contact holes is often
Disconnection and poor contact were caused by the hole steps. In this embodiment, such a problem does not occur.

[0129]

According to the present invention, the yield can be significantly increased as compared with the conventional analog gray scale or digital gray scale method. In other words, even if a bad TFT element that is regarded as defective in the conventional method is used,
For the reasons described above, a sufficient gradation display could be obtained. As a result, it is a feature of the present invention that the yield is improved and the production cost is reduced. However, it is also a feature of the present invention that the same gray scale display as that of the related art or a more excellent gray scale display can be achieved at low cost.

When the present invention is applied, if a polysilicon TFT manufactured by a self-alignment method is used for the two TFTs, an LC which is extremely excellent in high-speed operation and high gradation display can be obtained.
D can be prepared.

Further, even when a non-self-aligned polysilicon TFT is used for the two TFTs, gradation display of 64 gradations or more can be performed without difficulty, and the production cost is reduced to the 16th floor of the conventional analog system. It can be produced at a cost that is equivalent to, or much lower than, that of a traditional LCD.

Further, even when a non-self-aligned amorphous silicon TFT is used as the two TFTs, a large area LCD having a gradation display capability of 16 gradations or more can be obtained.
Can be manufactured at low cost.

As described above, the present invention suffers from amortization of upfront investment due to low yield and high cost that cannot be seen.
Becoming a savior in the liquid crystal display industry in a muddy state where profitability was uncertain due to the loss of deficit, pioneering new fields of use that could not be imagined with conventional expensive liquid crystal displays, LCD displays exceeding the conventional economic forecast The inventor believes that this will trigger a market.

[Brief description of the drawings]

FIG. 1 shows a circuit example of a pixel of a TFTLCD of the present invention and an operation example thereof.

FIG. 2 shows a circuit example of a pixel of a conventional TFTLCD and an operation example thereof.

FIG. 3 shows a circuit example of a pixel of a TFTLCD of the present invention and an operation example thereof.

FIG. 4 shows a circuit example of a pixel of a TFTLCD of the present invention and an operation example thereof.

FIG. 5 shows an example of a circuit of a pixel of the TFTLCD of the present invention.

FIG. 6 shows a circuit example of a pixel of the TFTLCD of the present invention and an operation example thereof.

FIG. 7 shows a circuit example of a pixel of a TFTLCD of the present invention and an operation example thereof.

FIG. 8 shows an example of a signal waveform when performing digital gradation using the present invention.

FIG. 9 shows a mounting example of a TFTLCD having the present invention.

FIG. 10 shows an example of a method for manufacturing a circuit of the present invention.

FIG. 11 shows an example of a method for manufacturing a circuit of the present invention.

FIG. 12 shows an example of a method for manufacturing a circuit of the present invention.

FIG. 13 shows an example of a method for manufacturing a circuit of the present invention.

FIG. 14 shows an example of a method for manufacturing a circuit of the present invention.

[Explanation of symbols]

 104 semiconductor film 106 gate electrode 107 first TFT 108 second TFT 109 metal wiring 110 signal line 112 .. Voltage supply line 113... Selection line 115... Pixel electrode

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G09G 3/20 621 G09G 3/20 621M 3/36 3/36 H01L 29/786 H01L 29/78 616K 21 / 336

Claims (28)

[Claims] A first signal line formed on the substrate, a first signal line formed on the substrate, and a first gate formed on the substrate and connected to the first signal line; A top gate thin film transistor; a second signal line formed on the substrate and connected to one of a source and a drain of the first thin film transistor; and a second signal line formed on the substrate and A second top gate thin film transistor having a gate connected to a source, a voltage supply line formed on the substrate and connected to a drain of the second thin film transistor, formed on the substrate, and A drive circuit including an electrode connected to a source of a second thin film transistor, and a third top gate thin film transistor formed on the substrate. Thus, an electro-optical display device including a driving circuit for driving at least one of the first thin film transistor and the second thin film transistor. A first substrate having an insulating surface, a first signal line formed on the substrate, and a first gate formed on the substrate and connected to the first signal line. An inverted staggered thin film transistor; a second signal line formed on the substrate and connected to a drain of the first thin film transistor; and a second signal line formed on the substrate and connected to a source of the first thin film transistor A second inverted staggered thin film transistor having a gate formed thereon, a voltage supply line formed on the substrate and connected to a drain of the second thin film transistor, and a second thin film transistor formed on the substrate And a third inverted staggered thin film transistor formed on the substrate, wherein the first thin film transistor is connected to the first thin film transistor. And a driving circuit for driving at least one of the second thin film transistors. A first substrate having an insulating surface; a first signal line formed on the substrate; and a first gate formed on the substrate and connected to the first signal line. A thin film transistor; a second signal line formed on the substrate and connected to a drain of the first thin film transistor; and a gate formed on the substrate and connected to a source of the first thin film transistor. A second thin film transistor, a voltage supply line formed on the substrate and connected to a drain of the second thin film transistor, and a voltage supply line formed on the substrate and connected to a source of the second thin film transistor An electrode, a drive circuit having a third thin film transistor formed on the substrate, wherein the first thin film transistor and the second thin film transistor A driving circuit for driving at least one of the above. A first substrate having an insulating surface; a first signal line formed on the substrate; and a first gate formed on the substrate and connected to the first signal line. A top gate thin film transistor, a second signal line formed on the substrate and connected to a drain of the first thin film transistor, and a second signal line formed on the substrate and connected to a source of the first thin film transistor A second top gate type thin film transistor having a gate, a voltage supply line formed on the substrate and connected to a drain of the second thin film transistor, and on the first thin film transistor and the second thin film transistor. A flattening film formed; an electrode formed on the flattening film and connected to a source of the second thin film transistor; A driving circuit having a third top gate type thin film transistor formed on an electro-optical display device having a driving circuit for driving at least one of said first thin film transistor and the second thin film transistor. 5. A first substrate having an insulating surface, a first signal line formed on the substrate, and a first gate formed on the substrate and connected to the first signal line. An inverted staggered thin film transistor; a second signal line formed on the substrate and connected to a drain of the first thin film transistor; and a second signal line formed on the substrate and connected to a source of the first thin film transistor A second inverted staggered thin-film transistor having a gate, a voltage supply line formed on the substrate and connected to a drain of the second thin-film transistor, and on the first thin-film transistor and the second thin-film transistor. A formed flattening film; an electrode formed on the flattening film and connected to a source of the second thin film transistor; Have been the third a drive circuit having an inverted staggered thin film transistor, an electro-optical display device having a driving circuit for driving at least one of said first thin film transistor and the second thin film transistor. 6. A first substrate having an insulating surface, a first signal line formed on the substrate, and a first gate formed on the substrate and connected to the first signal line. A thin film transistor; a second signal line formed on the substrate and connected to a drain of the first thin film transistor; and a gate formed on the substrate and connected to a source of the first thin film transistor. A second thin film transistor, a voltage supply line formed on the substrate and connected to a drain of the second thin film transistor, and a flattening film formed on the first thin film transistor and the second thin film transistor An electrode formed on the planarization film and connected to a source of the second thin film transistor; and a third thin film transistor formed on the substrate. A driving circuit having a Njisuta, electro-optical display device having a driving circuit for driving at least one of said first thin film transistor and the second thin film transistor. 7. A first circuit having a substrate having an insulating surface, a first signal line formed on the substrate, and a gate formed on the substrate and connected to the first signal line. A second signal line formed on the substrate and connected to the drain of the first thin film transistor; and a second signal line formed on the substrate and connected to the source of the first thin film transistor A second top-gate thin film transistor having a gate formed thereon; a voltage supply line formed on the substrate and connected to a drain of the second thin film transistor; a second power supply line formed on the substrate; A drive circuit having an electrode connected to a source of the thin film transistor, and a third top gate thin film transistor formed on the substrate, wherein the first An electro-optical display device comprising: a thin film transistor; and a driving circuit for driving at least one of the second thin film transistor, wherein a channel width of the second thin film transistor is equal to the first width.
An electro-optical display device that is larger than the channel width of the thin film transistor. 8. A first substrate having an insulating surface; a first signal line formed on the substrate; and a first gate formed on the substrate and connected to the first signal line. An inverted staggered thin film transistor; a second signal line formed on the substrate and connected to a drain of the first thin film transistor; and a second signal line formed on the substrate and connected to a source of the first thin film transistor A second inverted staggered thin film transistor having a gate formed thereon, a voltage supply line formed on the substrate and connected to a drain of the second thin film transistor, and a second thin film transistor formed on the substrate And a third inverted staggered thin film transistor formed on the substrate, wherein the first thin film transistor is connected to the first thin film transistor. And a driving circuit for driving at least one of the second thin film transistors, wherein the channel width of the second thin film transistors is
An electro-optical display device that is larger than the channel width of the thin film transistor. 9. A first substrate having an insulating surface, a first signal line formed on the substrate, and a first gate formed on the substrate and connected to the first signal line. A thin film transistor; a second signal line formed on the substrate and connected to a drain of the first thin film transistor; and a gate formed on the substrate and connected to a source of the first thin film transistor. A second thin film transistor, a voltage supply line formed on the substrate and connected to a drain of the second thin film transistor, and a voltage supply line formed on the substrate and connected to a source of the second thin film transistor An electrode, a drive circuit having a third thin film transistor formed on the substrate, wherein the first thin film transistor and the second thin film transistor A driving circuit that drives at least one of the first and second thin film transistors, wherein a channel width of the second thin film transistor is equal to the first width of the first thin film transistor.
An electro-optical display device that is larger than the channel width of the thin film transistor. 10. A substrate having an insulating surface, a first signal line formed on the substrate, a channel region formed on the substrate, and a first pair of impurity regions, A first top gate thin film transistor having a gate connected to a first signal line; and a first top gate thin film transistor formed on the substrate and connected to one of the first pair of impurity regions of the first thin film transistor. A signal line, a channel region formed on the substrate, and a second pair of impurity regions, and a gate connected to the other of the first pair of impurity regions of the first thin film transistor A second top-gate thin film transistor having: a voltage supply line formed on the substrate and connected to one of the second pair of impurity regions of the second thin film transistor; Are formed on, and the third with the second of said electrode connected to the other of the second pair of impurity regions, a channel formation region formed on the substrate of the thin film transistor
An electro-optical display device, comprising: a driving circuit having the top gate type thin film transistor according to (1), wherein the driving circuit drives at least one of the first thin film transistor and the second thin film transistor. 11. A substrate having an insulating surface, a first signal line formed on the substrate, a channel region formed on the substrate, and a first pair of impurity regions, A first inverted staggered thin film transistor having a gate connected to a first signal line; and a first inverted staggered thin film transistor formed on the substrate and connected to one of the first pair of impurity regions of the first thin film transistor. A signal line, a channel region formed on the substrate, and a second pair of impurity regions, and a gate connected to the other of the first pair of impurity regions of the first thin film transistor A second inverted staggered thin film transistor having: a voltage supply line formed on the substrate and connected to one of the second pair of impurity regions of the second thin film transistor; formed on the substrate; Is, and the third with the second of said second pair of the other electrode connected to the impurity regions, a channel formation region formed on the substrate of the thin film transistor
An electro-optical display device, comprising: a driving circuit having an inverted staggered thin film transistor according to the above, wherein the driving circuit drives at least one of the first thin film transistor and the second thin film transistor. 12. A substrate having an insulating surface, a first signal line formed on the substrate, a channel region formed on the substrate, and a first pair of impurity regions, A first thin film transistor having a gate connected to a first signal line; and a second signal formed on the substrate and connected to one of the first pair of impurity regions of the first thin film transistor. A line, a channel region formed on the substrate, and a second pair of impurity regions, and a gate having a gate connected to the other of the first pair of impurity regions of the first thin film transistor. A second thin film transistor; a voltage supply line formed on the substrate and connected to one of the second pair of impurity regions of the second thin film transistor; a second voltage supply line formed on the substrate; Third with the second pair of the other electrode connected to the impurity regions, a channel formation region formed on the substrate film transistor
An electro-optical display device, comprising: a driving circuit having the thin film transistor according to (1), wherein the driving circuit drives at least one of the first thin film transistor and the second thin film transistor. 13. A semiconductor device comprising: a substrate having an insulating surface; a first signal line formed on the substrate; a channel region formed on the substrate; and a first pair of impurity regions. A first top gate thin film transistor having a gate connected to a first signal line; and a first top gate thin film transistor formed on the substrate and connected to one of the first pair of impurity regions of the first thin film transistor. A signal line, a channel region formed on the substrate, and a second pair of impurity regions, and a gate connected to the other of the first pair of impurity regions of the first thin film transistor A second top gate type thin film transistor having: a voltage supply line formed on the substrate and connected to one of the second pair of impurity regions of the second thin film transistor; A thin film transistor and a flattening film formed on the second thin film transistor; and an electrode formed on the flattening film and connected to the other of the second pair of impurity regions of the second thin film transistor; A third having a channel forming region formed on the substrate;
An electro-optical display device, comprising: a driving circuit having the top gate type thin film transistor according to (1), wherein the driving circuit drives at least one of the first thin film transistor and the second thin film transistor. 14. A semiconductor device comprising: a substrate having an insulating surface; a first signal line formed on the substrate; a channel region formed on the substrate; and a first pair of impurity regions. A first inverted staggered thin film transistor having a gate connected to a first signal line; and a first inverted staggered thin film transistor formed on the substrate and connected to one of the first pair of impurity regions of the first thin film transistor. A signal line, a channel region formed on the substrate, and a second pair of impurity regions, and a gate connected to the other of the first pair of impurity regions of the first thin film transistor A second inverted staggered thin film transistor, comprising: a voltage supply line formed on the substrate and connected to one of the second pair of impurity regions of the second thin film transistor; and a first thin film transistor. A transistor and a flattening film formed on the second thin film transistor; an electrode formed on the flattening film and connected to the other of the second pair of impurity regions of the second thin film transistor; A third having a channel forming region formed on the substrate;
An electro-optical display device, comprising: a driving circuit having an inverted staggered thin film transistor according to the above, wherein the driving circuit drives at least one of the first thin film transistor and the second thin film transistor. 15. A substrate having an insulating surface, a first signal line formed on the substrate, a channel region formed on the substrate, and a first pair of impurity regions, A first thin film transistor having a gate connected to a first signal line; and a second signal formed on the substrate and connected to one of the first pair of impurity regions of the first thin film transistor. A line, a channel region formed on the substrate, and a second pair of impurity regions, and a gate having a gate connected to the other of the first pair of impurity regions of the first thin film transistor. A second thin film transistor; a voltage supply line formed on the substrate and connected to one of the second pair of impurity regions of the second thin film transistor; A flattening film formed on the second thin film transistor; an electrode formed on the flattening film and connected to the other of the second pair of impurity regions of the second thin film transistor; Third having a formed channel forming region
An electro-optical display device, comprising: a driving circuit having the thin film transistor according to (1), wherein the driving circuit drives at least one of the first thin film transistor and the second thin film transistor. 16. A semiconductor device comprising: a substrate having an insulating surface; a first signal line formed on the substrate; a channel region formed on the substrate; and a first pair of impurity regions, A first top gate thin film transistor having a gate connected to a first signal line; and a first top gate thin film transistor formed on the substrate and connected to one of the first pair of impurity regions of the first thin film transistor. A signal line, a channel region formed on the substrate, and a second pair of impurity regions, and a gate connected to the other of the first pair of impurity regions of the first thin film transistor A second top-gate thin film transistor having: a voltage supply line formed on the substrate and connected to one of the second pair of impurity regions of the second thin film transistor; Are formed on, and the third with the second of said electrode connected to the other of the second pair of impurity regions, a channel formation region formed on the substrate of the thin film transistor
A drive circuit having a top-gate thin film transistor, wherein the drive circuit drives at least one of the first thin film transistor and the second thin film transistor; The channel width of the thin film transistor of
An electro-optical display device that is larger than the channel width of the thin film transistor. 17. A semiconductor device comprising: a substrate having an insulating surface; a first signal line formed on the substrate; a channel region formed on the substrate; and a first pair of impurity regions, A first inverted staggered thin film transistor having a gate connected to a first signal line; and a first inverted staggered thin film transistor formed on the substrate and connected to one of the first pair of impurity regions of the first thin film transistor. A signal line, a channel region formed on the substrate, and a second pair of impurity regions, and a gate connected to the other of the first pair of impurity regions of the first thin film transistor A second inverted staggered thin film transistor having: a voltage supply line formed on the substrate and connected to one of the second pair of impurity regions of the second thin film transistor; formed on the substrate; Is, and the third with the second of said second pair of the other electrode connected to the impurity regions, a channel formation region formed on the substrate of the thin film transistor
A drive circuit having an inverted staggered thin film transistor according to claim 1, wherein said drive circuit drives at least one of said first thin film transistor and said second thin film transistor; The channel width of the thin film transistor of
An electro-optical display device that is larger than the channel width of the thin film transistor. 18. A substrate having an insulating surface, a first signal line formed on the substrate, a channel region formed on the substrate, and a first pair of impurity regions, A first thin film transistor having a gate connected to a first signal line; and a second signal formed on the substrate and connected to one of the first pair of impurity regions of the first thin film transistor. A line, a channel region formed on the substrate, and a second pair of impurity regions, and a gate having a gate connected to the other of the first pair of impurity regions of the first thin film transistor. A second thin film transistor; a voltage supply line formed on the substrate and connected to one of the second pair of impurity regions of the second thin film transistor; a second voltage supply line formed on the substrate; Third with the second pair of the other electrode connected to the impurity regions, a channel formation region formed on the substrate film transistor
A drive circuit that drives at least one of the first thin film transistor and the second thin film transistor, the electro-optical display device comprising: The channel width is the first
An electro-optical display device that is larger than the channel width of the thin film transistor. 19. A substrate having an insulating surface, a first signal line formed on the substrate, and a channel region formed on the substrate, and connected to the first signal line. A first top gate thin film transistor having a gate, a second signal line formed on the substrate and connected to a drain of the first thin film transistor, and a channel region formed on the substrate A second top-gate thin film transistor having a gate connected to a source of the first thin film transistor; a voltage supply line formed on the substrate and connected to a drain of the second thin film transistor; An electrode formed on a substrate and connected to a source of the second thin film transistor, wherein the second thin film transistor The channel width of the register is the first
An electro-optical display device that is larger than the channel width of the thin film transistor. 20. A semiconductor device having a substrate having an insulating surface, a first signal line formed on the substrate, and a channel region formed on the substrate, and connected to the first signal line. A first inverted staggered thin film transistor having a gate, a second signal line formed on the substrate and connected to a drain of the first thin film transistor, and a channel region formed on the substrate A second inverted staggered thin film transistor having a gate connected to a source of the first thin film transistor; a voltage supply line formed on the substrate and connected to a drain of the second thin film transistor; An electrode formed on a substrate and connected to a source of the second thin film transistor. The channel width is the first
An electro-optical display device that is larger than the channel width of the thin film transistor. 21. A substrate having an insulating surface, a first signal line formed on the substrate, and a channel region formed on the substrate, and connected to the first signal line. A first thin film transistor having a gate, a second signal line formed on the substrate and connected to a drain of the first thin film transistor, and a channel region formed on the substrate; and A second thin film transistor having a gate connected to a source of the first thin film transistor; a voltage supply line formed on the substrate and connected to a drain of the second thin film transistor; formed on the substrate; And an electrode connected to the source of the second thin film transistor, wherein the channel width of the second thin film transistor is 1
An electro-optical display device that is larger than the channel width of the thin film transistor. 22. A semiconductor device comprising: a substrate having an insulating surface; a first signal line formed on the substrate; a channel region formed on the substrate; and a first pair of impurity regions. A first top gate thin film transistor having a gate connected to a first signal line; and a first top gate thin film transistor formed on the substrate and connected to one of the first pair of impurity regions of the first thin film transistor. A signal line, a channel region formed on the substrate, and a second pair of impurity regions, and a gate connected to the other of the first pair of impurity regions of the first thin film transistor A second top-gate thin film transistor having: a voltage supply line formed on the substrate and connected to one of the second pair of impurity regions of the second thin film transistor; And an electrode connected to the other of the second pair of impurity regions of the second thin film transistor, wherein the channel width of the second thin film transistor is 1
An electro-optical display device that is larger than the channel width of the thin film transistor. 23. A semiconductor device comprising: a substrate having an insulating surface; a first signal line formed on the substrate; a channel region formed on the substrate; and a first pair of impurity regions. A first inverted staggered thin film transistor having a gate connected to a first signal line; and a first inverted staggered thin film transistor formed on the substrate and connected to one of the first pair of impurity regions of the first thin film transistor. A signal line, a channel region formed on the substrate, and a second pair of impurity regions, and a gate connected to the other of the first pair of impurity regions of the first thin film transistor A second inverted staggered thin film transistor having: a voltage supply line formed on the substrate and connected to one of the second pair of impurity regions of the second thin film transistor; formed on the substrate; Is, and the the other electrode connected to said second pair of impurity regions of the second thin film transistor, an electro-optical display devices having a channel width of the second thin film transistor, the first
An electro-optical display device that is larger than the channel width of the thin film transistor. 24. A semiconductor device comprising: a substrate having an insulating surface; a first signal line formed on the substrate; a channel region formed on the substrate; and a first pair of impurity regions, A first thin film transistor having a gate connected to a first signal line; and a second signal formed on the substrate and connected to one of the first pair of impurity regions of the first thin film transistor. A line, a channel region formed on the substrate, and a second pair of impurity regions, and a gate having a gate connected to the other of the first pair of impurity regions of the first thin film transistor. A second thin film transistor; a voltage supply line formed on the substrate and connected to one of the second pair of impurity regions of the second thin film transistor; a second voltage supply line formed on the substrate; An electro-optical display device having an electrode connected to the other of said second pair of impurity regions of the film transistor, the channel width of the second thin film transistor, the first
An electro-optical display device that is larger than the channel width of the thin film transistor. 25. The electro-optical display according to claim 1, further comprising a liquid crystal layer. 26. The electro-optical display device according to claim 4, wherein a flattening film is formed on the third thin film transistor. 27. The electro-optical display device according to claim 5, wherein a flattening film is formed on the third thin film transistor. 28. The electro-optical display device according to claim 6, wherein a flattening film is formed on the third thin film transistor.