JP2000138384A - Amorphous semiconductor device and its manufacture - Google Patents
Amorphous semiconductor device and its manufactureInfo
- Publication number
- JP2000138384A JP2000138384A JP10310468A JP31046898A JP2000138384A JP 2000138384 A JP2000138384 A JP 2000138384A JP 10310468 A JP10310468 A JP 10310468A JP 31046898 A JP31046898 A JP 31046898A JP 2000138384 A JP2000138384 A JP 2000138384A
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- Prior art keywords
- amorphous semiconductor
- layer
- type
- oxide layer
- adjacent
- Prior art date
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Classifications
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
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- Photovoltaic Devices (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、相隣接して配され
た、互いに異なる導電型を有する非晶質半導体層を備え
る太陽電池や光センサ等の非晶質半導体素子に係り、特
に界面特性の向上した非晶質半導体素子及びその製造方
法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an amorphous semiconductor device such as a photovoltaic cell and a solar cell having amorphous semiconductor layers having mutually different conductivity types disposed adjacent to each other, and more particularly to an interface characteristic. And a method of manufacturing the same.
【０００２】[0002]
【従来の技術】従来、非晶質シリコン（ａ−Ｓｉ）、非
晶質シリコンカーバイド（ａ−ＳｉＣ）、非晶質シリコ
ンゲルマニウム（ａ−ＳｉＧｅ）、或いは微結晶シリコ
ン（μｃ−Ｓｉ）等の非晶質半導体は、太陽電池や光セ
ンサ等の半導体素子用材料として用いられている。そし
て、これら非晶質半導体を用いた非晶質半導体素子は、
通常基板上にｐ，ｉ及びｎ型の導電型を有する非晶質半
導体層が積層されて構成されている。2. Description of the Related Art Conventionally, amorphous silicon (a-Si), amorphous silicon carbide (a-SiC), amorphous silicon germanium (a-SiGe), microcrystalline silicon (μc-Si), etc. Amorphous semiconductors are used as materials for semiconductor elements such as solar cells and optical sensors. And, an amorphous semiconductor element using these amorphous semiconductors,
Usually, an amorphous semiconductor layer having p, i and n-type conductivity is laminated on a substrate.
【０００３】[0003]
【発明が解決しようとする課題】ところで、従来の非晶
質半導体素子を製造するにあたっては、プラズマＣＶＤ
法や光ＣＶＤ法等のＣＶＤ法を用い、高周波電界或いは
光のエネルギーにより原料ガスを分解し、そして生じた
分解生成物を基板上に堆積することにより非晶質半導体
層を形成していた。然し乍ら、斯かる方法によれば非晶
質半導体層の形成時に、上記高周波電界或いは光のエネ
ルギーが下地となる非晶質半導体層内部における構成元
素同士の結合を切るために、下地となる非晶質半導体層
の欠陥が増加する、という課題があった。In manufacturing a conventional amorphous semiconductor device, plasma CVD is used.
An amorphous semiconductor layer is formed by decomposing a source gas by a high-frequency electric field or light energy using a CVD method such as a photo-CVD method or the like, and depositing the generated decomposition product on a substrate. However, according to such a method, when the amorphous semiconductor layer is formed, the high-frequency electric field or light energy cuts off bonds between constituent elements inside the amorphous semiconductor layer serving as a base, so that the amorphous base There is a problem that defects of the high quality semiconductor layer increase.
【０００４】特に、一導電型の非晶質半導体層上に他導
電型の非晶質半導体層を形成するにあたっては、下地と
なる一導電型の非晶質半導体層中における導電型決定不
純物が他導電型の非晶質半導体層中に拡散し、該層の膜
特性を低下させるためにその影響は一層大きなものとな
っていた。[0004] In particular, in forming an amorphous semiconductor layer of another conductivity type on an amorphous semiconductor layer of one conductivity type, the conductivity type determining impurities in the amorphous semiconductor layer of one conductivity type serving as a base are not sufficient. The effect diffuses into the other conductive type amorphous semiconductor layer and deteriorates the film characteristics of the layer, so that the influence is further increased.
【０００５】また、斯かる課題を解決するために、下地
となる非晶質半導体層上にａ−ＳｉＣやａ−ＳｉＯ等の
プラズマに対する耐性の大きい界面層を形成する方法も
検討されているが、この界面層を形成するにあたっても
プラズマＣＶＤ法や光ＣＶＤ法を用いているために、同
じ問題が存在していた。In order to solve such a problem, a method of forming an interface layer having high resistance to plasma, such as a-SiC or a-SiO, on an underlying amorphous semiconductor layer has been studied. However, the same problem also exists in forming the interface layer because a plasma CVD method or an optical CVD method is used.
【０００６】本発明は、斯かる課題を解決し、界面特性
の向上した光起電力素子及びその製造方法を提供するも
のである。The present invention solves the above problems and provides a photovoltaic element having improved interface characteristics and a method for manufacturing the same.
【０００７】[0007]
【課題を解決するための手段】上記従来の課題を解決す
るために、本発明非晶質半導体素子は、基板上に、相隣
接して配された、互いに異なる導電型を有する非晶質半
導体層を備える非晶質半導体素子であって、相隣接する
前記非晶質半導体層の隣接界面に、相隣接する非晶質半
導体層のうち前記基板側に配された非晶質半導体層にお
ける主構成元素の自然酸化物層を設けたことを特徴とす
る。In order to solve the above-mentioned conventional problems, an amorphous semiconductor device according to the present invention comprises an amorphous semiconductor element having mutually different conductivity types disposed adjacent to each other on a substrate. An amorphous semiconductor element comprising a layer, wherein an adjacent interface between the adjacent amorphous semiconductor layers includes a main element of the amorphous semiconductor layer disposed on the substrate side among the adjacent amorphous semiconductor layers. A natural oxide layer of a constituent element is provided.
【０００８】また、基板上に、ｐ，ｉ及びｎ型の非晶質
半導体層が互いに隣接して配された非晶質半導体素子で
あって、前記ｐ型とｉ型の非晶質半導体層の隣接界面又
はｎ型とｉ型の非晶質半導体層の隣接界面のうち少なく
ともいずれか一方の隣接界面に、自然酸化物層を設けた
ことを特徴とする。An amorphous semiconductor device in which p, i, and n-type amorphous semiconductor layers are disposed adjacent to each other on a substrate, wherein the p-type and i-type amorphous semiconductor layers are provided. A native oxide layer is provided on at least one of the adjacent interface of the n-type and i-type amorphous semiconductor layers.
【０００９】さらには、基板上に、ｐ，ｉ及びｎ型の非
晶質半導体層からなる単位素子が、互いに隣接して配さ
れた非晶質半導体素子であって、相隣接する前記単位素
子の隣接界面に、相隣接する単位素子のうち前記基板側
に配された一方の単位素子において他方の単位素子側に
位置する前記非晶質半導体層における主構成元素の自然
酸化物層を設けたことを特徴とする。Further, an amorphous semiconductor element in which unit elements comprising p, i and n-type amorphous semiconductor layers are arranged adjacent to each other on a substrate, wherein the adjacent unit elements are adjacent to each other. A natural oxide layer of a main constituent element in the amorphous semiconductor layer located on the other unit element side in one unit element arranged on the substrate side among adjacent unit elements on the adjacent interface of It is characterized by the following.
【００１０】加えて、前記自然酸化物層の厚さが約０．
４ｎｍ〜約１ｎｍであることを特徴とする。[0010] In addition, the thickness of the native oxide layer is about 0.
It is 4 nm to about 1 nm.
【００１１】また、本発明製造方法は、一導電型を有す
る非晶質半導体層上に、他導電型の非晶質半導体層を形
成する工程を有する非晶質半導体素子の製造方法であっ
て、前記一導電型の非晶質半導体層上に該非晶質半導体
層における主構成元素の自然酸化物層を形成し、該自然
酸化物層上に前記他導電型の非晶質半導体層を形成する
ことを特徴とする。Further, the manufacturing method of the present invention is a method for manufacturing an amorphous semiconductor device, comprising a step of forming an amorphous semiconductor layer of another conductivity type on an amorphous semiconductor layer having one conductivity type. Forming a native oxide layer of a main constituent element in the amorphous semiconductor layer on the one conductivity type amorphous semiconductor layer, and forming the other conductivity type amorphous semiconductor layer on the native oxide layer It is characterized by doing.
【００１２】さらには、前記自然酸化物層を形成する工
程において、前記一導電型の非晶質半導体層表面に酸素
を含むガス状分子を供給することにより前記自然酸化物
層を形成することを特徴とする。Further, in the step of forming the native oxide layer, it is preferable that the native oxide layer is formed by supplying gaseous molecules containing oxygen to the surface of the one conductivity type amorphous semiconductor layer. Features.
【００１３】加えて、前記自然酸化物層を形成する工程
において、前記ガス状分子が分子状態を維持できる温度
に前記一導電型非晶質半導体層を保持することを特徴と
する。In addition, in the step of forming the native oxide layer, the one-conductivity-type amorphous semiconductor layer is maintained at a temperature at which the gaseous molecules can maintain a molecular state.
【００１４】尚、本発明において自然酸化物層とは、プ
ラズマや光照射等の外部からのエネルギーを与えずに形
成された層のことである。In the present invention, the natural oxide layer is a layer formed without applying external energy such as plasma or light irradiation.
【００１５】[0015]
【発明の実施の形態】以下に、本発明の実施の形態に係
る非晶質半導体素子について、図１に示す素子構造断面
図を参照して説明する。尚、以下の説明においては非晶
質半導体素子としての非晶質太陽電池について説明す
る。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An amorphous semiconductor device according to an embodiment of the present invention will be described below with reference to the device structure sectional view shown in FIG. In the following description, an amorphous solar cell as an amorphous semiconductor element will be described.
【００１６】同図において、１はガラスからなる基板で
あり、該基板１上にＳｎＯ2，ＩＴＯ等の透光性導電材
からなる透光性電極２が形成されている。そして、該透
光性電極２上には、ｐ型のａ−ＳｉＣ層３、ｉ型のａ−
Ｓｉ層４及びｎ型のμｃ−Ｓｉ層５が順次積層され、さ
らにｎ型μｃ−Ｓｉ層５上にはＡｇ、Ａｌ等の高反射性
の金属からなる裏面電極６が形成されている。In FIG. 1, reference numeral 1 denotes a substrate made of glass, on which a light-transmitting electrode 2 made of a light-transmitting conductive material such as SnO 2 or ITO is formed. A p-type a-SiC layer 3 and an i-type a-
An Si layer 4 and an n-type μc-Si layer 5 are sequentially stacked, and a back electrode 6 made of a highly reflective metal such as Ag or Al is formed on the n-type μc-Si layer 5.
【００１７】そして、同図に示す如く、相隣接するｐ型
のａ−ＳｉＣ層３とｉ型のａ−Ｓｉ層４との隣接界面
に、ＳｉＣの自然酸化物層ｂを備えている。即ち、ｐ型
とｉ型という互いに異なる導電型を有する非晶質半導体
層３及び４の隣接界面に、基板１側に位置するｐ型のａ
−ＳｉＣ層３の主構成元素であるＳｉＣの自然酸化物層
ｂを備えている。As shown in FIG. 1, a natural oxide layer b of SiC is provided at an adjacent interface between the adjacent p-type a-SiC layer 3 and i-type a-Si layer 4. That is, at the adjacent interface between the amorphous semiconductor layers 3 and 4 having different conductivity types of p-type and i-type, the p-type a
And-a natural oxide layer b of SiC which is a main constituent element of the SiC layer 3.
【００１８】従って、本実施の形態によれば、ｉ型のａ
−Ｓｉ層４を形成するにあたって下地が自然酸化物層ｂ
であるので、ｉ型のａ−Ｓｉ層４形成時の高周波電界或
いは光のエネルギーによりｐ型のａ−ＳｉＣ層３が悪影
響を受けることがない。Therefore, according to the present embodiment, the i-type a
In forming the Si layer 4, the underlying layer is a natural oxide layer b
Therefore, the p-type a-SiC layer 3 is not adversely affected by the high-frequency electric field or the energy of light when the i-type a-Si layer 4 is formed.
【００１９】また、ｐ型のａ−ＳｉＣ層３とｉ型のａ−
Ｓｉ層４との隣接界面に設けるのが自然酸化物層ｂであ
るので、その形成にあたってプラズマＣＶＤ法や光ＣＶ
Ｄ法等のＣＶＤ法を用いる必要がなく、高周波電界や光
のエネルギーによりｐ型のａ−ＳｉＣ層３が悪影響を受
けることがない。Further, the p-type a-SiC layer 3 and the i-type
Since the natural oxide layer b is provided at the interface adjacent to the Si layer 4, the formation thereof is performed by the plasma CVD method or the light CV method.
There is no need to use a CVD method such as the D method, and the p-type a-SiC layer 3 is not adversely affected by high-frequency electric field or light energy.
【００２０】従って、本実施の形態によれば、相隣接し
て配された、互いに異なる導電型を有する非晶質半導体
層の隣接界面における界面特性を向上させることがで
き、光電変換特性の良好な太陽電池を提供することがで
きる。Therefore, according to the present embodiment, it is possible to improve the interface characteristics at the adjacent interface between the amorphous semiconductor layers having different conductivity types, which are disposed adjacent to each other, and to improve the photoelectric conversion characteristics. Solar cell can be provided.
【００２１】次に、本発明に係る非晶質半導体素子であ
る非晶質太陽電池の他の実施の形態について、図２乃至
４に示す素子構造断面図を参照して説明する。尚、図２
乃至４において、図１と同様の機能を呈する部分には同
一の符号を付している。Next, another embodiment of the amorphous solar cell which is an amorphous semiconductor element according to the present invention will be described with reference to the element structure sectional views shown in FIGS. FIG.
4 to 4, the parts having the same functions as those in FIG.
【００２２】まず、図２に示す非晶質太陽電池において
は、ｉ型のａ−Ｓｉ層４及びｎ型のμｃ−Ｓｉ層５との
隣接界面に、基板１側に位置するｉ型のａ−Ｓｉ層４の
主構成元素であるＳｉの自然酸化物層ｂを備えている。First, in the amorphous solar cell shown in FIG. 2, an i-type a-Si layer 4 located on the substrate 1 side is provided at an adjacent interface between the i-type a-Si layer 4 and the n-type μc-Si layer 5. And-a natural oxide layer b of Si which is a main constituent element of the Si layer 4.
【００２３】また、図３に示す非晶質太陽電池において
は、ｐ型のａ−ＳｉＣ層３とｉ型のａ−Ｓｉ層４との隣
接界面にＳｉＣの自然酸化物層ｂ１を備え、且つｉ型の
ａ−Ｓｉ層４及びｎ型のμｃ−Ｓｉ層５との隣接界面
に、基板１側に位置するｉ型のａ−Ｓｉ層４の主構成元
素であるＳｉの自然酸化物層ｂ２を備えている。In the amorphous solar cell shown in FIG. 3, a natural oxide layer b1 of SiC is provided at an adjacent interface between the p-type a-SiC layer 3 and the i-type a-Si layer 4, and At the adjacent interface between the i-type a-Si layer 4 and the n-type μc-Si layer 5, a natural oxide layer b2 of Si, which is a main constituent element of the i-type a-Si layer 4 located on the substrate 1 side, is provided. It has.
【００２４】さらに、図４に示す非晶質太陽電池におい
ては、基板１上に設けられた透光性電極２上に、ｐ型の
ａ−ＳｉＣ層３、ｉ型のａ−Ｓｉ層４及びｎ型のμｃ−
Ｓｉ層５が順次積層されてなる単位セルＵＣ１及びＵＣ
２が積層されており、相隣接する単位セルＵＣ１、ＵＣ
２の隣接界面に、基板１側の単位セルＵＣ１において他
方の単位セルＵＣ２側に位置するｎ型のμｃ−Ｓｉ層５
の主構成元素であるＳｉの自然酸化物層ｂを備えてい
る。Further, in the amorphous solar cell shown in FIG. 4, a p-type a-SiC layer 3, an i-type a-Si layer 4 and a p-type a-SiC layer 4 are formed on a light-transmitting electrode 2 provided on a substrate 1. n-type μc-
Unit cells UC1 and UC in which Si layers 5 are sequentially stacked
2 are stacked, and adjacent unit cells UC1, UC
In the unit cell UC1 on the substrate 1 side, the n-type μc-Si layer 5 located on the other unit cell UC2 side
A natural oxide layer b of Si, which is a main constituent element of the above.
【００２５】以上図２乃至４に示した非晶質太陽電池
も、図１に示した非晶質太陽電池と同様に、相隣接して
配された、互いに異なる導電型を有する非晶質半導体層
の隣接界面に、基板側に位置する非晶質半導体層の主構
成元素の自然酸化物層ｂを備える構成を備えるために、
界面特性が向上し、光電変換特性が向上するという効果
を奏する。 （実施例）以下に、本発明の実施例について説明する。The amorphous solar cells shown in FIGS. 2 to 4 are also adjacent to each other and have different conductivity types, similarly to the amorphous solar cell shown in FIG. In order to provide a configuration including a native oxide layer b of a main constituent element of the amorphous semiconductor layer located on the substrate side at an adjacent interface between the layers,
This has the effect of improving the interface characteristics and improving the photoelectric conversion characteristics. (Examples) Examples of the present invention will be described below.
【００２６】非晶質半導体素子の製造装置として、図５
の概略構成図に示すプラズマＣＶＤ装置を用いた。FIG. 5 shows an apparatus for manufacturing an amorphous semiconductor element.
The plasma CVD apparatus shown in FIG.
【００２７】同図において、１１は基板透光性電極２が
形成された基板１を装置内に導入するためのするための
仕込室であり、１２は各非晶質半導体層を形成後、基板
１を装置外に取り出すための取出室である。In the figure, reference numeral 11 denotes a preparation chamber for introducing the substrate 1 on which the substrate light-transmitting electrode 2 is formed into the apparatus, and 12 denotes a substrate after forming each amorphous semiconductor layer. This is an extraction room for taking out the device 1 outside the apparatus.
【００２８】また、Ｐ，Ｉ及びＮは夫々ｐ型、ｉ型及び
ｎ型の非晶質半導体層を形成するための反応室であり、
各反応室Ｐ，Ｉ及びＮ内には夫々グロー放電プラズマを
生起するための一対の平行平板電極２１が設けられてい
る。そして、これら反応室Ｐ，Ｉ及びＮ内には夫々基板
１を加熱するためのヒータ（不図示）が設けられ、さら
に図示しない反応ガス供給系から所定の反応ガスが反応
室ｐ，ｉ及びｎ内に供給される構成とされている。P, I, and N are reaction chambers for forming p-type, i-type, and n-type amorphous semiconductor layers, respectively.
A pair of parallel plate electrodes 21 for generating glow discharge plasma are provided in each of the reaction chambers P, I, and N, respectively. A heater (not shown) for heating the substrate 1 is provided in each of the reaction chambers P, I, and N, and predetermined reaction gases are supplied from reaction gas supply systems (not shown) to the reaction chambers p, i, and n. It is configured to be supplied inside.
【００２９】さらに、Ｂは自然酸化物層を形成するため
の反応室であり、装置外に設けられた窒素ガス供給系か
ら窒素ガスが、純水の入ったバブラー３１中を通過する
ことにより水分を含んだ状態で、反応室Ｂ内に供給され
る構成となっている。さらに、同反応室Ｂ中には基板を
加熱又は保温するためのヒータ（不図示）が設けられて
いる。Reference numeral B denotes a reaction chamber for forming a native oxide layer, and a nitrogen gas is supplied from a nitrogen gas supply system provided outside the apparatus through a bubbler 31 containing pure water. Is supplied into the reaction chamber B in a state where Further, a heater (not shown) for heating or keeping the substrate warm is provided in the reaction chamber B.
【００３０】そして、斯かる製造装置を用いて透光性電
極の形成された基板１上に、表１に示す反応条件を用い
て非晶質半導体層を積層し、この非晶質半導体層上にス
パッタ法を用いてＡｇからなる裏面電極を形成して図１
乃至図３に示す構造の非晶質太陽電池を製造した。尚、
図１の構造のサンプルを実施例１、図２の構造のサンプ
ルを実施例２、図３の構造のサンプルを実施例３として
おり、表１に示す如く、ｐ，ｉ及びｎ型の各非晶質半導
体層の形成条件はいずれの実施例サンプルについても同
一である。Then, an amorphous semiconductor layer is laminated under the reaction conditions shown in Table 1 on the substrate 1 on which the translucent electrode is formed by using such a manufacturing apparatus. A back electrode made of Ag is formed on the substrate by sputtering, and FIG.
An amorphous solar cell having the structure shown in FIGS. still,
The sample of the structure of FIG. 1 is Example 1, the sample of the structure of FIG. 2 is Example 2, and the sample of the structure of FIG. 3 is Example 3. As shown in Table 1, each of the p, i, and n type The conditions for forming the crystalline semiconductor layer are the same for all the samples of the examples.
【００３１】また、表２に示す形成条件を用いて図４に
示す構造の非晶質太陽電池を製造し、これを実施例４と
した。An amorphous solar cell having the structure shown in FIG. 4 was manufactured under the forming conditions shown in Table 2, and this was designated as Example 4.
【００３２】[0032]
【表１】 [Table 1]
【００３３】[0033]
【表２】 尚、表１及び２において、Ｂ2Ｈ6ガス及びＰＨ3ガス
は、いずれも水素により１％に希釈されている。[Table 2] In Tables 1 and 2, both the B 2 H 6 gas and the PH 3 gas are diluted to 1% with hydrogen.
【００３４】さらに、比較用サンプルとして、自然酸化
物層を設けない以外は実施例１〜３と同一の条件を用い
て透光性電極の形成された基板上に、ｐ，ｉ及びｎの各
非晶質半導体層を形成した比較例１の非晶質太陽電池、
及びｐ型のａ−ＳｉＣ層３とｉ型のａ−Ｓｉ層４との隣
接界面に、プラズマＣＶＤ法を用いて厚さ約０．６ｎｍ
のａ−ＳｉＣ：Ｏ酸化物層を設けた比較例２の非晶質半
導体素子を用意した。また、自然酸化物層を設けない以
外は表２に示す条件と同一の条件で比較例３の光起電力
素子を製造した。Further, as a comparative sample, each of p, i and n was formed on the substrate on which the light-transmitting electrode was formed under the same conditions as in Examples 1 to 3 except that the natural oxide layer was not provided. An amorphous solar cell of Comparative Example 1 in which an amorphous semiconductor layer was formed,
A thickness of about 0.6 nm is formed on the adjacent interface between the p-type a-SiC layer 3 and the i-type a-Si layer 4 by using a plasma CVD method.
The amorphous semiconductor device of Comparative Example 2 provided with the a-SiC: O oxide layer was prepared. In addition, a photovoltaic element of Comparative Example 3 was manufactured under the same conditions as those shown in Table 2 except that the natural oxide layer was not provided.
【００３５】そして、上記実施例１〜３のサンプル及び
比較例１，２のサンプルについて、夫々の光電変換特性
をＡＭ１．５、１００ｍＷ／ｃｍ2、２５℃の条件で測
定した結果を表２に、また実施例４のサンプルと比較例
３のサンプルについて光電変換特性を測定した結果を表
４に示す。Table 2 shows the results of measuring the photoelectric conversion characteristics of the samples of Examples 1 to 3 and the samples of Comparative Examples 1 and 2 at AM 1.5, 100 mW / cm 2 and 25 ° C. Table 4 shows the results of measuring the photoelectric conversion characteristics of the sample of Example 4 and the sample of Comparative Example 3.
【００３６】[0036]
【表３】 [Table 3]
【００３７】[0037]
【表４】 同表から明らかに、本実施例のサンプルにより高い変換
効率が得られており、本発明により非晶質半導体素子の
特性を向上できることがわかる。[Table 4] It is apparent from the table that the sample of this example has higher conversion efficiency, and that the characteristics of the amorphous semiconductor device can be improved by the present invention.
【００３８】次に、上述の実施例１〜４のサンプルにつ
いて、自然酸化物層の膜厚を断面ＴＥＭ（透過型電子顕
微鏡）、及びＳＩＭＳ（二次イオン質量分析）を用いて
測定したところ、ｐ型ａ−ＳｉＣ層とｉ型ａ−Ｓｉ層と
の間に設けたＳｉＣの自然酸化物層の厚さは約０．６ｎ
ｍであり、ｉ型ａ−Ｓｉ層とｎ型μｃ−Ｓｉ層との間に
設けたＳｉの自然酸化物層の厚さは約０．８ｎｍであっ
た。また、実施例４のサンプルにおいて、相隣接する単
位セルＵＣ、ＵＣの接合界面において、基板側の単位セ
ルＵＣにおけるｎ型のμｃ−Ｓｉ層５と、背面側の単位
セルＵＣにおけるｐ型のａ−ＳｉＣ層３との界面に設け
たＳｉの自然酸化物層の厚さは約０．７ｎｍであった。Next, for the samples of Examples 1 to 4, the thickness of the native oxide layer was measured using a cross-sectional TEM (transmission electron microscope) and SIMS (secondary ion mass spectrometry). The thickness of the natural oxide layer of SiC provided between the p-type a-SiC layer and the i-type a-Si layer is about 0.6 n.
m, and the thickness of the natural oxide layer of Si provided between the i-type a-Si layer and the n-type μc-Si layer was about 0.8 nm. Further, in the sample of Example 4, the n-type μc-Si layer 5 in the unit cell UC on the substrate side and the p-type a in the unit cell UC on the back side at the junction interface between adjacent unit cells UC and UC. -The thickness of the natural oxide layer of Si provided at the interface with the SiC layer 3 was about 0.7 nm.
【００３９】そこで、実施例１のサンプル形成条件を用
い、自然酸化物層の形成時間を調整することにより自然
酸化物層の膜厚を変化させて形成した光起電力素子を形
成し、ＡＭ１．５、１００ｍＷ／ｃｍ2２５℃の条件で
光起電力特性を測定した。この結果得られた自然酸化物
層と光電変換効率との関係を図６の特性図に示す。Therefore, a photovoltaic element formed by changing the thickness of the natural oxide layer by adjusting the formation time of the natural oxide layer using the sample forming conditions of Example 1 was formed. 5, 100 mW / cm 2 Photovoltaic characteristics were measured at 25 ° C. The relationship between the resulting natural oxide layer and the photoelectric conversion efficiency is shown in the characteristic diagram of FIG.
【００４０】同図から明らかに、ｐ型ａ−ＳｉＣ層とｉ
型ａ−Ｓｉ層との間に設けたＳｉＣの自然酸化物層の厚
さを０．４〜１ｎｍの範囲とすることにより、比較例１
及び２のサンプルよりも高い光電変換効率を得ることが
できた。As is apparent from the figure, the p-type a-SiC layer and the i-type
By setting the thickness of the natural oxide layer of SiC provided between the mold and the a-Si layer in the range of 0.4 to 1 nm, Comparative Example 1
And higher photoelectric conversion efficiencies than those of the samples No. 2 and No. 2.
【００４１】さらに、実施例２のサンプル形成条件を用
い、自然酸化物層の形成時間を調整することにより自然
酸化物層の膜厚を変化させて形成した光起電力素子を形
成し、ＡＭ１．５、１００ｍＷ／ｃｍ2２５℃の条件で
光起電力特性を測定した。この結果得られた自然酸化物
層と光電変換効率との関係を図７の特性図に示す。Further, the photovoltaic element formed by changing the thickness of the natural oxide layer by adjusting the formation time of the natural oxide layer using the sample forming conditions of Example 2 was formed. 5, 100 mW / cm 2 Photovoltaic characteristics were measured at 25 ° C. FIG. 7 is a characteristic diagram showing the relationship between the resulting natural oxide layer and the photoelectric conversion efficiency.
【００４２】同図から明らかに、ｉ型ａ−Ｓｉ層とｎ型
μｃ−ＳｉＣとの間に設けたＳｉの自然酸化物層の厚さ
を０．４〜１ｎｍの範囲とすることにより、比較例１及
び２のサンプルよりも高い光電変換効率を得ることがで
きた。As is apparent from the figure, the thickness of the natural oxide layer of Si provided between the i-type a-Si layer and the n-type μc-SiC is set in the range of 0.4 to 1 nm, so that the comparison can be made. Higher photoelectric conversion efficiency than the samples of Examples 1 and 2 could be obtained.
【００４３】加えて、実施例４のサンプル形成条件を用
い、自然酸化物層の形成時間を調整することにより自然
酸化物層の膜厚を変化させて形成した光起電力素子を形
成し、ＡＭ１．５、１００ｍＷ／ｃｍ2２５℃の条件で
光起電力特性を測定した。この結果得られた自然酸化物
層と光電変換効率との関係を図８の特性図に示す。In addition, a photovoltaic element formed by changing the thickness of the native oxide layer by adjusting the formation time of the native oxide layer using the sample formation conditions of Example 4 was formed, The photovoltaic characteristics were measured under the conditions of 0.5, 100 mW / cm 2 and 25 ° C. The relationship between the resulting natural oxide layer and the photoelectric conversion efficiency is shown in the characteristic diagram of FIG.
【００４４】同図から明らかに、基板側の単位セルＵＣ
１におけるｎ型のμｃ−Ｓｉ層５と、背面側の単位セル
ＵＣ２におけるｐ型のａ−ＳｉＣ層３との界面に設けた
Ｓｉの自然酸化物層の厚さを０．４〜１ｎｍの範囲とす
ることにより、比較例３のサンプルよりも高い光電変換
効率を得ることができた。As is apparent from FIG. 5, the unit cell UC on the substrate side
The thickness of the natural oxide layer of Si provided at the interface between the n-type μc-Si layer 5 in 1 and the p-type a-SiC layer 3 in the unit cell UC2 on the back side is in the range of 0.4 to 1 nm. By doing so, a higher photoelectric conversion efficiency than that of the sample of Comparative Example 3 could be obtained.
【００４５】従って、自然酸化物層の厚さは設ける位置
に拘らず、０．４〜１ｎｍの範囲が好ましい。Therefore, the thickness of the native oxide layer is preferably in the range of 0.4 to 1 nm, regardless of the position where the native oxide layer is provided.
【００４６】また、バブラー３１を通過させる窒素ガス
の流量を調整することにより自然酸化物層中の酸素の組
成比を変化させた光起電力素子を形成し、その光電変換
特性を測定した。この結果、酸素の組成比が多すぎると
直列抵抗成分の増加により光電変換特性が低下し、また
酸素の組成比が少なすぎると高周波電界或いは光のエネ
ルギーによるダメージを十分に低減できず、光電変換特
性が低下することから、酸素の組成比は自然酸化膜と同
程度が好ましい。Further, a photovoltaic element in which the composition ratio of oxygen in the native oxide layer was changed by adjusting the flow rate of nitrogen gas passing through the bubbler 31 was formed, and its photoelectric conversion characteristics were measured. As a result, if the composition ratio of oxygen is too large, the photoelectric conversion characteristics decrease due to an increase in the series resistance component, and if the composition ratio of oxygen is too small, damage due to a high-frequency electric field or light energy cannot be sufficiently reduced, and Since the characteristics are deteriorated, the composition ratio of oxygen is preferably equal to that of the natural oxide film.
【００４７】以上の実施例においては、自然酸化物層の
形成にあたって、加熱された基板表面に水分子を供給す
るようにしている。このようにすると、形成直後の非晶
質半導体層表面が水素で覆われているために比較的活性
度が高い状態となっており、このために基板表面に供給
された水分子が分解され易く、自然酸化物層を容易に形
成することができる。従って、水分子を供給する際の基
板表面の温度は、供給された水を分子状態で維持できる
温度が好ましい。In the above embodiment, water molecules are supplied to the heated substrate surface when forming the native oxide layer. In this case, since the surface of the amorphous semiconductor layer immediately after formation is covered with hydrogen, the activity is relatively high, so that water molecules supplied to the substrate surface are easily decomposed. And a natural oxide layer can be easily formed. Therefore, the temperature of the substrate surface when supplying the water molecules is preferably a temperature at which the supplied water can be maintained in a molecular state.
【００４８】また、水分子の代わりに例えば亜酸化窒
素、ＴＥＯＳ（テトラエトキシシラン），或いはＣＯ2
等の酸素を含むガスを基板表面に供給することによって
も、同様に、プラズマや光のエネルギーによりガスを分
解することなく、容易に自然酸化物層を形成することが
できる。Instead of water molecules, for example, nitrous oxide, TEOS (tetraethoxysilane), or CO 2
Also, by supplying a gas containing oxygen such as to the substrate surface, a natural oxide layer can be easily formed without decomposing the gas by the energy of plasma or light.
【００４９】さらに、上記実施例においては、自然酸化
物層を形成するための専用の反応室を備える製造装置を
用いて非晶質半導体素子の製造を行ったが、非晶質半導
体層形成用の反応室で自然酸化物層を形成するようにし
ても良い。然し乍ら、自然酸化物層の形成を非晶質半導
体層形成用の反応室で行うと、反応室内の壁面等に酸素
が付着し、この酸素が非晶質半導体層形成時に層中に混
入することにより非晶質半導体層の膜特性を低下させる
可能性がある。従って、自然酸化物層の形成は非晶質半
導体層形成用の反応室とは別の反応室で行うことが好ま
しい。Further, in the above embodiment, an amorphous semiconductor element was manufactured using a manufacturing apparatus having a dedicated reaction chamber for forming a native oxide layer. A natural oxide layer may be formed in the reaction chamber. However, when a native oxide layer is formed in a reaction chamber for forming an amorphous semiconductor layer, oxygen adheres to walls and the like in the reaction chamber, and this oxygen is mixed into the layer when the amorphous semiconductor layer is formed. This may degrade the film characteristics of the amorphous semiconductor layer. Therefore, the formation of the natural oxide layer is preferably performed in a different reaction chamber from the reaction chamber for forming the amorphous semiconductor layer.
【００５０】加えて、自然酸化物層の形成にあたって
は、上記のように反応室内で行う以外にも、例えば非晶
質半導体層形成後に製造装置外に取出して大気に曝すこ
とにより自然酸化物層を形成するようにしても良い。斯
かる大気中での酸化により自然酸化物層を形成する方法
を用いても、同様の効果を奏することができる。然し乍
ら、大気中で自然酸化物層の形成を行うと、大気中に含
まれる埃等の他の不純物も自然酸化物層中に混入し、製
造した非晶質半導体素子の素子特性や歩留を低下させる
おそれがある。従って、自然酸化物層の形成は製造装置
内で行うことが好ましい。さらに、自然酸化物層の形成
を反応室内で行うと、基板を途中で一旦大気に曝すこと
なく製造装置中で連続して行うことができるので、生産
性にも優れている。In addition, the formation of the native oxide layer is not limited to the above-described one performed in the reaction chamber. For example, the native oxide layer may be taken out of the manufacturing apparatus after the amorphous semiconductor layer is formed and exposed to the atmosphere. May be formed. The same effect can be obtained by using such a method of forming a natural oxide layer by oxidation in the atmosphere. However, when the natural oxide layer is formed in the air, other impurities such as dust contained in the air are also mixed into the natural oxide layer, and the element characteristics and yield of the manufactured amorphous semiconductor element are reduced. There is a risk of lowering. Therefore, the formation of the natural oxide layer is preferably performed in a manufacturing apparatus. Further, when the natural oxide layer is formed in the reaction chamber, the substrate can be continuously formed in the manufacturing apparatus without once exposing the substrate to the atmosphere, so that the productivity is excellent.
【００５１】また、本発明非晶質半導体素子は、上述の
ようにガラスからなる基板上にｐ，ｉ及びｎ型の非晶質
半導体層が順次形成された構造を有するものに限るもの
ではない。例えば表面に絶縁コートがなされたステンレ
ス板を基板として用い、この基板上にｎ，ｉ及びｐ型の
非晶質半導体層を形成し、さらに非晶質半導体層上に透
光性電極及び櫛形状の集電極を備えた非晶質半導体素子
においても本発明を適用することができる。The amorphous semiconductor device of the present invention is not limited to a device having a structure in which p, i and n-type amorphous semiconductor layers are sequentially formed on a glass substrate as described above. . For example, a stainless steel plate having an insulating coating on the surface is used as a substrate, n, i, and p-type amorphous semiconductor layers are formed on the substrate, and a light-transmitting electrode and a comb-shaped electrode are formed on the amorphous semiconductor layer. The present invention can also be applied to an amorphous semiconductor device provided with the collector electrode described above.
【００５２】加えて、本発明の非晶質半導体素子は上述
した太陽電池に限るものではなく、互いに異なる導電型
を有すると共に相隣接して配された非晶質半導体層を有
するものであれば良く、例えば光センサも本発明非晶質
半導体素子に含まれる。また、非晶質半導体層は上述し
たａ−Ｓｉ，ａ−ＳｉＣ或いはμｃ−Ｓｉからなる層に
限るものではなく、例えばａ−ＳｉＧｅ，ａ−ＳｉＳ
ｎ，μｃ−ＳｉＣ等他の非晶質半導体からなる層も含む
ことは言うまでもない。In addition, the amorphous semiconductor device of the present invention is not limited to the above-described solar cell, but may be any other device having an amorphous semiconductor layer having mutually different conductivity types and being arranged adjacent to each other. For example, an optical sensor is also included in the amorphous semiconductor device of the present invention. Further, the amorphous semiconductor layer is not limited to the layer made of a-Si, a-SiC or μc-Si described above, but may be, for example, a-SiGe, a-SiS.
Needless to say, a layer made of another amorphous semiconductor such as n, μc-SiC is also included.
【００５３】[0053]
【発明の効果】以上のように、本発明によれば、プラズ
マＣＶＤ法或いは光ＣＶＤ法における高周波放電或いは
光のエネルギーによる悪影響を低減でき、界面特性の優
れた非晶質半導体素子を提供することができる。As described above, according to the present invention, it is possible to reduce the adverse effects of high-frequency discharge or light energy in plasma CVD or photo-CVD, and to provide an amorphous semiconductor device having excellent interface characteristics. Can be.
【図１】本発明の実施形態に係る非晶質半導体素子の素
子構造断面図である。FIG. 1 is a sectional view of an element structure of an amorphous semiconductor element according to an embodiment of the present invention.
【図２】本発明の別の実施形態に係る非晶質半導体素子
の素子構造断面図である。FIG. 2 is a sectional view of an element structure of an amorphous semiconductor element according to another embodiment of the present invention.
【図３】本発明の他の実施形態に係る非晶質半導体素子
の素子構造断面図である。FIG. 3 is a cross-sectional view of an element structure of an amorphous semiconductor element according to another embodiment of the present invention.
【図４】本発明のさらに別の実施形態に係る非晶質半導
体素子の素子構造断面図である。FIG. 4 is a cross-sectional view of an element structure of an amorphous semiconductor element according to still another embodiment of the present invention.
【図５】実施例サンプルを製造するための製造装置の構
成図である。FIG. 5 is a configuration diagram of a manufacturing apparatus for manufacturing an example sample.
【図６】実施例１のサンプルにおける自然酸化物層の膜
厚と光電変換効率との関係を示す特性図である。FIG. 6 is a characteristic diagram showing the relationship between the thickness of the native oxide layer and the photoelectric conversion efficiency in the sample of Example 1.
【図７】実施例２のサンプルにおける自然酸化物層の膜
厚と光電変換効率との関係を示す特性図である。FIG. 7 is a characteristic diagram showing the relationship between the thickness of the native oxide layer and the photoelectric conversion efficiency in the sample of Example 2.
【図８】実施例４のサンプルにおける自然酸化物層の膜
厚と光電変換効率との関係を示す特性図である。FIG. 8 is a characteristic diagram showing the relationship between the thickness of the native oxide layer and the photoelectric conversion efficiency in the sample of Example 4.
１…基板、２…透光性電極、３…ｐ型ａ−ＳｉＣ層、４
…ｉ型ａ−Ｓｉ層、５…ｎ型μｃ−Ｓｉ層、６…裏面電
極、ｂ…自然酸化物層DESCRIPTION OF SYMBOLS 1 ... Substrate, 2 ... Translucent electrode, 3 ... p-type a-SiC layer, 4
... i-type a-Si layer, 5 ... n-type μc-Si layer, 6 ... back electrode, b ... natural oxide layer
Claims (7)
異なる導電型を有する非晶質半導体層を備える非晶質半
導体素子であって、相隣接する前記非晶質半導体層の隣
接界面に、相隣接する非晶質半導体層のうち前記基板側
に配された非晶質半導体層における主構成元素の自然酸
化物層を設けたことを特徴とする非晶質半導体素子。1. An amorphous semiconductor device comprising an amorphous semiconductor layer having mutually different conductivity types disposed adjacent to each other on a substrate, wherein the adjacent amorphous semiconductor layers are adjacent to each other. An amorphous semiconductor element, wherein a natural oxide layer of a main constituent element in an amorphous semiconductor layer disposed on the substrate side among adjacent amorphous semiconductor layers is provided at an interface.
体層が互いに隣接して配された非晶質半導体素子であっ
て、前記ｐ型とｉ型の非晶質半導体層の隣接界面又はｎ
型とｉ型の非晶質半導体層の隣接界面のうち少なくとも
いずれか一方の隣接界面に、自然酸化物層を設けたこと
を特徴とする非晶質半導体素子。2. An amorphous semiconductor device comprising a substrate and p, i, and n-type amorphous semiconductor layers disposed adjacent to each other, wherein the p-type and i-type amorphous semiconductor layers are provided. Adjacent interface or n
An amorphous semiconductor element, characterized in that a native oxide layer is provided on at least one of the adjacent interfaces between the type and i-type amorphous semiconductor layers.
体層からなる単位素子が、互いに隣接して配された非晶
質半導体素子であって、相隣接する前記単位素子の隣接
界面に、相隣接する単位素子のうち前記基板側に配され
た一方の単位素子において他方の単位素子側に位置する
前記非晶質半導体層における主構成元素の自然酸化物層
を設けたことを特徴とする非晶質半導体素子。3. An amorphous semiconductor device comprising: a unit element comprising p, i, and n-type amorphous semiconductor layers disposed on a substrate adjacent to each other; At the adjacent interface, a natural oxide layer of a main constituent element in the amorphous semiconductor layer located on the other unit element side in one unit element arranged on the substrate side among adjacent unit elements is provided. An amorphous semiconductor device characterized by the above-mentioned.
〜約１ｎｍであることを特徴とする請求項１乃至３のい
ずれかに記載の非晶質半導体素子。4. The thickness of the native oxide layer is about 0.4 nm.
The amorphous semiconductor device according to any one of claims 1 to 3, wherein the thickness is from about 1 nm to about 1 nm.
他導電型の非晶質半導体層を形成する工程を有する非晶
質半導体素子の製造方法であって、 前記一導電型の非晶質半導体層上に該非晶質半導体層に
おける主構成元素の自然酸化物層を形成し、該自然酸化
物層上に前記他導電型の非晶質半導体層を形成すること
を特徴とする非晶質半導体素子の製造方法。5. An amorphous semiconductor layer having one conductivity type,
What is claimed is: 1. A method for manufacturing an amorphous semiconductor element comprising a step of forming an amorphous semiconductor layer of another conductivity type, wherein a natural constituent element of a main constituent element in the amorphous semiconductor layer is formed on the amorphous semiconductor layer of one conductivity type. A method for manufacturing an amorphous semiconductor device, comprising: forming an oxide layer; and forming the other conductivity type amorphous semiconductor layer on the natural oxide layer.
て、前記一導電型の非晶質半導体層表面に酸素を含むガ
ス状分子を供給することにより前記自然酸化物層を形成
することを特徴とする請求項５記載の非晶質半導体素子
の製造方法。6. The step of forming the native oxide layer, wherein the native oxide layer is formed by supplying gaseous molecules containing oxygen to the surface of the one conductivity type amorphous semiconductor layer. The method for manufacturing an amorphous semiconductor device according to claim 5, wherein
て、前記ガス状分子が分子状態を維持できる温度に前記
一導電型非晶質半導体層を保持することを特徴とする請
求項６記載の非晶質半導体素子の製造方法。7. The method according to claim 6, wherein in the step of forming the native oxide layer, the one-conductivity-type amorphous semiconductor layer is maintained at a temperature at which the gaseous molecules can maintain a molecular state. A method for manufacturing an amorphous semiconductor device.
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|---|---|---|---|
| JP10310468A JP2000138384A (en) | 1998-10-30 | 1998-10-30 | Amorphous semiconductor device and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10310468A JP2000138384A (en) | 1998-10-30 | 1998-10-30 | Amorphous semiconductor device and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2000138384A true JP2000138384A (en) | 2000-05-16 |
Family
ID=18005617
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
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| Country | Link |
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| JP (1) | JP2000138384A (en) |
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