JP2000133545A - Laminated ceramic chip capacitor - Google Patents

Laminated ceramic chip capacitor

Info

Publication number
JP2000133545A
JP2000133545A JP10304559A JP30455998A JP2000133545A JP 2000133545 A JP2000133545 A JP 2000133545A JP 10304559 A JP10304559 A JP 10304559A JP 30455998 A JP30455998 A JP 30455998A JP 2000133545 A JP2000133545 A JP 2000133545A
Authority
JP
Japan
Prior art keywords
electrodes
electrode
multilayer ceramic
controlling
auxiliary
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10304559A
Other languages
Japanese (ja)
Other versions
JP3463161B2 (en
Inventor
Takashi Suzuki
尚 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TDK Corp
Original Assignee
TDK Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by TDK Corp filed Critical TDK Corp
Priority to JP30455998A priority Critical patent/JP3463161B2/en
Publication of JP2000133545A publication Critical patent/JP2000133545A/en
Application granted granted Critical
Publication of JP3463161B2 publication Critical patent/JP3463161B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To restrain discharging from front surfaces as well as side surfaces and provide a small-sized laminated ceramic chip capacitor of high capacity and high breakdown voltage. SOLUTION: To the basic structure, where a plurality of internal electrodes 1a to 1e and a plurality of dielectrics layers 2a to 2h are laminated alternately, a pair of supplementary electrodes 6a, 6b are additionally provided in parallel, having predetermined gaps G1, G2 on the side of internal terminals positioned as the outermost layer of internal electrodes 1a to 1e for controlling the surface discharge and supplementary electrodes 7a, 7b, 8a, 8b positioned in a pair on both ends which are closer to the outside than the internal electrodes 1a to 1e. These supplementary electrodes for controlling discharges are electrically connected with other external electrodes by pairs.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、マイコン,その他
各種の電子機器用として小型で高容量,高耐圧に構成す
る積層セラミックコンデンサに関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer ceramic capacitor having a small size, a high capacity, and a high withstand voltage for a microcomputer and other various electronic devices.

【0002】[0002]

【従来の技術】通常、積層セラミックコンデンサは図8
で示すように複数の相対向する内部電極10a〜10f
と誘電体層11a〜11fとを複数交互に複数積層させ
てコンデンサ素子Cを形成すると共に、内部電極10
a〜10fを順次互い違いに別の外部電極12,13と
電気的に接続させて外部電極12,13をセラミック素
子Cの両端部に設けることにより構成されている。
2. Description of the Related Art Generally, a multilayer ceramic capacitor is shown in FIG.
As shown by a plurality of opposed internal electrodes 10a to 10f
And with a dielectric layer 11a~11f by stacked multiple alternately to form the capacitor element C 1, the internal electrodes 10
a~10f sequentially staggered by another external electrodes 12 and 13 electrically connected to it is formed by providing the external electrodes 12 and 13 on both ends of the ceramic element C 1.

【0003】その積層セラミックコンデンサでは、内部
電極10a〜10fの面積が広く、また、誘電体層11
a〜11fの厚みが薄ければ薄い程、大容量のものが得
られる。然し、誘電体層11a〜11fが薄いものを高
圧用として使用すると、電極端部における電界の集中に
より絶縁破壊を生ずる虞れがある。
In the multilayer ceramic capacitor, the area of the internal electrodes 10a to 10f is large and the dielectric layers 11a to 10f are large.
The smaller the thickness of a to 11f, the larger the capacity. However, when a thin dielectric layer 11a to 11f is used for high voltage, dielectric breakdown may occur due to concentration of an electric field at an electrode end.

【0004】その耐高圧化を図るには相対向する電圧相
互の距離dを大きくすればよいが、コンデンサ素子C
の表面に最も近い内部電極10a,10eの極性がラ
ンドパターンの極性と逆の場合には表面放電が生じ易
い。これは極性をコンデンサ素子Cに表示することで
避けられるが、部品装着時等の取扱いが面倒なものにな
る。
[0004] may be increased the distance d 1 of the voltage mutual opposed to achieve the high voltage, but the capacitor element C
If the polarities of the internal electrodes 10a and 10e closest to the surface of the first pattern are opposite to the polarities of the land patterns, surface discharge is likely to occur. This is avoided by displaying polarity capacitor element C 1, handling of time of component mounting is cumbersome.

【0005】それに代えて、コンデンサ素子Cの表面
に最も近い内部電極10a,10fとコンデンサ素子C
の表面との距離dを大きくしてもよいが、これでは
小型化に対応できなくなる。
[0005] Alternatively, the closest internal electrode 10a on the surface of the capacitor element C 1, 10f and the capacitor element C
May increase the distance d 2 between the first surface, it can not be correspond to the size reduction in this.

【0006】その課題を解決するため、図9で示すよう
に所定の間隙Gを内端側に隔て相平行する対の電極
で、外部電極20,21と電気的に個別に接続する複数
の内部電極22a,22b〜25a,25bと、外部電
極20,21と電気的に接続させないで内部電極22
a,22b〜25a,25bの内端側と相対向する内部
電極26a〜26cと、誘電体層27a〜27hとを複
数交互に複数積層させてコンデンサ素子Cを形成する
積層セラミックコンデンサが提案されている(実開昭5
4−5755号)。
[0006] Therefore the problem to solve, by a pair of electrodes parallel spaced phase inner end a predetermined gap G 3 as shown in Figure 9, a plurality of connecting external electrodes 20 and 21 electrically separate The internal electrodes 22a, 22b to 25a, 25b and the internal electrodes 22 without being electrically connected to the external electrodes 20, 21.
a, 22b~25a, the internal electrode 26a~26c which faces the inner end of 25b, and a dielectric layer 27a~27h by stacked multiple alternately is proposed laminated ceramic capacitors to form a capacitor element C 2 (Shinkai Kaisho 5
No. 4-5755).

【0007】その積層セラミックコンデンサでは、電圧
が直列に接続された容量により分担されることから高圧
に耐えられるが、図8で示す構成のものと同等の容量を
得るには内部電極を数的に二倍以上形成しなければなら
ない。
The multilayer ceramic capacitor can withstand a high voltage because the voltage is shared by the capacitors connected in series. However, in order to obtain a capacitance equivalent to that of the configuration shown in FIG. Must be formed more than twice.

【0008】その他に、図10で示すように複数の相対
向する内部電極30a〜30eと、所定の間隙Gを内
端側に隔て相平行する対の電極で、内部電極30a〜3
0eの最外層に位置する表面放電制御用の補助電極31
a,31b、32a,32bと、誘電体層33a〜33
hとを複数交互に複数積層させてコンデンサ素子C
形成すると共に、各電極を別の外部電極34,35と電
気的に接続する積層セラミックコンデンサが知られてい
る(発明協会公開技報:公枝番号90−18959)。
[0008] In addition, an internal electrode 30a~30e and, pairs of parallel spaced phase inner end a predetermined gap G 4 electrode a plurality of opposed, as shown in Figure 10, the internal electrodes 30a~3
Auxiliary electrode 31 for controlling surface discharge located at the outermost layer
a, 31b, 32a, 32b and dielectric layers 33a-33
and h into a plurality alternately stacking a plurality to form a capacitor element C 3, each electrode is different multilayer ceramic capacitor to external electrodes 34 and 35 electrically connected is known (Journal of Technical Disclosure: Branch number 90-18959).

【0009】その積層セラミックコンデンサでは、表面
放電制御用の補助電極31a,31b、32a,32b
を設けることから、表面の放電を抑制できても、側面の
放電を抑制することができない。
In the multilayer ceramic capacitor, auxiliary electrodes 31a, 31b, 32a, 32b for controlling surface discharge are provided.
However, even if the surface discharge can be suppressed, the side discharge cannot be suppressed.

【0010】[0010]

【発明が解決しようとする課題】本発明は、表面の放電
と共に、側面の放電も抑制できて小型で高容量,高耐圧
なものに構成可能な積層セラミックコンデンサを提供す
ることを目的とする。
SUMMARY OF THE INVENTION An object of the present invention is to provide a multilayer ceramic capacitor which can suppress a discharge on a side surface as well as a discharge on a surface, and can be formed into a small, high-capacity, high-withstand voltage capacitor.

【0011】[0011]

【課題を解決するための手段】本発明の請求項1に係る
積層セラミックコンデンサにおいては、複数の相対向す
る内部電極と誘電体層とを複数交互に複数積層させてコ
ンデンサ素子を形成すると共に、内部電極を順次互い違
いに別の外部電極と電気的に接続させて外部電極をセラ
ミック素子の両端部に設ける基本構造を有し、所定の間
隙を内端側に隔て相平行する対の電極で、内部電極の最
外層に位置する表面放電制御用の補助電極と、内部電極
並びに表面放電制御用の補助電極よりも外寄りに対単位
で両側に位置する側面放電制御用の補助電極とを付加
し、その各放電制御用の補助電極を対毎に別の外部電極
と電気的に接続することにより構成されている。
In a multilayer ceramic capacitor according to a first aspect of the present invention, a plurality of internal electrodes and a plurality of dielectric layers facing each other are alternately laminated to form a capacitor element. It has a basic structure in which the internal electrodes are sequentially and alternately electrically connected to another external electrode and the external electrodes are provided at both ends of the ceramic element, and a pair of electrodes that are parallel to each other with a predetermined gap on the inner end side, An auxiliary electrode for surface discharge control located on the outermost layer of the internal electrode, and auxiliary electrodes for side discharge control located on both sides in pairs outside of the internal electrode and the auxiliary electrode for surface discharge control are added. Each of the auxiliary electrodes for controlling discharge is electrically connected to another external electrode for each pair.

【0012】本発明の請求項2に係る積層セラミックコ
ンデンサにおいては、側面放電制御用の補助電極を少な
くとも内部電極に対応させて設けることにより構成され
ている。
In the multilayer ceramic capacitor according to a second aspect of the present invention, the auxiliary electrode for controlling side discharge is provided at least in correspondence with the internal electrode.

【0013】本発明の請求項3に係る積層セラミックコ
ンデンサにおいては、側面放電制御用の補助電極を内部
電極並びに表面制御用の補助電極と対応させて設けるこ
とにより構成されている。
In the multilayer ceramic capacitor according to a third aspect of the present invention, the auxiliary electrode for controlling side discharge is provided in correspondence with the internal electrode and the auxiliary electrode for controlling the surface.

【0014】本発明の請求項4に係る積層セラミックコ
ンデンサにおいては、側面放電制御用の補助電極を各電
極毎に少なくとも二層ずつ対応させて設けることにより
構成されている。
In the multilayer ceramic capacitor according to a fourth aspect of the present invention, an auxiliary electrode for controlling side discharge is provided for each electrode in at least two layers.

【0015】本発明の請求項5に係る積層セラミックコ
ンデンサにおいては、側面放電制御用の補助電極とのみ
積層した誘電体層を付加することにより構成されてい
る。
The multilayer ceramic capacitor according to claim 5 of the present invention is constituted by adding a dielectric layer laminated only with an auxiliary electrode for controlling side discharge.

【0016】[0016]

【発明の実施の形態】以下、添付図面を参照して説明す
ると、図1a,図1bは本発明に係る積層セラミックコ
ンデンサの基本的な実施の形態を示すものであり、それ
は複数の相対向する内部電極1a〜1eと誘電体層2a
〜2eとを複数交互に複数積層させてコンデンサ素子C
を形成すると共に、内部電極1a〜1eを順次互い違い
に別の外部電極3,4と電気的に接続させて外部電極
3,4をセラミック素子Cの両端部に設ける基本構造を
有する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to the accompanying drawings, FIGS. 1A and 1B show a basic embodiment of a multilayer ceramic capacitor according to the present invention. Internal electrodes 1a-1e and dielectric layer 2a
To 2e are alternately laminated in plural to form a capacitor element C
Is formed, and the internal electrodes 1a to 1e are sequentially and alternately electrically connected to other external electrodes 3 and 4, so that the external electrodes 3 and 4 are provided at both ends of the ceramic element C.

【0017】誘電体層2a〜2eは誘電体シートでな
り、内部電極1a〜1eはニッケル等の導電性ペースト
を誘電体シートの表面に印刷してなり、この導電性ペー
ストを印刷した誘電体シートを複数積層し焼成処理する
ことにより、内部電極1a〜1eと誘電体層2a〜2e
とが交互に位置するコンデンサ素子Cとして構成されて
いる。
The dielectric layers 2a to 2e are dielectric sheets. The internal electrodes 1a to 1e are formed by printing a conductive paste such as nickel on the surface of the dielectric sheet. Are laminated and fired, whereby the internal electrodes 1a to 1e and the dielectric layers 2a to 2e are formed.
Are alternately arranged as capacitor elements C.

【0018】外部電極3,4は銅等の導電性ペーストを
塗布焼き付けて下地電極とし、ニッケルの電解メッキ膜
並びにニッケル,錫またはその合金の電解メッキ膜を積
層被着することにより形成されている。
The external electrodes 3 and 4 are formed by applying and baking a conductive paste such as copper as a base electrode, and depositing a nickel electrolytic plating film and an electrolytic plating film of nickel, tin or an alloy thereof. .

【0019】その基本構成に加えて、図1aで示すよう
に所定の間隙Gを内端側に隔て相平行する対の電極
で、内部電極1a〜1eの最外層に位置する表面放電制
御用の補助電極5a,5b、6a,6bが誘電体層2f
〜2hと積層させて設けられている。
[0019] In addition to its basic structure, the electrode pairs of parallel inner end in spaced phase a predetermined gap G 1 as shown in FIG. 1a, a surface discharge control located on the outermost layer of the internal electrode 1a~1e Auxiliary electrodes 5a, 5b, 6a, 6b are
To 2h.

【0020】その表面放電制御用の補助電極5a,5
b、6a,6bと共に、図1bで示すように所定の間隙
を内端側に隔て相平行する対の電極で、内部電極1
a,1b並びに表面放電制御用の補助電極(図示せず)よ
りも外寄りに対単位で両側に位置する側面放電制御用の
補助電極7a,7b、8a,8bが誘電体層2aと積層
させて設けられている。
Auxiliary electrodes 5a, 5 for controlling the surface discharge
b, 6a, along with 6b, the electrode pairs of parallel inner end in spaced phase a predetermined gap G 2 as shown in 1b, the internal electrodes 1
a, 1b and side discharge control auxiliary electrodes 7a, 7b, 8a, 8b located on both sides in pairs outside of the surface discharge control auxiliary electrodes (not shown) are laminated on the dielectric layer 2a. It is provided.

【0021】その側面放電制御用の補助電極7a,7
b、8a,8bは内部電極1a〜1eと同じ誘電体層2
aの面上に設けたものであり、表面放電制御用の補助電
極5a,5b、6a,6bも含めて、上述した内部電極
1a〜1eと同様にニッケル等の導電性ペーストを誘電
体シートに印刷することにより形成されている。また、
これら各電極を形成した誘電体シートを所定層に積層す
ることによりコンデンサ素子Cとして形成されている。
Auxiliary electrodes 7a, 7 for controlling side discharge
b, 8a and 8b are the same dielectric layers 2 as the internal electrodes 1a to 1e.
a, and a conductive paste such as nickel or the like, including the auxiliary electrodes 5a, 5b, 6a, and 6b for controlling surface discharge, is formed on the dielectric sheet in the same manner as the internal electrodes 1a to 1e described above. It is formed by printing. Also,
A capacitor element C is formed by laminating a dielectric sheet on which these electrodes are formed in a predetermined layer.

【0022】そのコンデンサ素子Cでは、図2で示すよ
うに側面放電制御用の補助電極7a、7c〜7f、8
a、8c〜8f(各対の片側のみ図示)が少なくとも内部
電極1a〜1eと対応させて設けられている。また、図
1a,図1bで示すように表面放電制御用の補助電極5
a,5b、6a,6bと、側面放電制御用の補助電極7
a〜7f、8a〜8fとは各対毎に外部電極3,4と個
別に電気的に接続されている。
In the capacitor element C, as shown in FIG. 2, auxiliary electrodes 7a, 7c to 7f, 8f for controlling side discharge.
a, 8c to 8f (only one side of each pair is shown) are provided corresponding to at least the internal electrodes 1a to 1e. Further, as shown in FIGS. 1A and 1B, an auxiliary electrode 5 for controlling surface discharge is provided.
a, 5b, 6a, 6b and auxiliary electrodes 7 for controlling side discharge
Each of the pairs a to 7f and 8a to 8f is electrically connected to the external electrodes 3 and 4 individually.

【0023】このように構成する積層セラミックコンデ
ンサでは、分布静電容量を表面放電制御用の補助電極5
a,5b、6a,6bによるばかりでなく、側面放電制
御用の補助電極7a〜7f、8a〜8fでも低下させら
れる。そのため、内部電極1a〜1eと誘電体層2a〜
2eとを複数交互に複数積層する基本構造から小型で高
容量なものに構成できると共に、内部電極1a〜1eか
ら生ずる放電を抑制できて高耐圧のものにも構成でき
る。
In the multilayer ceramic capacitor configured as described above, the distributed capacitance is controlled by the auxiliary electrode 5 for controlling surface discharge.
It can be reduced not only by a, 5b, 6a and 6b, but also by auxiliary electrodes 7a to 7f and 8a to 8f for side discharge control. Therefore, the internal electrodes 1a to 1e and the dielectric layers 2a to 2e
2e and a basic structure in which a plurality of 2e are alternately stacked, a small-sized and high-capacity one can be configured, and a discharge generated from the internal electrodes 1a to 1e can be suppressed, so that a high-voltage one can be configured.

【0024】その積層セラミックコンデンサの放電耐圧
を測定したところ、図3のグラフで示す通り、図9の従
来品Aでは1500〜2000Vであり、図10の従来
品Bでは2500〜3000Vであったのに対し、本発
明品では3500〜4000Vと極めて高い耐放電電圧
を示した。
When the discharge withstand voltage of the multilayer ceramic capacitor was measured, as shown in the graph of FIG. 3, it was 1500 to 2000 V for the conventional product A of FIG. 9 and 2500 to 3000 V for the conventional product B of FIG. In contrast, the product of the present invention exhibited an extremely high withstand voltage of 3500 to 4000 V.

【0025】側面放電制御用の補助電極は内部電極1a
〜1eと対応するものに加えて、図4で示すように表面
放電制御用の補助電極5a,5bと対応するもの7h,
7i、8h,8iとして表面放電制御用の補助電極5
a,5bと同じ誘電体層2iの面上に設けるようにでき
る。
The auxiliary electrode for controlling side discharge is the internal electrode 1a.
In addition to those corresponding to .about.1e, those corresponding to auxiliary electrodes 5a and 5b for surface discharge control as shown in FIG.
7i, 8h, 8i, auxiliary electrodes 5 for controlling surface discharge
a and 5b can be provided on the same surface of the dielectric layer 2i.

【0026】その側面放電制御用の補助電極7h,7
i、8h,8iを表面放電制御用の補助電極5a,5b
と対応させて設けることから、側面放電をより効果的に
抑制することができる。
Auxiliary electrodes 7h, 7 for controlling side discharge
i, 8h and 8i are auxiliary electrodes 5a and 5b for controlling surface discharge.
Therefore, the side discharge can be more effectively suppressed.

【0027】また、図5で示すように側面放電制御用の
補助電極7j,7k、8j,8kのみを独自の誘電体層
2jの面上に設けるようにもできる。
As shown in FIG. 5, only the auxiliary electrodes 7j, 7k, 8j, 8k for controlling the side discharge can be provided on the surface of the dielectric layer 2j.

【0028】その側面放電制御用の補助電極は、内部電
極並びに表面放電制御用の補助電極と別の誘電体層の面
上に設けるものとして、図6で示すように内部電極1a
〜1e,表面放電制御用の補助電極5a,6aと異なる
層間に積層するようにできる。
The auxiliary electrode for controlling the lateral discharge is provided on the surface of the dielectric layer different from the internal electrode and the auxiliary electrode for controlling the surface discharge, and as shown in FIG.
1e, the auxiliary electrodes 5a and 6a for controlling surface discharge can be laminated between different layers.

【0029】その側面放電制御用の補助電極7h,7
j、8h,8jは、表面放電制御用の補助電極5a,6
aより外側に位置させてコンデンサ素子Cの表面側に近
い層間に積層するようにできる。これにより、更に、電
極端部における電界の集中による絶縁破壊を効果的に防
ぐことができる。
Auxiliary electrodes 7h, 7 for controlling side discharge
j, 8h and 8j are auxiliary electrodes 5a and 6 for controlling surface discharge.
The capacitor element C can be stacked outside the surface of the capacitor element C near the surface side. This can further effectively prevent dielectric breakdown due to concentration of an electric field at the electrode end.

【0030】側面放電制御用の補助電極は、図7で示す
ように内部電極1a〜1eに対応させて、図5で示す側
面放電制御用の補助電極7j,8jのみを設けた誘電体
層2jを少なくとも二層重ねで所定の層間に積層するよ
うにもできる。
As shown in FIG. 7, the auxiliary electrode for controlling the side discharge corresponds to the internal electrodes 1a to 1e, and the dielectric layer 2j provided with only the auxiliary electrodes 7j and 8j for controlling the side discharge shown in FIG. Can be laminated between predetermined layers in at least two layers.

【0031】この側面放電制御用の補助電極を設ける場
合には、側面放電を複数の側面放電制御用の補助電極7
j,8jで分担できることから、表面放電と共に、側面
放電をより効果的に抑制することができる。
When the side discharge control auxiliary electrode is provided, the side discharge is controlled by a plurality of side discharge control auxiliary electrodes 7.
Since j and 8j can be shared, the side discharge can be more effectively suppressed together with the surface discharge.

【0032】[0032]

【発明の効果】以上の如く、本発明に係る積層セラミッ
クコンデンサに依れば、内部電極と誘電体層とを複数交
互に複数積層する基本構造から小型で高容量なものに構
成できると共に、所定の間隙を内端側に隔て相平行する
対の電極で、内部電極の最外層に位置する表面放電制御
用の補助電極と、内部電極並びに表面放電制御用の補助
電極よりも外寄りに対単位で両側に位置する側面放電制
御用の補助電極とを付加することにより、分布静電容量
を表面放電制御用の補助電極によるばかりでなく、側面
放電制御用の補助電極でも低下できるため、内部電極か
ら生ずる放電を効果的に抑制できて高耐圧のものにも構
成することができる。
As described above, according to the multilayer ceramic capacitor of the present invention, the basic structure of alternately laminating a plurality of internal electrodes and dielectric layers can be reduced to a small size and high capacity. A pair of electrodes that are parallel to each other with the gap between them on the inner end side, and a pair of electrodes that are located on the outermost layer of the internal electrodes and that are more outward than the internal electrodes and the auxiliary electrodes for surface discharge control. By adding auxiliary electrodes for side discharge control located on both sides, the distributed capacitance can be reduced not only by the auxiliary electrodes for surface discharge control but also by the auxiliary electrodes for side discharge control. Can be effectively suppressed and a high breakdown voltage device can be configured.

【図面の簡単な説明】[Brief description of the drawings]

【図1a】本発明に係る積層セラミックコンデンサを側
断面で示す説明図である。
FIG. 1a is an explanatory view showing a multilayer ceramic capacitor according to the present invention in a side sectional view.

【図1b】図1aの積層セラミックコンデンサを構成す
る誘電体層の一例を平面で示す説明図である。
FIG. 1B is an explanatory view showing an example of a dielectric layer constituting the multilayer ceramic capacitor of FIG. 1A in a plane.

【図2】図1の積層セラミックコンデンサを横断面で示
す説明図である。
FIG. 2 is an explanatory view showing a cross section of the multilayer ceramic capacitor of FIG. 1;

【図3】本発明に係る積層セラミックコンデンサと従来
例との耐放電電圧を示すグラフである。
FIG. 3 is a graph showing discharge withstand voltages of a multilayer ceramic capacitor according to the present invention and a conventional example.

【図4】図1aの積層セラミックコンデンサを構成する
誘電体層の別の例を平面で示す説明図である。
FIG. 4 is an explanatory view showing another example of a dielectric layer constituting the multilayer ceramic capacitor of FIG. 1A in a plane.

【図5】図1aの積層セラミックコンデンサを構成する
誘電体層の更に別の例を平面で示す説明図である。
FIG. 5 is an explanatory view showing, in a plane, still another example of a dielectric layer included in the multilayer ceramic capacitor of FIG. 1A.

【図6】本発明の別の例に係る積層セラミックコンデン
サを横断面で示す説明図である。
FIG. 6 is an explanatory view showing a cross-sectional view of a multilayer ceramic capacitor according to another example of the present invention.

【図7】本発明の更に別の例に係るに積層セラミックコ
ンデンサを横断面で示す説明図である。
FIG. 7 is an explanatory diagram showing a cross-sectional view of a multilayer ceramic capacitor according to still another example of the present invention.

【図8】従来の一例に係る積層セラミックコンデンサを
側断面で示す説明図である。
FIG. 8 is an explanatory diagram showing a side view of a multilayer ceramic capacitor according to a conventional example.

【図9】従来の別の例に係る積層セラミックコンデンサ
を側断面で示す説明図である。
FIG. 9 is an explanatory view showing a side view of a multilayer ceramic capacitor according to another example of the related art.

【図10】従来の更に別の例に係る積層セラミックコン
デンサを側断面で示す説明図である。
FIG. 10 is an explanatory view showing a side cross section of a multilayer ceramic capacitor according to still another conventional example.

【符号の説明】[Explanation of symbols]

C コンデンサ素子 1a〜1e 内部電極 2a〜2h 誘電体層 3,4 外部電極 5a,5b 表面放電制御用の外部電極 6a,6b 表面放電制御用の外部電極 7a,7b 側面放電制御用の外部電極 8a,8b 側面放電制御用の外部電極 G,G 電極内端間の間隙C Capacitor element 1a-1e Internal electrode 2a-2h Dielectric layer 3,4 External electrode 5a, 5b External electrode 6a, 6b for surface discharge control External electrode 7a, 7b External electrode for side discharge control 8a , 8b Gap between the inner ends of the outer electrodes G 1 , G 2 for controlling the side discharge

フロントページの続き Fターム(参考) 5E001 AB03 AC07 AC09 AF00 AF06 AH01 AH09 AJ01 5E082 AA01 AB03 BC35 EE04 EE23 EE35 FG06 FG26 FG54 GG10 GG11 GG26 GG28 HH43 JJ03 JJ05 JJ12 JJ21 JJ23 KK01 MM24 PP08 Continued on the front page F-term (reference) 5E001 AB03 AC07 AC09 AF00 AF06 AH01 AH09 AJ01 5E082 AA01 AB03 BC35 EE04 EE23 EE35 FG06 FG26 FG54 GG10 GG11 GG26 GG28 HH43 JJ03 JJ05 JJ12 JJ21 JJ23 KK01 MM01

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】 相対向する複数の内部電極と誘電体層と
を複数交互に複数積層させてコンデンサ素子を形成する
と共に、内部電極を順次互い違いに別の外部電極と電気
的に接続させて外部電極をセラミック素子の両端部に設
ける基本構造を有し、 所定の間隙を内端側に隔て相平行する対の電極で、内部
電極の最外層に位置する表面放電制御用の補助電極と、
内部電極並びに表面放電制御用の補助電極よりも外寄り
に対単位で両側に位置する側面放電制御用の補助電極と
を付加し、その各放電制御用の補助電極を対毎に別の外
部電極と電気的に接続してなることを特徴とする積層セ
ラミックコンデンサ。
1. A capacitor element is formed by alternately laminating a plurality of opposing internal electrodes and a plurality of dielectric layers to form a capacitor element, and sequentially connecting the internal electrodes to another external electrode alternately and electrically. A basic structure in which electrodes are provided at both ends of the ceramic element, a pair of electrodes parallel to each other with a predetermined gap on the inner end side, and an auxiliary electrode for surface discharge control located on the outermost layer of the internal electrode;
An internal electrode and auxiliary electrodes for side surface discharge control located on both sides in pairs outside of the auxiliary electrode for surface discharge control are added, and each auxiliary electrode for discharge control is a separate external electrode for each pair. A multilayer ceramic capacitor characterized by being electrically connected to a multilayer ceramic capacitor.
【請求項2】 上記側面放電制御用の補助電極を少なく
とも内部電極に対応させて設けたことを特徴とする請求
項1に記載の積層セラミックコンデンサ。
2. The multilayer ceramic capacitor according to claim 1, wherein said side discharge control auxiliary electrode is provided corresponding to at least an internal electrode.
【請求項3】 上記側面放電制御用の補助電極を内部電
極並びに表面制御用の補助電極と対応させて設けたこと
を特徴とする請求項1に記載の積層セラミックコンデン
サ。
3. The multilayer ceramic capacitor according to claim 1, wherein the auxiliary electrode for controlling the side discharge is provided in correspondence with the internal electrode and the auxiliary electrode for controlling the surface.
【請求項4】 上記側面放電制御用の補助電極を各電極
毎に少なくとも二層ずつ対応させて設けたことを特徴と
する請求項2または3に記載の積層セラミックコンデン
サ。
4. The multilayer ceramic capacitor according to claim 2, wherein the auxiliary electrodes for controlling the side discharge are provided corresponding to at least two layers for each electrode.
【請求項5】 上記側面放電制御用の補助電極とのみ積
層する誘電体層を付加したことを特徴とする請求項2〜
4のいずれかに記載の積層セラミックコンデンサ。
5. A method according to claim 2, further comprising the step of adding a dielectric layer laminated only with the auxiliary electrode for controlling the side discharge.
5. The multilayer ceramic capacitor according to any one of 4.
JP30455998A 1998-10-26 1998-10-26 Multilayer ceramic chip capacitors Expired - Lifetime JP3463161B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP30455998A JP3463161B2 (en) 1998-10-26 1998-10-26 Multilayer ceramic chip capacitors

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP30455998A JP3463161B2 (en) 1998-10-26 1998-10-26 Multilayer ceramic chip capacitors

Publications (2)

Publication Number Publication Date
JP2000133545A true JP2000133545A (en) 2000-05-12
JP3463161B2 JP3463161B2 (en) 2003-11-05

Family

ID=17934460

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JP3463161B2 (en)

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