JP2000132391A - Branch prediction mechanism - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the prediction hit rate of a branch instruction with condition and to improve performance by making a plurality of branch history information contained in one line of a branch history buffer correspond to the addresses of the branch instructions with conditions. SOLUTION: A branch history buffer 804 storing the plurality of branch history information in one line is installed. In fetching an instruction (IF stage), one line containing the plurality of branch history information is read from the branch history buffer 804. When a plurality of branch instructions with conditions are contained in the fetched instruction, the respective branch instructions with conditions are branch-predicted by using the plurality of branch history information which are read. As a means for making the plurality of branch history information contained in one line of the branch history buffer 804 correspond to the addresses of the branch instructions with condition, an entry in the line of the branch history buffer 804 is made to correspond to an entry in the line of an instruction cache 802.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus, and more particularly to a microprocessor having a branch instruction predicting mechanism.

[0002]

2. Description of the Related Art At present, a microprocessor performs parallel processing in a microprocessor by introducing a pipeline system to increase the speed. FIG. 8 is a diagram for explaining the pipeline processing. Referring to FIG. 8, in the microprocessor, each instruction in a program is:
Instruction fetch (IF), instruction decode (ID), operation execution (EX), data read (MEM), write (W
In B), a series of processing ends. Each of these processes is performed in one cycle, and the unit of this process is called a “pipeline stage”.

In the T1 cycle, the instruction 1 is processed in the IF stage.

In the T2 cycle, the processing of the instruction 1 shifts to the ID stage, and the processing of the instruction 2 is performed in the IF stage.

In the T3 cycle, the instruction 1 is processed in the EX stage, the instruction 2 is processed in the ID stage, and the instruction 3 is processed in the IF stage. In the T5 cycle in which the processing of the instruction 1 ends, the processing of the instruction 5 has started.

[0006] As described above, the pipeline type microprocessor processes one instruction in several steps, and enables a plurality of instructions to be executed in parallel with overlapping without increasing resources.

FIG. 9 is a block diagram showing an example of a configuration of a pipeline type microprocessor. Referring to FIG. 9, this pipelined microprocessor includes a PC (program counter) register 201, an instruction cache unit 202, an instruction decode / register unit 203, an instruction execution unit 204, a data cache unit 205, an address adder 206, And pipeline registers 207, 208, 209, 210 for separating each pipeline stage.

The processing of an instruction is performed as follows.

The PC register 201 stores an address of an instruction in a program. The instruction specified by the PC register 201 is read by the instruction cache unit 202 (instruction fetch), and the pipeline register 207
To be stored.

The instruction decode / register unit 203 decodes the read instruction, reads the register value, and stores it in the pipeline register 208.

In the instruction execution unit 204, the operation of the decoded instruction is performed, and the result is stored in the pipeline register 209. The operation result is temporarily stored in the pipeline register 210 through the data line 211 for writing to the register file.

The data cache unit 205 writes and reads operation results to and from the data cache. The data read from the data cache is stored in the pipeline register 210,
2 is written to a register in the instruction decode / register unit 203.

The address adder 206 calculates the address of the next instruction to be executed, and stores it in the PC register 201 through the address line 213.

The pipeline registers 207, 208, 2
Since the data 09 and 210 hold the data used in the respective stages, the data is divided into the respective pipeline stages and the parallel processing can be performed in units of the pipeline stages.

In a normal program flow, the next instruction to be executed is the next instruction in the program order. Therefore, the address of the next instruction in the program order is calculated by the address adder 206 in the same cycle as the instruction fetch,
In the next cycle, the address of a new instruction can be stored in the PC register 201.

However, in the case of a branch instruction, the program flow is changed to an instruction at an address specified in the instruction. The addressing of the program flow changed by the branch instruction is usually performed in the instruction execution unit in the ID stage, and is therefore delayed by three cycles. Then, since the instruction at the specified address is fetched from the instruction cache again, this causes the pipeline to stop.

In a pipeline type processor, performance is improved by parallelizing instructions while filling the pipeline. In particular, in a recent microprocessor having an increased number of pipeline stages, a branch instruction causes Cannot be parallelized, and the penalty due to branching also increases.

Therefore, in order to reduce the branch penalty, the address specified by the branch instruction is calculated at an early stage of the pipeline, and the instruction at the specified address is fetched.

FIG. 10 shows an example of the configuration of a microprocessor capable of calculating an address specified by a branch instruction at an early stage of a pipeline and fetching an instruction at the specified address in order to reduce a branch penalty. FIG. Referring to FIG. 10, this conventional processor includes a PC register 301, an instruction cache unit 302, an instruction decode / register unit 303,
Instruction execution unit 304, data cache unit 3
05, address adder 306, pipeline register 3
07, 308, 309, 310 and a branch prediction unit 312.

The instruction specified by the PC register 301 is read by the instruction cache unit 302 and stored in the pipeline register 307.

The instruction decode / register unit 303 decodes an instruction. If the instruction stored in the pipeline register 307 is a branch instruction, the branch prediction unit 312 calculates an address specified by the branch instruction, stores the value in the PC register 301 through the address line 313, Fetch instructions.

By calculating the address specified by the branch instruction in the branch prediction unit 312, the next instruction can be fetched at an early stage of the pipeline, thereby reducing the penalty for stopping the pipeline due to the branch.

The branch instruction includes a non-branch instruction in which a branch is always taken, and a conditional branch instruction. The conditional branch instruction is
For example, whether a branch is taken or not taken is determined depending on conditions set by execution of another preceding instruction, such as branching when the zero flag is on.

When the conditional branch instruction is executed, the instruction execution unit 3
Since the program flow is not determined until the condition in step 04, the microprocessor shown in FIG. 10 cannot reduce the pipeline stop panalty due to the conditional branch instruction.

FIG. 11 is a block diagram showing a configuration of a conventional processor for reducing a stop penalty of a pipeline of a conditional branch instruction. Referring to FIG. 11, the microprocessor includes a PC register 401, an instruction cache unit 402, an instruction decode / register unit 403, an instruction execution unit 404, a data cache unit 405, an address adder 406, and pipeline registers 407, 408, and 409. , 410, a branch prediction unit 412, and a branch history buffer 414.

The branch history buffer 414 is a buffer for storing information on whether a condition in a conditional branch instruction is satisfied or not satisfied.

The instruction specified by the PC register 401 is read by the instruction cache unit 402 and stored in the pipeline register 407. At the same time, the branch history information at the address specified by the PC register 401 is read from the branch history buffer 414, and the pipeline register 407 is read.
To store.

Instruction decode / register unit 403
Performs decoding of the read instruction. When the instruction stored in the pipeline register 407 is a conditional branch instruction, the conditional branch instruction predicts whether or not the branch is taken based on the branch history information stored in the pipeline register 407. Is performed.

When it is predicted that the branch is taken, the address specified in the instruction is calculated by the branch prediction unit 412, and the value is transferred to the PC register 4 through the address line 413.
01, and a new instruction is fetched.

When it is predicted that the branch is not taken, the next instruction in the program order already fetched is transferred to the instruction decode / register unit 403.

The branch condition is determined by the instruction execution unit 40.
4 is performed. If the branch prediction is correct, the fetched instruction is executed according to the prediction.

If the branch prediction is wrong, the correct instruction address is stored in the PC register 401 through the address line 415, and the instruction in the program flow is fetched again.

After the condition is determined, the branch history information is updated.
The data is written to the branch history buffer 414 through the signal line 416.

FIG. 12 is a diagram showing an example of the configuration of a conventional information processing apparatus in which a plurality of microprocessors are connected in parallel. FIG. 12 shows a configuration in which two microprocessors are connected for simplicity. Although shown, it is not limited to two.

Referring to FIG. 12, there are provided two processors 502a and 502b connected to an external bus 501, each of which is provided with a PC register 503.
a, 503b, instruction cache units 504a, 50
4b, address adders 505a, 505b, branch history buffers 506a, 506b, instruction decode unit 50
7a, 507b, branch prediction units 508a, 508
b, instruction execution units 509a and 509b, and data cache units 510a and 510b.

Each processor 502a, 502b
Performs the same operation as the conventional processor shown in FIG.

The conditional branch instructions processed in the processors 502a and 502b are
History buffers 506a and 506 individually held in
b, the branch prediction units 508a, 508
The prediction is performed by b. After the branch condition is determined, the history information is updated in the instruction execution units 509a and 509b and written into the respective branch history buffers 506a and 506b.

The branch history information is held in each of the processors 502a and 502b.
It is not shared between 2a and 502b.

As an information processing device in which a plurality of processors are connected in parallel, research on an on-chip multiprocessor is also underway. As an on-chip multiprocessor which is a technology in which a plurality of processors are integrated on a single chip, for example, literatures (Transactions of the Institute of Electronics, Information and Communication Engineers, DI, Vol. J8)
1-DI, No. 6, May 1998; 71
8-727).

FIG. 13 shows one of the configurations taken up in the above-mentioned document. Referring to FIG. 13, this on-chip multiprocessor includes a pipeline register 601, an instruction cache unit 602, and two processors 603.
a, 603b.

The two processors 603a and 603b are
PC registers 604a, 604b, instruction decode / register units 607a, 607b, branch prediction units 608a, 608b, address adders 606a,
606b, instruction execution units 610a, 610b, data cache units 612a, 612b, and pipeline registers 605a, 605b, 609a, 609
b, 611a, 611b, 613a, 613b.

The pipeline register 601 and the instruction cache unit 602 include two processors 603a and 60
3b is used as a shared resource.

The pipeline register 601 selects and stores one of the addresses transferred from the processors 603a and 603b.

In the IF stage, an instruction sequence is read from the instruction cache 602 specified by the address stored in the pipeline register 601.

The read instruction sequence is stored in the pipeline registers 605a and 605b of the processor 603a / 603b that has requested the instruction sequence. At the same time, the contents of the pipeline register 601 are the PC registers 604a,
04b.

The pipeline register 601 specifies only one address, and access to the instruction cache 602 is limited to only once per cycle. That is, in a cycle in which one processor accesses the instruction cache, another processor cannot access the instruction cache.

Therefore, the two processors 603a and 603a
In order to supply a sufficient instruction to 03b, it is necessary to read an instruction of two cycles in one cycle from the instruction cache and store it in the pipeline registers 605a and 605b.

In the ID stage, the instruction sequence in the pipeline registers 605a and 605b is
The data is decoded by the register units 607a and 607b. If these instructions are branch instructions, branch prediction is performed by branch prediction units 608a and 608b.

These branch predictions are performed in the respective processors 603a and 603b, and the branch history information is not shared between the processors.

On the other hand, even in a single processor, the degree of parallelism has been increased by a superscalar technique, which is a technique for processing a plurality of instructions in a plurality of execution units in parallel by a single processor at the same time. Since the number of instructions processed in one step increases, the number of instructions fetched from the instruction cache in one cycle increases.

FIG. 14 is a diagram showing an example of a configuration of a conventional processor for realizing a super scalar. Referring to FIG. 14, the PC register 701, the instruction cache 70
2, address adder 703, branch history buffer 704,
It comprises an instruction decode / register unit 706, a branch prediction unit 707, an instruction execution unit 709, and a data cache unit 712.

The instruction execution unit 709 includes a plurality of operation units 709a and 709b, and is capable of executing a plurality of instructions in parallel.

A plurality of instructions specified by the PC register 701 are read from the instruction cache 702 and stored in the pipeline register 705. These instructions are decoded by the instruction decode / register unit 706, allocated to the operation units in the instruction execution unit 709, and executed.

The prediction of a conditional branch instruction is performed by the branch prediction unit 707. At the time of instruction fetch, one piece of branch history information corresponding to the PC register 701 is read from the branch history buffer 704 and stored in the pipeline register 705.

When a plurality of conditional branch instructions are included in a plurality of instructions stored in the pipeline register 705, prediction of all conditional branch instructions cannot be performed, and one conditional branch instruction cannot be predicted. Only instruction prediction is performed.

[0056]

In an information processing apparatus having an increased degree of parallelism, it is necessary to process a plurality of conditional branch instructions in one cycle. However, in the conventional information processing apparatus, when a plurality of conditional branch instructions cannot be predicted and a plurality of conditional branch instructions are included in a plurality of instructions stored in a pipeline register,
Only one conditional branch instruction is predicted. Also,
In order to improve the performance of the information processing apparatus, it is essential to increase the predicted hit rate of the conditional branch instruction.

In the conventional information processing apparatus, a branch history buffer is individually provided for each of a plurality of processors, the amount of hardware increases, and the amount of branch history information used by each processor to improve the prediction hit rate. However, there is a problem that the amount of hardware further increases when the number is increased.

Therefore, the present invention has been made in view of the above problems, and an object of the present invention is to provide an information processing apparatus that fetches a plurality of instructions from an instruction cache in one cycle. An object of the present invention is to provide an information processing apparatus which enables branch prediction of a plurality of conditional branch instructions included in the information processing apparatus.

Another object of the present invention is to provide an information processing apparatus which improves the prediction hit rate of a conditional branch instruction to improve the performance.

[0060]

According to a first aspect of the present invention, there is provided an information processing apparatus comprising: a branch history buffer configured to store a plurality of pieces of branch history information in one line; If a plurality of conditional branch instructions are read from a line fetched from the branch history buffer and the fetched instruction includes a plurality of conditional branch instructions, each of the conditional branch instructions is read out using the plurality of branch history information read from the branch history buffer. Perform branch prediction. In the present invention, a plurality of pieces of branch history information included in one line of the branch history buffer are associated with addresses of conditional branch instructions.

According to the present invention, in an information processing apparatus including a plurality of processors, a branch history buffer for storing a history of branch taken / not taken when a branch instruction is executed and an instruction address when the branch instruction is taken is provided by the plurality of processors. It is characterized by being shared between.

[0062]

Embodiments of the present invention will be described. Referring to FIG. 1, the information processing apparatus according to the present invention includes a branch history buffer (804) for storing a plurality of pieces of branch history information in one line. When one line including a plurality of pieces of branch history information is read from the branch history buffer and a plurality of conditional branch instructions are included in the fetched instruction, the plurality of pieces of branch history information read from the branch history buffer are used. , Branch prediction of each conditional branch instruction. The information stored in the branch history buffer includes (a) branch history information indicating whether a branch is taken / not taken when a branch instruction is executed, (b) branch history information and an address when a branch is taken, (c) branch history information, It includes at least one form of the address at the time of the branch and the instruction at the branch destination when the branch is taken.

In the embodiment of the present invention, a plurality of pieces of branch history information included in one line of the branch history buffer are associated with addresses of conditional branch instructions.

As a first means for associating a plurality of pieces of branch history information with addresses of conditional branch instructions, referring to FIG.
1) The entry in the line (902) of the branch history buffer (804) corresponds to the entry in (1). The first instruction in one line of the instruction cache (802) is associated with the first branch history information in one line of the branch history buffer (804), and the second instruction is associated with the second history information. This makes it possible to predict a plurality of conditional branch instructions using the corresponding branch history information.

As a second means of association, referring to FIG. 7, a branch history buffer (1402a, 1402b)
Are provided with tags (1403a, 1403b) each having a part of the address of the branch history information,
The address of the conditional branch instruction may be compared with a comparator.

According to the embodiment of the present invention, the history information of a conditional branch instruction can be used for prediction without being confused with the history information of a different instruction, and the prediction hit rate can be improved.

More specifically, the information processing apparatus of the present invention
In one preferred embodiment, referring to FIG. 1, an instruction cache unit (8) capable of simultaneously reading a plurality of instructions from the instruction cache in the same cycle.
02) and a branch history buffer (804) for storing a plurality of branch history information per line. In the IF stage, the instruction cache unit (802)
The instruction cache line is accessed in accordance with the address specified by the PC register (801), instructions of a plurality of entries are read from the line, stored in the instruction buffer (805a), and the branch history is stored in accordance with the address specified by the PC register (801). A line of the buffer (804) is accessed, a plurality of entries of branch history information of an instruction corresponding to an entry of the instruction cache (802) are read from the line, and stored in a history buffer (805c). Unit (80
In 6), the instruction stored in the instruction buffer (805a) is decoded, and it is determined whether or not the instruction is a conditional branch instruction. The determination result is sent to the branch prediction unit (807). When the instruction stored in the buffer is a conditional branch instruction, whether or not the conditional branch instruction is satisfied is predicted based on branch history information stored in a history buffer (805c). When it is predicted that the branch of the branch instruction is taken, the address of the branch destination is calculated, the calculation result is transferred to the PC register (801), and the result of the branch prediction is sent to the instruction execution unit (809). In the EX stage, an instruction execution unit (809) for performing the operation of each instruction and verifying the branch of the conditional branch instruction includes the branch prediction unit for the conditional branch instruction. If the branch prediction at the link (807) is correct, the branch history information is updated, the updated history information is written into the branch history buffer (804), and if the branch prediction is wrong, the address for fetching the correct instruction is stored. Is calculated and written into the PC register (801), the branch history information is updated, and the updated history information is written into the branch history buffer (804).

As described above, in the embodiment of the present invention, prediction of each branch instruction can be performed in the same cycle by referring to a plurality of pieces of branch history information in the same cycle.

Referring to FIG. 7, a branch history buffer (1402a, 1402b) composed of a plurality of blocks stores
Tag (1403) having a part of the address of branch history information
a, 1403b), at the IF stage, reads the history information and the tag address of the entry designated by the PC register (1401) from the branch history buffer (1402a, 1402b), and reads the history buffer (1406).
a, 1406b), and in the ID stage, the tag address and the address of the conditional branch instruction in the buffer (1405) are compared by a comparator (1407), and the branch history information of the matched block is output by a multiplexer ( 1408) and used for branch prediction of a conditional branch instruction in the branch prediction unit.

According to another preferred embodiment of the present invention, in an information processing apparatus having a plurality of processors, referring to FIG.
Is shared between processors. When the same conditional branch instruction is executed by a plurality of processors (1104a, 1104b), branch history information can be shared among the plurality of processors, and the prediction hit rate can be improved.

[0071]

Embodiments of the present invention will be described with reference to the drawings.

[Embodiment 1] FIG. 1 is a block diagram showing the configuration of an information processing apparatus according to an embodiment of the present invention. FIG.
, This information processing device is a super scalar type microprocessor capable of processing two instructions in one cycle, and includes an address register 801, an instruction cache unit 802, an address adder 803, a branch history buffer 804, Instruction decode / register unit 806, branch prediction unit 807, instruction execution unit 809, data cache unit 811, and pipeline registers 805a, 805b, 805c, 80
8, 810, and 812.

FIG. 2 is a block diagram showing the configuration of instruction cache unit 802, branch history buffer 804, and pipeline registers 805a and 805c shown in FIG.

Referring to FIG. 2, a pipeline register 805a is an instruction buffer for storing two instructions read at a time from instruction cache unit 802, and a pipeline register 805c is a branch history buffer 804
This is a history buffer that stores two entries of branch history information read out from.

FIG. 1 shows pipeline stage names separated by pipeline registers at the left end.

The operation of the first embodiment of the present invention will be described with reference to FIGS. PC register 801
Stores an address for accessing the instruction cache unit 802 and the branch prediction buffer 804. This address is transferred from the address adder 803, the branch prediction unit 807, and the instruction execution unit 809 through address lines 813, 814, and 815, respectively, and one is selected by the multiplexer.

When the selected address is the PC register 801
Is stored in The address is selected by the instruction execution unit 8
The address transferred from the address 09 is the highest priority, and is determined in the order of the address transferred from the branch prediction unit 807 and the result of the address adder 803.

In the IF stage, the instruction cache unit 802, the address adder 803, the branch history buffer 8
04 is performed.

The address adder 803 supplies the instruction cache unit 802 and the branch prediction buffer 804 in the next cycle.
Is added to the value of the address stored in the PC register 801 to obtain the value of the address two instructions ahead. The result is sent to the PC register 801 through the address line 813.

In the instruction cache unit 802, the PC
Two instructions starting from the address specified by the register 801 are read. The instruction cache line 901 is accessed according to the address specified by the PC register 801. From the line, for example, an instruction 901e at address 400
And two instructions 901f at address 404 are read.

The two instructions read are stored in the instruction buffer 805.
a. The instruction at address 400 is the instruction buffer 80
5a1, the instruction at address 404 is stored in the instruction buffer 805a2.
Is stored in

The branch history buffer 804 reads two entries of history information starting from the address specified by the PC register 801. Line 90 of the branch prediction buffer 804 according to the address specified by the PC register 801
Access 2 From this line, branch history information 902e of the instruction at address 400 and branch history information 902f of the instruction at address 404 are read.

As described above, the entry in the instruction cache and the entry in the branch history buffer 804 are always associated with each other.

The read branch history information is stored in the history buffer 805c. The branch history information at address 400 in the two entries is stored in the history buffer 805c1 as 404.
The branch history information of the address is stored in the history buffer 805c2.

The branch history information stored in the history buffer always corresponds to the instruction stored in the instruction buffer 805a. The history buffer 805c1 is branch history information of the instruction buffer 805a1, and the history buffer 805c2 is branch history information of the instruction buffer 805a2.

In the ID stage, processing in the instruction decode / register unit 806 and the branch prediction unit 807 is performed.

The instruction decode / register unit 806 decodes the instruction stored in the instruction buffer 805a and reads data from the register.

By decoding the instruction, the instruction buffer 80
It is determined whether the instruction stored in 5a is a conditional branch instruction. The determination result is sent to the branch prediction unit 807 via the signal line 816.

When the instruction stored in the instruction buffer 805a is a conditional branch instruction, the branch prediction unit 807 predicts whether or not the conditional branch instruction is taken.

If the branch of the conditional branch instruction is predicted to be taken, the branch destination address is calculated, and the result is transferred to the PC register 801 through the address line 814.
No action is taken if it is predicted not to hold.

The branch is predicted by the history buffer 805c.
This is performed based on the branch history information stored in. Further, the address of the branch destination instruction is obtained by adding the offset value in the conditional branch instruction to the address value of the conditional branch instruction. The result of the branch prediction is sent to the instruction execution unit 809 via a signal line 817.

In the EX stage, the instruction execution unit 80
The process is performed at 9. The instruction execution unit 809 performs the operation of each instruction and the prediction verification of the conditional branch instruction. Also, the branch history information is updated. If the branch prediction is correct, the branch history information is updated, and the updated history information is written to the branch history buffer 804 via the signal line 818. If the branch prediction is wrong, the correct address is calculated to fetch the correct instruction and written to the PC register 801 through the address line 815. Further, the branch history information is updated, and the updated history information is written to the branch history buffer 804 via the signal line 818.

In the MEM stage, processing is performed in the data cache unit 811. The data cache unit 811 reads and writes data.

In the WB stage, data stored in the pipeline register 812 is written to a register in the instruction decode / register unit 806 via a data line 819.

FIG. 3 is a diagram showing a program to be executed and instructions processed in each stage in a table format for each cycle. In FIG. 3, alu is an operation instruction, and br is a conditional branch instruction. “Br, 100” is an instruction that branches to an address obtained by adding 100 to the instruction address if the condition is satisfied. (NT) and (T) added to the end of the branch instruction represent whether or not a conditional branch instruction is taken, (T) represents that a branch is taken, and (N)
T) indicates that the branch is not taken.

These (branch taken / not taken) are
This is the result of the branch that is known after the condition is determined, and may be different from that at the time of branch prediction based on information in the branch history buffer 804.

Referring to FIG. 1 and FIG. 3, when the address 400 is set in the PC register 801 in the T1 cycle, two instructions starting from address 400 from the instruction cache in the instruction cache unit 802 (40
(Addresses 0 and 404) are read out and the instruction buffer 80 is read.
5a.

The conditional branch instruction at address 400 is 805a1
The conditional branch instruction at address 404 is stored in the instruction buffer 805.
a2. At the same time, two entries of history information starting from address 400 specified by the PC register 801 are read from the branch history buffer 804 and stored in the history buffer 805c. History buffer 805c1
The history information of “not established” is stored in the history buffer 805.
The history information of “established” is stored in c2. That is, 40
The history information at address 0 is “not established”, and the history information at address 404 is “established”.

The address adder 803 adds 8 to the value 400 of the PC register 801 to obtain the value of address 408. The result is transferred to the PC register 801.

Next, the operation of the ID stage in the T2 cycle will be described.

The instruction decode / register unit 806 stores addresses 400 and 4 stored in the instruction buffer 805a.
Decoding of two instructions at address 04 is performed, and it is found that the instruction is a conditional branch instruction. At the same time, branch prediction unit 807
Predicts a conditional branch instruction. Branch prediction is performed based on branch history information stored in the history buffer 805c.

The conditional branch instruction at address 400 is "not taken"
Is predicted. Since the conditional branch instruction is not taken, the program flow is not changed.

The conditional branch instruction at address 404 is predicted to be "taken". Since the conditional branch instruction is satisfied, the program flow branches to the instruction at the address 504, which is the address 100 specified in the instruction. The calculated address 504 is stored in the PC register 801 through the address line 814.

In the IF stage, instruction fetches at addresses 408 and 412 are performed. However, the fetched instruction is canceled because the conditional branch instruction at address 404 is predicted to be “taken”.

Next, the operation of the EX stage in the T3 cycle will be described. 4 in the instruction execution unit 809
Prediction verification of conditional branch instructions at addresses 00 and 404 is performed. The branch of the conditional branch instruction at address 400 is "not taken" and the program flow is not changed because the prediction is correct. The branch of the conditional branch instruction at address 404 is "taken", and the prediction was correct. In this case, the branch history information is updated and written to the branch history buffer 804 via the signal line 818.

In the IF stage, two instructions are fetched starting from the address 504 predicted in the T3 cycle.

In the T4 cycle, addresses 400 and 40
The conditional branch instruction at address 4 is processed in the MEM stage.

In the IF stage, the PC register 801 stores the address 512 calculated by the instruction execution unit 809 in the T3 cycle. Two instructions at addresses 512 and 516 are stored in the instruction cache unit 80.
2 is read. 504 and 5 in T4 cycle
Two instructions at address 08 are decoded in the ID stage.

In this embodiment, the history information of a plurality of conditional branch instructions is stored in one line of the branch history buffer 804 corresponding to one line of the instruction cache, and the plurality of pieces of history information are read out at the time of instruction fetch. The reference makes it possible to predict a plurality of conditional branch instructions which cannot be performed by the conventional method.

[Embodiment 2] A second embodiment of the present invention will be described. FIG. 4 is a block diagram showing the configuration of the second exemplary embodiment of the present invention. Referring to FIG. 4, a second embodiment of the present invention is shown.
The embodiment includes a pipeline register 1101, an instruction cache 1102, a branch history buffer 1103, and processors 1104a and 1104b. Each of the processors 1104a and 1104b is a super scalar type microprocessor, and can process two instructions in one cycle.

These instruction cache units 1102
Access to the branch history buffer 1103 is a common address specified by the pipeline register 1101, as in the first embodiment.

The instruction cache unit 1102 and the branch history buffer 1103 are resources shared by two processors, and the pipeline register 1101 specifies only one address, as in the conventional processor shown in FIG. Therefore, one processor can execute the instruction cache unit 1102 and the branch history buffer 110
In the cycle accessing 3, the other processor cannot access these shared resources.

Since two super scalar processors that issue two instructions are connected in parallel, the instruction cache unit 1102 fetches four instructions from the instruction cache in one cycle and stores them in the instruction buffer 1106a or 1106b. .

As a result, each processor 1104
a) Increase the ability to supply instructions to 1104b.

The branch history information for four instructions is read from the branch history buffer 1103, and the history buffer 11
06a or 1106b.

The processors 1104 a and 1104 b
C registers 1105a and 1105b, instruction decode / register units 1108a and 1108b, branch prediction units 1109a and 1109b, and instruction execution unit 111
1a, 1111b, data cache unit 1113
a, 1113b, instruction buffers 1106a, 1106
b, history buffers 1107a and 1107b.

FIG. 5 shows the instruction cache unit 1 of FIG.
102, a branch prediction buffer 1103, and pipeline registers 1106a, 1106b, 1107a, 110
It is a block diagram which shows the structure of 7b.

Referring to FIG. 5, one line 1201 of instruction cache unit 1102 has entry 1201
a, 1201b, 1201c, 1201d, 1201
e, 1201f, and stores a total of eight instructions. One line of the branch history buffer 1103 stores 8 pieces of branch history information.
Entries 1202a, 1202b, 1202c, 120
2d, 1202e, and 1202f.

The instruction buffers 1106a and 1106b prepared for each processor can store four instructions, respectively, and the history buffers 1107a and 1107b
Can store 4-branch history information.

The operation of the second embodiment of the present invention will be described with reference to FIGS. The addresses are transferred from the processors 1104a and 1104b to the pipeline register 1101. Only one address selected by arbitration from these addresses is stored in the pipeline register 1101.

In the IF stage, the instruction cache 1102 and the branch history buffer 1103 are accessed by the address specified by the pipeline register 1101.

Since only one address is specified by pipeline register 1101, in each cycle,
Only one processor has instruction cache unit 11
02 is supplied with an instruction.

The four instructions read from the instruction cache unit 1102 are stored in the instruction buffer of the processor that has determined the address of the pipeline register 1101. Also, the branch history information of four entries read from the branch history buffer 1103 is stored in the history buffer of the same processor.

FIG. 6 shows a second embodiment of the present invention.
FIG. 6A is a diagram showing, in a table form, an execution program and processing in each cycle, and FIG.
6A shows the processing stages of the processor 2 (1104b).

The address of the address 400 determined by the processor 1 (1104a) is set in the pipeline register 1101. The instruction at address 400 is stored in the instruction cache 1201e in the instruction cache unit 1102.

In the T1 cycle, the instruction specified by the pipeline register 1101 causes the instruction cache to read four instructions (40 instructions starting with the instruction at address 400).
0, 404, 408, and 412) are stored in the instruction buffer 1106a of the processor 1 (1104a). From the branch history buffer 1103, four pieces of information starting from the branch history information of the instruction at the address 400 are read. And
History buffer 110 of processor 1 (1104a)
7a.

The instruction at address 400 stored in the instruction cache 1201e is stored in the instruction buffer 1106a1.
The instruction at address 404 stored in 1201f is stored in the instruction buffer 1106a2 and stored in the instruction buffer 1106a2.
The instruction at address 08 is sent to instruction buffer 1106a3,
The instruction at address 412 stored in 2h is read out to the instruction buffer 1106a4.

The branch history information at address 400 stored in 1202e of the branch history buffer 1103 is sent to the history buffer 1107a1, and the branch history information at address 404 stored at 1202f is sent to the history buffer 1107.
a2, the branch history information at address 404 stored in 1202g is sent to the history buffer 1107a3,
The branch history information at address 404 stored in h is read out to the history buffer 1107a4.

In the T2 cycle, the processor 1 (1
104a) holds the address 400 in the PC register 1105.

4 read to the instruction buffer 1106a
The instructions at addresses 00 and 404 are decoded. At the same time, branch prediction is performed based on the branch history information stored in the history buffer 1107a.

Here, the conditional branch instruction at address 400 is predicted as “not taken”, and the conditional branch instruction at address 404 is predicted as “taken”.

If the conditional branch instruction is "not taken", the program flow is not changed. Since the conditional branch instruction at address 404 was predicted to be "taken", the program flow proceeds to the 100th instruction specified in the instruction at address 404.
Branch to the instruction at address 504 at the address. In other words, the instructions at addresses 408 and 408 are canceled with the change in the program flow.

In the same T2 cycle, the pipeline register 1101 holds the address 384 determined by the processor 2. The four instructions starting with this address are read from the instruction cache 1102 to the instruction buffer 1106b of the processor 2 (1104b).

The branch history information is read from the branch history buffer 1103 to the history buffer 1107b.

In the T3 cycle, four instructions starting at address 504 are read from the instruction cache 1102 and stored in the instruction buffer 1106a of the processor 1 (1104a) according to the prediction of the conditional branch instruction at address 404.

In the EX stage, addresses 400 and 404 are processed in the instruction execution unit 1111a.
The conditional branch instruction at address 400 is "not taken" and the prediction is correct, but the conditional branch instruction at address 404 is "not taken" and the verification shows that the prediction is wrong.

Therefore, the two instructions at addresses 504 and 508 read in the IF stage of this cycle are:
Canceled. The branch history information at addresses 400 and 404 is updated. That is, the history information of “not established” is written to the branch history buffer 1103 for both instructions.

On the other hand, in the processor 2 (1104a),
In the T3 cycle, the instructions at addresses 384 and 388 are processed in the ID stage.

In cycle T4, processor 1 (1
In 104b), the instructions at addresses 400 and 404 are ME
Processed at M stage. Processor 2 (110
In the EX stage 4b), the instructions at addresses 384 and 388 are executed. In the ID stage, 392 and 39 are executed.
The instruction at the address 6 is decoded. In the IF stage, fetch of four instructions starting from address 400 is performed.

In cycle T5, processor 1 (1
In 104a), fetch of four instructions starting from address 408 is performed. On the other hand, the processor 2 (1104b) predicts conditional branch instructions at addresses 400 and 404. Based on the branch history information read into the history buffer, the program flow is executed without being changed, based on the history information of "not taken" at address 400 and "not taken" updated at address 404 in the T3 cycle.

As described above, in the second embodiment of the present invention, in an information processing apparatus having a plurality of processors, a branch history buffer is shared between processors, and branch history information of a plurality of instructions is read at a time. Because of this,
A plurality of branch instructions can be predicted, for example, in the same cycle.

When the same conditional branch instruction is executed by a plurality of processors, by sharing the history information among the plurality of processors, the prediction hit rate can be improved.

In comparison with the conventional branch history buffer individually provided for each processor, in the second embodiment of the present invention, the branch history buffer is used as a shared resource, and information which can be used by each processor without increasing the amount of hardware. It is possible to increase the amount.

[Embodiment 3] Next, a third embodiment of the present invention will be described. FIG. 7 is a block diagram showing a configuration of the third embodiment of the present invention, and shows a configuration of a branch history buffer configured by a two-way set associative system. Referring to FIG. 7, the branch history buffer includes two blocks 1402a and 1402b. Each block 1402a, 1402b has a tag buffer 1403a, 1403 having a part of the address of the branch history information.
b and buffers 1404a, 1404 storing branch history information.
404b. The buffer 1405 is for storing the address of the instruction when decoding the instruction.

History buffers 1406a and 1406b
Is a pipeline register for storing history information and tags read from the branch history buffers 1402a and 1402b. The tag information uses predetermined lower bits of the address, and is stored as additional information (tag) in each entry of the branch history buffer.

The comparator 1407 stores the tag information of the history buffers 1406a and 1406b and the buffer 140
Compare the value of 5.

The multiplexer 1408 selects the branch information read from the two blocks using the comparison result of the comparator 1407 as a selection control signal. Buffer 1
Reference numeral 405 stores the address of the branch instruction.

The operation of the third embodiment of the present invention will be described. Reading of the branch history buffers 1402a and 1402b is performed in the IF stage. The read information is stored in pipeline registers 1406a and 1406b, and in the ID stage, the address of the conditional branch instruction is compared with the tag information by the comparator 1407, and is used for predicting the conditional branch instruction. You.

At the IF stage, the branch history information of the conditional branch instruction is read from the branch history buffer simultaneously with the instruction fetch from the instruction cache.

The address of the instruction for performing the instruction fetch is P
It is stored in the C register 1401.

The branch history information and the tag of the entry specified by the PC register 1401 are stored in each of the blocks 1402a and 1402.
02b, and read from the history buffer 1406a,
1406b.

In the ID stage, if the instruction fetched from the instruction cache is a conditional branch instruction, a branch prediction unit (not shown) performs branch prediction.

The address of the buffer 1405 is compared with the tags 1406a and 1406b of the branch information of the history buffer by the comparator 1407. If the tags match, the branch history information of the matched block is selected by the multiplexer 1408. Used for predicting conditional branch instructions.

According to the third embodiment of the present invention, in an information processing apparatus that fetches a plurality of instructions in one cycle, a plurality of pieces of branch history information can be read from a branch history buffer in one cycle. Can be predicted for a plurality of conditional branch instructions.

Also, by having address information in the tag, the relationship between the branch history information and the branch instruction is clarified, so that the occurrence of a situation in which information of different branch instructions is used for prediction is prevented, and The prediction hit rate can be improved.

[0156]

As described above, according to the present invention, the following effects can be obtained.

A first effect of the present invention is that branch prediction of a plurality of conditional branch instructions can be performed, and the hit rate of branch prediction is improved, thereby improving processing performance. In an information processing device having an increased degree of parallelism, it is necessary to process a plurality of conditional branch instructions in one cycle. In a conventional information processing apparatus, a plurality of conditional branch instructions could not be predicted, but the present invention has solved this problem.

In order to improve the performance of the information processing apparatus, it is essential to increase the prediction hit rate of the conditional branch instruction. According to the present invention, since a plurality of conditional branch instructions can be predicted, unpredictable conditional branch instructions can be eliminated, and an improvement in prediction hit rate can be expected.

A second effect of the present invention is that, when the same conditional branch instruction is executed by a plurality of processors, a plurality of processors share a branch history buffer, thereby further improving the prediction hit ratio. It is possible.

A third effect of the present invention is that by sharing the branch history buffer, the amount of history information used by each processor can be increased without increasing the amount of hardware.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a first exemplary embodiment of the present invention.

FIG. 2 is a block diagram showing a detailed configuration of the first embodiment of the present invention. .

FIG. 3 is a diagram for explaining a branch prediction operation according to the first embodiment of the present invention, and is a diagram showing a program and instructions processed in each stage.

FIG. 4 is a block diagram showing a configuration of a second exemplary embodiment of the present invention.

FIG. 5 is a block diagram showing a detailed configuration of a second embodiment of the present invention. .

FIG. 6 is a diagram for explaining a branch prediction operation according to the second embodiment of the present invention, and is a diagram illustrating a program and instructions processed in each stage.

FIG. 7 is a block diagram showing a configuration of a third exemplary embodiment of the present invention.

FIG. 8 is a diagram for explaining the operation principle of pipeline processing.

FIG. 9 is a block diagram illustrating an example of a configuration of a pipelined microprocessor.

FIG. 10 is a block diagram illustrating an example of a configuration of a microprocessor having a branch prediction unit.

FIG. 11 is a block diagram illustrating an example of a configuration of a microprocessor having a branch history buffer.

FIG. 12 is a block diagram illustrating an example of a configuration of a conventional information processing device in which a plurality of processors are connected in parallel.

FIG. 13 is a block diagram showing an example of a configuration of a conventional information processing apparatus having a branch prediction mechanism and having a shared cache in an on-chip multiprocessor.

FIG. 14 is a block diagram illustrating an example of a configuration of a superscalar microprocessor.

[Description of sign]

 201 PC register 202 Instruction cache unit 203 Instruction decode / register unit 204 Instruction execution unit 205 Data cache unit 206 Address adder 207 Pipeline register 208 Pipeline register 209 Pipeline register 210 Pipeline register 211 Data line 212 Data line 213 Address line 301 PC register 302 Instruction cache unit 303 Instruction decode / register unit 304 Instruction execution unit 305 Data cache unit 306 Address adder 307 Pipeline register 308 Pipeline register 309 Pipeline register 310 Pipeline register 311 Address line 312 Branch prediction unit 313 Address Line 401 PC Regis 402 instruction cache unit 403 instruction decode / register unit 404 instruction execution unit 405 data cache unit 406 address adder 407 pipeline register 408 pipeline register 409 pipeline register 410 pipeline register 411 address line 412 branch prediction unit 413 address line 414 branch History buffer 415 Address line 416 Signal line 501 External bus 502a Processor a 502b Processor b 503a PC register 503b PC register 504a Instruction cache unit 504b Instruction cache unit 505a Address adder 505b Address adder 506a Branch history buffer 506b Branch history buffer 507a Instruction / Register unit 07b Instruction decode / register unit 508a Branch prediction unit 508b Branch prediction unit 509a Instruction execution unit 509b Instruction execution unit 510a Data cache unit 510b Data cache unit 511a Pipeline register 511b Pipeline register 512a Pipeline register 512b Pipeline register 513a Pipeline register 513b pipeline register 514a pipeline register 514b pipeline register 601 pipeline register 602 instruction cache unit 603a processor a 603b processor b 604a PC register 604b PC register 605a pipeline register 605b pipeline register 606a address adder 6 06b Address adder 607a Instruction decode / register unit 607b Instruction decode / register unit 608a Branch prediction unit 608b Branch prediction unit 609a Pipeline register 609b Pipeline register 610a Instruction execution unit 610b Instruction execution unit 611a Pipeline register 611b Pipeline register 612a Data Cache unit 612b Data cache unit 613a Pipeline register 613b Pipeline register 701 PC register 702 Instruction cache unit 703 Address adder 704 Branch history buffer 705 Pipeline register 706 Instruction decode / register unit 707 Branch prediction unit 708 Pipeline register 709 Instruction actual Unit 709a Operation unit 709b Operation unit 710 Pipeline register 711 Data cache unit 712 Pipeline register 801 PC register 802 Instruction cache unit 803 Address adder 804 Branch history buffer 805a Instruction buffer 805b Pipeline register 805c History buffer 806 Instruction decode / register unit 807 Branch prediction unit 808 Pipeline register 809 Instruction execution unit 810 Pipeline register 811 Data cache unit 812 Pipeline register 813 Address line 814 Address line 815 Address line 816 Signal line 817 Signal line 818 Signal line 819 Data line 901 Instruction cache line 902 Line in branch history buffer 110 1 Pipeline Register 1102 Instruction Cache Unit 1103 Branch History Buffer 1104a Processor a 1104b Processor b 1105a PC Register 1105b PC Register 1106a Instruction Buffer 1106b Instruction Buffer 1107a History Buffer 1107b History Buffer 1108a Instruction Decode / Register Unit 1108b Instruction Decode / register Unit 1108b Prediction unit 1109b branch prediction unit 1110a pipeline register 1110b pipeline register 1111a instruction execution unit 1111b instruction execution unit 1112a pipeline register 1112b pipeline register 1113a data cache unit 1113b data cache unit 11 14a Pipeline Register 1114b Pipeline Register 1201 Instruction Cache Line 1202 Branch History Buffer Line 1401 PC Register 1402a Branch History Buffer Block 1402b Branch History Buffer Block 1403a Tag Buffer 1403b Tag Buffer 1404a History Buffer 1404b History Buffer 1405 Address Buffer 1406a History buffer 1406b History buffer 1407 Comparator 1408 Multiplexer

Claims (19)

[Claims] An information processing apparatus for simultaneously reading a plurality of instructions from an instruction cache in the same cycle, wherein a plurality of branch instructions among the plurality of read instructions are referred to in a same cycle by a plurality of branch history information, respectively. An information processing apparatus comprising means for performing prediction of a branch instruction in the same cycle. 2. The information processing apparatus according to claim 1, further comprising a branch history buffer for storing branch history information of a plurality of branch instructions in one line. 3. A branch history buffer for storing a plurality of pieces of branch history information in one line corresponding to an instruction in a line of an instruction cache, wherein a plurality of branch instructions to be executed in the processor are predicted. 2. The information processing apparatus according to claim 1, wherein the information processing apparatus is capable of performing the following. 4. An information processing apparatus including a plurality of processors, wherein a means for predicting a branch instruction is shared among the plurality of processors. 5. A branch history buffer for storing a branch taken / not taken history at the time of execution of a branch instruction and an instruction address when a branch is taken is shared by the plurality of processors. 5. The information processing apparatus according to 4. 6. An information processing apparatus including a plurality of processors, comprising: an instruction cache unit capable of simultaneously reading a plurality of instructions from an instruction cache in the same cycle; An information processing apparatus comprising: means for referring to a plurality of pieces of branch history information in a cycle and predicting each instruction in the same cycle. 7. The information processing apparatus according to claim 4, wherein a branch history buffer for storing branch history information of a plurality of branch instructions in one line is shared by the plurality of processors. . 8. A processor according to claim 1, further comprising a branch history buffer for storing a plurality of pieces of branch history information in one line corresponding to instructions in a line of the instruction cache, wherein said branch history buffer is shared by said plurality of processors. 7. The information processing apparatus according to claim 4, wherein prediction of a plurality of branch instructions to be executed within the apparatus can be performed. 9. An information processing apparatus for simultaneously reading a plurality of instructions from an instruction cache in the same cycle, comprising: a branch history buffer in which one line stores branch history information of a plurality of branch instructions; A branch history buffer including one or more blocks having a tag having a part and a comparator for comparing the address of the tag of each block with the address of a conditional branch instruction; An information processing apparatus, wherein a plurality of conditional branch instructions in an instruction can be predicted. 10. An information processing apparatus including a plurality of processors, wherein a branch history buffer for storing branch history information of a plurality of branch instructions in one line, comprising a tag having a part of the address of the branch history information. A branch history buffer including one or a plurality of blocks and a comparator for comparing an address of the tag of each of the blocks and an address of a conditional branch instruction, wherein the plurality of processors share the branch history buffer; An information processing apparatus, wherein prediction of all branch instructions executed among the plurality of processors can be performed. 11. An information processing apparatus including a plurality of processors, comprising: a branch history buffer for storing a plurality of branch history information in one line corresponding to an instruction in a line of the instruction cache; An information processing apparatus, wherein a branch history buffer is shared, and all branch instructions executed in the plurality of processors can be predicted. 12. An information processing apparatus including a pipeline processor, an instruction cache unit capable of simultaneously reading a plurality of instructions from an instruction cache in the same cycle, and a branch history storing a plurality of pieces of branch history information per line. A buffer including a plurality of conditional branch instructions read out from the branch history buffer at the time of fetching an instruction from the instruction cache, wherein the fetched instruction includes a plurality of conditional branch instructions. An information processing apparatus configured to perform a branch prediction of each of the plurality of conditional branch instructions using a plurality of pieces of branch history information read from the branch history buffer. 13. A plurality of pieces of branch history information included in one line of the branch history buffer can be conditionally associated with an entry in the line of the instruction cache corresponding to an entry in the line of the branch history buffer. 13. The information processing apparatus according to claim 12, wherein the information is associated with a branch instruction address. 14. A branch history buffer comprising: a plurality of blocks each including a tag having a part of an address of branch history information;
2. A comparator for comparing an address of the tag in a line accessed for each block with an address of a conditional branch instruction.
2. The information processing apparatus according to item 2. 15. A multiplexer which selectively outputs branch history information included in a line of a block in which the address of a conditional branch instruction matches the address of a tag according to the comparison result of the branch instruction, and stores the branch history information in the branch instruction. The information processing apparatus according to claim 14, which is used for prediction. 16. An information processing apparatus provided with a plurality of processors of a pipeline system, wherein a plurality of processors share a branch history buffer for storing branch history information of a branch instruction, When a plurality of instructions are fetched from an instruction cache shared by a plurality of instructions, the branch history information of the plurality of instructions is read out from the branch history buffer at a time, thereby enabling the prediction of the plurality of conditional branch instructions. An information processing apparatus, wherein when a conditional branch instruction is executed by a plurality of processors, branch history information can be shared among the plurality of processors. 17. An information processing apparatus including a pipeline type processor, an instruction cache unit capable of simultaneously reading a plurality of instructions from an instruction cache in the same cycle, a branch history buffer storing a plurality of branch history information, In the instruction fetch (IF) stage, the instruction cache unit accesses a line of the instruction cache according to an address specified by a PC register, reads instructions of a plurality of entries from the line, and stores the instructions in an instruction buffer. Accessing a line of the branch history buffer according to an address specified by a PC register, reading a plurality of entries of branch history information of an instruction corresponding to an entry of the instruction cache from the line, storing the information in a history buffer, and decoding the instruction (ID) On stage In the instruction decoding unit, the instruction stored in the instruction buffer is decoded, and it is determined whether or not the instruction is a conditional branch instruction. The result of the determination is sent to the branch prediction unit. When the stored instruction is a conditional branch instruction, predicting whether or not the conditional branch instruction is taken based on the branch history information stored in the history buffer, If the branch is predicted to be taken, the branch destination address is calculated, the calculation result is transferred to the PC register, and the result of the branch prediction is sent to the instruction execution unit. In the instruction execution (EX) stage, In the instruction execution unit, if the branch prediction in the branch prediction unit for the conditional branch instruction is correct, the branch history information is updated and the branch The updated history information is written to the history buffer, and if the branch prediction is incorrect, the address is calculated to fetch the correct instruction and written to the PC register, and the branch history information is updated to update the updated history information. In the branch history buffer. 18. An information processing apparatus including a pipeline type processor, comprising: an instruction cache unit capable of simultaneously reading a plurality of instructions from an instruction cache in the same cycle; and a plurality of blocks, each block being included in one line. A branch history buffer having a tag having a part of the address of the branch history information.
The branch history buffer entry is accessed in accordance with the address specified by the register, the branch history information of the entry is read out together with the tag address and stored in the history buffer. In the ID stage, the tag address of the history buffer and the conditional branch are read. The address of the instruction is compared with a comparator, the branch history information of the matched block is selected by a multiplexer and sent to the branch prediction unit, and the branch prediction unit converts the branch history information to the conditional branch instruction. An information processing device for use in prediction. 19. The branch history buffer includes: (a) branch history information; (b) branch history information and an address at the time of branch establishment;
(C) at least one form of branch history information, an address when the branch is taken, and an instruction at a taken place when the branch is taken. An information processing apparatus according to claim 1.