JP2000125192A - Image synthesizing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To facilitate synthesis by controlling input timing and addressing to a memory and compositing and outputting image data such as a still picture and continuous images in which a vertical synchronizing signal is inputted asynchronously, a vertical scan frequency is different and a horizontal scan frequency is equal. SOLUTION: A line gate detecting device 16 detects the line gate marker of image data outputted from each memory, nullifies the address counter of the detected memory and stops horizontal image data display at the position. Also, when both 1st and 2nd or 3rd respective memories 9 and 10 or 15 detect it, the address counter is made effective again. A synthesis deciding device 17 compares image data outputted from the 1st memory 9 with a preliminarily set luminance level in every pixel, a D/A converter 12 convert the data in each pixel unit when it is equal to or more than a set value and converts the data of the 2nd or 3rd memory 10 or 15 when it is below the set value, and a synchronizing signal and a blank signal are superimposed on the data in the timing of an output of a timing controller 11 to be a composited image signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog RGB
(Red Green Blue) signal, a plurality of image data is input, and these are A / D (Analog)
After the digital signal is converted into a digital signal by g to Digital conversion, the digital signal is synthesized, and the synthesized image is converted into a digital signal (D / A).
The present invention relates to an image synthesizing apparatus of a system that performs tal to analog conversion and outputs an analog signal.

[0002]

2. Description of the Related Art FIG. 10 shows an example of a system configuration of a conventional image synthesizing apparatus, wherein 1 and 2 are an image generating apparatus, 3 is an image synthesizing apparatus, and 4 is an image display apparatus. Still images or continuous images output from the image generating apparatuses 1 and 2 have the same image data resolution, the same vertical scanning frequency and the same horizontal scanning frequency, and the horizontal synchronization signal and the vertical synchronization signal are synchronized. I have.

The inside of the image generating apparatus will be described in detail with reference to FIG. 1 generates still or continuous images,
The first image synthesizing device 2 that outputs as an analog RGB signal generates a still image or a continuous screen having the same vertical frequency and horizontal frequency as the image of the first image generating device 1, and outputs the same as an analog RGB signal. Reference numerals 2 and 5 denote synchronizing devices for synchronizing the respective vertical synchronizing signals with respect to the image data output from the first image synthesizing device 1 and the second image synthesizing device 2. First
The image data generated by the image generation device 1 of the first A /
The digital signal is A / D converted by the D converter 6 and output to the first memory 9 at a trigger (hereinafter referred to as a frame trigger) cycle for each screen generated by the synchronizer 5. The image data generated by the second image generation device 2 is A / D converted into a digital signal by the second A / D conversion device 7, and is output to the second memory 10 at a frame trigger period. The memory read / write controller 8 alternately switches the first memory 9 and the second memory 10 between the input state and the output state in the frame trigger cycle. D / A converter 12
Performs D / A conversion of the image data output from the first memory 9 or the second memory 10 into an analog image signal, and outputs the image data according to the timing input from the timing control device 11. The timing control device 11 generates the timing of the synchronization signal and the blank signal in the frame trigger cycle, and outputs the timing to the D / A converter 12.

[0004]

In a conventional image synthesizing apparatus, it is necessary to synchronize a vertical synchronizing signal of an input image signal. For this reason, there is a problem that it is not possible to cope with the case where the image data output from the image generating device is asynchronous.

Further, even when the vertical scanning frequency and the horizontal scanning frequency of the image data output from the image generating apparatus are equal to each other and the respective image data are synchronized, the image data having different resolutions is displayed on the same scale on the same scale. There was a problem that cannot be displayed.

The present invention has been made to solve such a problem, and an object of the present invention is to be able to easily synthesize images without being limited by input image data.

[0007]

An image synthesizing apparatus according to a first aspect of the present invention controls input / output timings and addresses to and from a memory, receives a vertical synchronization signal asynchronously, and has different horizontal scanning frequencies and equal horizontal scanning frequencies. Image data such as a still image or a continuous image is synthesized and output to an image display device.

[0008] An image synthesizing apparatus according to a second aspect of the present invention comprises:
In the asynchronous image synthesizing apparatus according to the first aspect,
By adding a memory, a vertical synchronization signal is asynchronously input, and image data such as a still image or a continuous image having different horizontal scanning frequencies and equal horizontal scanning frequencies can be synthesized and output to an image display device in real time. It was made.

In the image synthesizing apparatus according to the third aspect of the invention, the vertical synchronizing signal is input asynchronously by controlling the input / output timing to and the address to the memory, sampling the image data, and equalizing the resolution. Image data such as still images or continuous images having different frequencies, equal horizontal scanning frequencies, and different resolutions can be combined and output to an image display device on the same scale.

An image synthesizing apparatus according to a fourth aspect of the present invention provides
In the asynchronous image synthesizing device according to the third aspect,
By adding a memory, a vertical synchronizing signal is input asynchronously, and image data such as still images or continuous images having different horizontal scanning frequencies, equal horizontal scanning frequencies, and different resolutions are synthesized and output in real time at the same scale. It is something that can be done.

In the image synthesizing apparatus according to a fifth aspect of the present invention, the vertical synchronizing signal is asynchronously input by controlling the input / output timing and address to and from the memory, and by subjecting the image data to pixel enlargement and equalizing the resolution. Image data such as still images or continuous images having different horizontal scanning frequencies and the same horizontal scanning frequency and different resolutions can be combined and output to an image display device at the same scale.

Further, an image synthesizing apparatus according to a sixth aspect of the present invention comprises:
In the asynchronous image synthesizing apparatus according to the fifth aspect,
By adding a memory, a vertical synchronizing signal is asynchronously input, and image data such as still images or continuous images having the same vertical scanning frequency and horizontal scanning frequency and different resolutions are synthesized and output on the same scale in real time. Is made possible.

[0013]

Embodiment 1 FIG. 1 is a diagram showing a configuration of an asynchronous image synthesizing apparatus to which a line gate detecting apparatus according to Embodiment 1 of the present invention is added.
In the figure, 1 is a first image synthesizing device, 2 is a second image synthesizing device, 6 is a first A / D converter, and 7 is a second A / D.
A conversion device, 8 is a memory read / write control device, 9 is a first memory, 10 is a second memory, 11 is a timing control device, 12 is a D / A conversion device, 13 is a first timing detection device, and 14 is a first timing detection device. 2 is the timing detection device, 15 is the third
, 16 is a line gate detecting device, and 17 is a synthesizing judging device.

The principle of operation of the image synthesizing apparatus configured as described above will be described with reference to FIGS. 1, 2 and 3. When two asynchronous still images or continuous image data having different horizontal scanning frequencies and equal vertical scanning frequencies are output from the first image generation device 1 and the second image generation device 2,
The first A / D converter 6 converts image data input as analog RGB signals into digital signals. Second
The A / D converter 7 converts image data input as analog RGB signals into digital signals in the same manner as the first A / D converter 6. The first timing detection device 14 detects a system clock from the first image generation device 1, detects a vertical synchronization signal and a horizontal synchronization signal from the image data, and generates a frame trigger and a trigger (line gate) for each line. Generate. The second timing detection device 15 detects a system clock from the image data output from the second image generation device 2 and generates a frame trigger and a line gate, similarly to the first timing detection device 14. The memory read / write controller 8 counts up by the system clock from the first timing detector 14 and counts up by the address counter reset by the frame trigger and the system clock from the second timing detector 15, and Address control and input / output timing to and from the memory are controlled by an address counter reset by a trigger. The first memory 9 inputs the image data converted into a digital signal by the first A / D converter 6 to an address generated by the first timing detector 13. As the output, the data of the address generated by the first timing detection device 13 is output.

The input / output is switched by the memory read / write controller 8 between input and output for each frame trigger generated by the first timing detector 13. The second memory 10 inputs the image data converted into a digital signal by the second A / D converter 7 to an address generated by the second timing detector 14. As the output, the data of the address generated by the first timing detection device 13 is output. The input and output are switched by the memory read / write control unit 8 for each frame trigger generated by the first timing detection unit 13. The third memory 15 inputs the image data converted into a digital signal by the second A / D converter 7 to an address generated by the second timing detector 14. As the output, the data of the address generated by the first timing detection device 13 is output. The input and output are switched by the memory read / write control unit 8 for each frame trigger generated by the first timing detection unit 13. The state of the second memory 10 and the state of the third memory 15 are always contradictory.

The memory read / write controller 8 inserts a line gate marker into image data when each memory is in a write state and a line gate is detected. The line gate detecting device 16 detects a line gate marker in the image data input from each memory, and invalidates an address counter referred to by the detected memory. The display of the image data in the horizontal direction is stopped at the position where the address counter becomes invalid. When a line gate marker is detected in both the first memory 9 and the image data in the second memory 10 or the third memory 15, the address counter is enabled again. The screen image then wraps horizontally. The synthesis determination device 17 performs the synthesis determination of the first memory 9 and the second memory 10 in the frame trigger period generated by the first timing detection device 13. The determination method compares the image data output from the first memory 9 with a preset luminance level for each pixel, and when the luminance level of the first memory 9 is higher than that, the image data in the first memory 9 is compared. Is smaller than the above, the image data in the second memory 10 or the third memory 15 is output to the D / A converter 12 for each pixel. The D / A converter 12 is the synthesis determination device 1
The D / A converter 7 performs D / A conversion on the composite image data output from the controller 7 and superimposes a synchronizing signal and a blank signal on the image data at the timing input from the timing controller 11 to output a composite image signal.

As described above, the present invention has two memories in one system to which the data of the image generating apparatus is inputted.
By having a timing detection device for each image generation device and having a line gate detection device and a synthesis determination device, a vertical synchronization signal is input asynchronously, and image data having different horizontal scanning frequencies and equal horizontal scanning frequencies is output to the image display device. It is possible to combine and output.

Embodiment 2 FIG. 4 is a diagram showing a configuration of an asynchronous image synthesizing apparatus to which a memory is added according to Embodiment 2 of the present invention, wherein 1 is a first image synthesizing apparatus, and 2 is a second image synthesizing apparatus. 6 is a first A / D converter, 7 is a second A / D converter, 8 is a memory read / write controller, 9 is a first memory, 10 is a second memory, and 11 is timing. Control device, 12 is D / A
A conversion device, 13 is a first timing detection device, 14 is a second timing detection device, 15 is a third memory, 16 is a line gate detection device, 17 is a synthesis determination device, and 18 is a fourth memory.

The principle of operation of the image synthesizing apparatus configured as described above will be described with reference to FIGS. 3, 4, and 5. FIG. When two asynchronous still images or continuous image data having different horizontal scanning frequencies and equal vertical scanning frequencies are output from the first image generation device 1 and the second image generation device 2,
The first A / D converter 6 converts image data input as analog RGB signals into digital signals. Second
The A / D converter 7 converts image data input as analog RGB signals into digital signals in the same manner as the first A / D converter 6. The first timing detection device 14 detects a system clock from the first image generation device 1, detects a vertical synchronization signal and a horizontal synchronization signal from the image data, and generates a frame trigger and a trigger (line gate) for each line. Generate. The second timing detection device 15 detects a system clock from the image data output from the second image generation device 2 and generates a frame trigger and a line gate, similarly to the first timing detection device 14. The memory read / write controller 8 counts up by the system clock from the first timing detector 14 and counts up by the address counter reset by the frame trigger and the system clock from the second timing detector 15, and Address control and input / output timing to and from the memory are controlled by an address counter reset by a trigger. The first memory 9 inputs the image data converted into a digital signal by the first A / D converter 6 to an address generated by the first timing detector 13. As the output, the data of the address generated by the first timing detection device 13 is output.

The input / output is switched by the memory read / write controller 8 for each frame trigger generated by the first timing detector 13. The fourth memory 18 inputs the image data converted into a digital signal by the first A / D converter 6 to an address generated by the first timing detector 13. As the output, the data of the address generated by the first timing detection device 13 is output. The input and output are switched by the memory read / write control unit 8 for each frame trigger generated by the first timing detection unit 13. The state of the first memory 9 and the state of the fourth memory 18 are always contradictory. The second memory 10 has a second A
The image data converted into a digital signal by the / D conversion device 7 is input to the address generated by the second timing detection device 14. As the output, the data of the address generated by the first timing detection device 13 is output. The input / output is performed by the memory read / write controller 8 in the first
The input and output are switched for each frame trigger generated by the timing detection device 13 of FIG. Third memory 15
Converts the image data converted into a digital signal by the second A / D converter 7 into a second timing detector 14
To the address generated by. As the output, the data of the address generated by the first timing detection device 13 is output. The input and output are switched by the memory read / write control unit 8 for each frame trigger generated by the first timing detection unit 13. The state of the second memory 10 and the state of the third memory 15 are always contradictory.

The memory read / write controller 8 inserts a line gate marker into image data when each memory is in a write state and a line gate is detected. The line gate detecting device 16 detects a line gate marker in the image data input from each memory, and invalidates an address counter referred to by the detected memory. The display of the image data in the horizontal direction is stopped at the position where the address counter becomes invalid. When a line gate marker is detected in both the first memory 9 or the fourth memory and the image data in the second memory 10 or the third memory 15,
Enable the address counter again. The screen image then wraps horizontally. The synthesizing determination unit 17 determines the synthesizing determination of the first memory 9 and the second memory 10 and the synthesizing determination of the fourth memory 18 and the third memory 15 according to the frame trigger period generated by the first timing detecting unit 13. Do. The determination method compares the image data output from the first memory 9 or the fourth memory 18 with a preset brightness level for each pixel, and determines whether the brightness level of the first memory 9 or the fourth memory 18 is In the above case, the first memory 9
Alternatively, the image data of the fourth memory is output to the D / A converter 12 for each pixel in the case of the image data of the second memory 10 or the third memory 15 which is smaller than that. The D / A converter 12 performs D / A conversion on the synthesized image data output from the synthesis determination device 17 and superimposes a synchronizing signal and a blank signal on the image data at the timing input from the timing control device 11 to convert the synthesized image signal. Output.

As described above, the present invention has two memories for both streams to which data of the image generation device is input, and has a timing detection device for each image generation device.
The provision of the line gate detecting device and the synthesizing judging device makes it possible to asynchronously input a vertical synchronizing signal and synthesize and output image data having different horizontal scanning frequencies and equal horizontal scanning frequencies to the image display device.

Third Embodiment FIG. 6 is a diagram showing a configuration of an asynchronous image synthesizing apparatus to which a data sampler according to a third embodiment of the present invention is added.
In the figure, 1 is a first image synthesizing device, 2 is a second image synthesizing device, 6 is a first A / D converter, and 7 is a second A / D.
A conversion device, 8 is a memory read / write control device, 9 is a first memory, 10 is a second memory, 11 is a timing control device, 12 is a D / A conversion device, 13 is a first timing detection device, and 14 is a first timing detection device. 2 is the timing detection device, 15 is the third
, 16 is a line gate detecting device, 17 is a synthesis judging device, 19 is a resolution adjusting circuit, 20 is a first data sampler, and 21 is a second data sampler.

The operation principle of the image synthesizing apparatus configured as described above will be described with reference to FIGS. 2, 3 and 6. When two asynchronous still images or continuous image data having different horizontal scanning frequencies and equal vertical scanning frequencies are output from the first image generation device 1 and the second image generation device 2,
The first A / D converter 6 converts image data input as analog RGB signals into digital signals. Second
The A / D converter 7 converts image data input as analog RGB signals into digital signals in the same manner as the first A / D converter 6. The first timing detecting device 13 detects a system clock from the first image generating device 1, detects a vertical synchronizing signal and a horizontal synchronizing signal from image data, and generates a frame trigger and a trigger (line gate) for each line. Generate. The second timing detection device 14 detects a system clock from the image data output from the second image generation device 2 and generates a frame trigger and a line gate in the same manner as the first timing detection device 13. The memory read / write controller 8 counts up with the system clock from the first timing detector 13 and counts up with the address counter reset by the frame trigger and the system clock from the second timing detector 14, Address control and input / output timing to and from the memory are controlled by an address counter reset by a trigger. The resolution adjusting circuit 19 compares the resolutions of the image data input from the first A / D converter 6 and the second A / D converter 7 and converts the high-resolution image data to the low-resolution image data. The control signal for matching is set to the first
To the second data sampler 20 and the second data sampler 21. First data sampler 2
0 samples the image data input from the first A / D converter 6 in accordance with the control signal generated by the resolution adjusting circuit 19, in accordance with the control signal. Similarly to the first data sampler 20, the second data sampler 21 converts the image data input from the second A / D converter 7 into a digital image signal according to the control signal generated by the resolution adjustment circuit 19. Perform sampling. The first memory 9 has a first data sampler 20
Is input to the address generated by the first timing detection device 13. As the output, the data of the address generated by the first timing detection device 13 is output.

The input / output is switched by the memory read / write control device 8 for each frame trigger generated by the first timing detection device 13. The second memory 10 stores the image data sampled by the second data sampler 21 in the second timing detection device 1.
4 to the address generated. As the output, the data of the address generated by the first timing detection device 13 is output. Input / output is a memory read / write controller 8
Thus, the input and output are switched for each frame trigger generated by the first timing detection device 13. Third
Memory 15 inputs the image data sampled by the second data sampler 21 to the address generated by the second timing detection device 14. As the output, the data of the address generated by the first timing detection device 13 is output. The input and output are switched by the memory read / write control unit 8 for each frame trigger generated by the first timing detection unit 13.
The state of the second memory 10 and the state of the third memory 15 are always contradictory.

The memory read / write controller 8 inserts a line gate marker into image data when each memory is in a write state and a line gate is detected. The line gate detecting device 16 detects a line gate marker in the image data input from each memory, and invalidates an address counter referred to by the detected memory. The display of the image data in the horizontal direction is stopped at the position where the address counter becomes invalid. When a line gate marker is detected in both the first memory 9 and the image data in the second memory 10 or the third memory 15, the address counter is enabled again. The screen image then wraps horizontally. The synthesis determination device 17 performs the synthesis determination of the first memory 9 and the second memory 10 in the frame trigger period generated by the first timing detection device 13. The determination method compares the image data output from the first memory 9 with a preset luminance level for each pixel, and when the luminance level of the first memory 9 is higher than that, the image data in the first memory 9 is compared. Is smaller than the above, the image data in the second memory 10 or the third memory 15 is output to the D / A converter 12 for each pixel. The D / A converter 12 is the synthesis determination device 1
The D / A converter 7 performs D / A conversion on the composite image data output from the controller 7 and superimposes a synchronizing signal and a blank signal on the image data at the timing input from the timing controller 11 to output a composite image signal.

As described above, the present invention has a resolution adjusting circuit, has two memories in one system to which data of the image generating device is inputted, has a timing detecting device for each image generating device, and has a line gate detecting device. By providing the device and the synthesis determination device, the vertical synchronization signal is asynchronously input, the horizontal scanning frequencies are different, the horizontal scanning frequencies are equal, and the image data having different resolutions can be synthesized and output to the image display device on the same scale. Become.

Embodiment 4 FIG. 7 is a diagram showing a configuration of an asynchronous image synthesizing apparatus to which a memory is added according to Embodiment 4 of the present invention. In FIG. 7, 1 is a first image synthesizing apparatus, and 2 is a second image synthesizing apparatus. 6 is a first A / D converter, 7 is a second A / D converter, 8 is a memory read / write controller, 9 is a first memory, 10 is a second memory, and 11 is timing. Control device, 12 is D / A
A conversion device, 13 is a first timing detection device, 14 is a second timing detection device, 15 is a third memory, 16 is a line gate detection device, 17 is a synthesis determination device, 18 is a fourth memory, 19 is A resolution adjustment circuit, 20 is a first data sampler, and 21 is a second data sampler.

The operation principle of the image synthesizing apparatus configured as described above will be described with reference to FIGS. 3, 5, and 7. FIG. When two asynchronous still images or continuous image data having different horizontal scanning frequencies and equal vertical scanning frequencies are output from the first image generation device 1 and the second image generation device 2,
The first A / D converter 6 converts image data input as analog RGB signals into digital signals. Second
The A / D converter 7 converts image data input as analog RGB signals into digital signals in the same manner as the first A / D converter 6. The first timing detecting device 13 detects a system clock from the first image generating device 1, detects a vertical synchronizing signal and a horizontal synchronizing signal from image data, and generates a frame trigger and a trigger (line gate) for each line. Generate. The second timing detection device 14 detects a system clock from the image data output from the second image generation device 2 and generates a frame trigger and a line gate in the same manner as the first timing detection device 13. The memory read / write controller 8 counts up with the system clock from the first timing detector 13 and counts up with the address counter reset by the frame trigger and the system clock from the second timing detector 14, Address control and input / output timing to and from the memory are controlled by an address counter reset by a trigger. The resolution adjusting circuit 19 compares the resolutions of the image data input from the first A / D converter 6 and the second A / D converter 7 and converts the high-resolution image data to the low-resolution image data. The control signal for matching is set to the first
To the second data sampler 20 and the second data sampler 21. First data sampler 2
0 samples the image data input from the first A / D converter 6 in accordance with the control signal generated by the resolution adjusting circuit 19, in accordance with the control signal. Similarly to the first data sampler 20, the second data sampler 21 converts the image data input from the second A / D converter 7 into a digital image signal according to the control signal generated by the resolution adjustment circuit 19. Perform sampling. The first memory 9 has a first data sampler 20
Is input to the address generated by the first timing detection device 13. As the output, the data of the address generated by the first timing detection device 13 is output.

The input / output is switched by the memory read / write control device 8 for each frame trigger generated by the first timing detection device 13. The fourth memory 18 stores the image data sampled by the first data sampler 20 in the first timing detection device 1.
Input to the address generated by step 3. As the output, the data of the address generated by the first timing detection device 13 is output. Input / output is a memory read / write controller 8
Thus, the input and output are switched for each frame trigger generated by the first timing detection device 13. First
The state of the memory 9 and the state of the fourth memory 18 are always contradictory. The second memory 10 stores the image data sampled by the second data sampler 21 in the second memory
At the address generated by the timing detection device 14 of FIG. As the output, the data of the address generated by the first timing detection device 13 is output. The input and output are switched by the memory read / write control unit 8 for each frame trigger generated by the first timing detection unit 13. The third memory 15 stores the image data sampled by the second data sampler 21,
The address is input to the address generated by the second timing detection device 14. As the output, the data of the address generated by the first timing detection device 13 is output. The input and output are switched by the memory read / write control unit 8 for each frame trigger generated by the first timing detection unit 13. The state of the second memory 10 and the third
The state of the memory 15 is always a contradiction state.

The memory read / write controller 8 inserts a line gate marker into image data when each memory is in a write state and a line gate is detected. The line gate detecting device 16 detects a line gate marker in the image data input from each memory, and invalidates an address counter referred to by the detected memory. In the screen image, the display of the image data in the horizontal direction stops at the position where the address counter becomes invalid. If a line gate marker is detected in both the first memory 9 or the fourth memory 18 and the image data in the second memory 10 or the third memory 15, the address counter is enabled again. The screen image then wraps horizontally. Composition determination device 17
Performs the synthesis determination of the first memory 9 and the second memory 10 and the synthesis determination of the fourth memory 18 and the third memory 15 in the frame trigger period generated by the first timing detection device 13. The determination method compares the image data output from the first memory 9 or the fourth memory 18 with a preset brightness level for each pixel, and determines whether the brightness level of the first memory 9 or the fourth memory 18 is In the above case, the image data in the first memory 9 or the fourth memory is stored in the D / A converter 12 in pixel units. Output. The D / A converter 12 performs D / A conversion on the synthesized image data output from the synthesis determination device 17 and superimposes a synchronizing signal and a blank signal on the image data at the timing input from the timing control device 11 to convert the synthesized image signal. Output.

As described above, the present invention has a resolution adjusting circuit, has two memories for both streams to which data of the image generation device is input, has a timing detection device for each image generation device, and has a line gate. By providing a detection device and a synthesis determination device, it is possible to asynchronously input a vertical synchronization signal, synthesize and output image data with different horizontal scanning frequencies, equal horizontal scanning frequencies, and different resolutions to the image display device on the same scale. Becomes

Fifth Embodiment FIG. 8 is a diagram showing a configuration of an asynchronous image synthesizing apparatus to which a pixel enlargement processor according to a third embodiment of the present invention is added. In FIG. A second image synthesizing device, 6 is a first A / D converter, 7 is a second A / D converter, 8 is a memory read / write controller, 9 is a first memory, 10 is a second memory, 11 is a timing control device,
12 is a D / A conversion device, 13 is a first timing detection device, 14 is a second timing detection device, 15 is a third memory, 16 is a line gate detection device, 17 is a synthesis judgment device, and 19 is resolution adjustment The circuit, 22 is a first pixel enlargement processor, and 23 is a second pixel enlargement processor.

The principle of operation of the image synthesizing apparatus configured as described above will be described with reference to FIGS. 2, 3 and 8. When two asynchronous still images or continuous image data having different horizontal scanning frequencies and equal vertical scanning frequencies are output from the first image generation device 1 and the second image generation device 2,
The first A / D converter 6 converts image data input as analog RGB signals into digital signals. Second
The A / D converter 7 converts image data input as analog RGB signals into digital signals in the same manner as the first A / D converter 6. The first timing detecting device 13 detects a system clock from the first image generating device 1, detects a vertical synchronizing signal and a horizontal synchronizing signal from image data, and generates a frame trigger and a trigger (line gate) for each line. Generate. The second timing detection device 14 detects a system clock from the image data output from the second image generation device 2 and generates a frame trigger and a line gate in the same manner as the first timing detection device 13. The memory read / write controller 8 counts up with the system clock from the first timing detector 13 and counts up with the address counter reset by the frame trigger and the system clock from the second timing detector 14, Address control and input / output timing to and from the memory are controlled by an address counter reset by a trigger. The resolution adjustment circuit 19 compares the resolutions of the image data input from the first A / D converter 6 and the second A / D converter 7 and converts the low resolution image data to the high resolution image data. The control signal for matching is set to the first
Are output to the pixel enlargement processor 22 and the second pixel enlargement processor 23. The first pixel enlargement processor 22 converts the image data input from the first A / D converter 6 into a resolution adjustment circuit 1
According to the control signal generated in step 9, the digital image signal is subjected to pixel enlargement processing. Similarly to the first pixel enlargement processor 22, the second pixel enlargement processor 23 converts the image data input from the second A / D converter 7 into a digital image according to the control signal generated by the resolution adjustment circuit 19. The pixel enlargement processing of the signal is performed. The first memory 9 inputs the image data subjected to the pixel enlargement processing by the first pixel enlargement processor 22 to the address generated by the first timing detection device 13. As the output, the data of the address generated by the first timing detection device 13 is output.

The input / output is switched by the memory read / write control device 8 for each frame trigger generated by the first timing detection device 13. The second memory 10 inputs the image data sampled by the second pixel enlargement processor 23 to the address generated by the second timing detection device 14. As the output, the data of the address generated by the first timing detection device 13 is output. The input and output are switched by the memory read / write control unit 8 for each frame trigger generated by the first timing detection unit 13. The third memory 15 inputs the image data subjected to the pixel enlargement processing by the second pixel enlargement processor 23 to the address generated by the second timing detection device 14. As the output, the data of the address generated by the first timing detection device 13 is output. The input and output are switched by the memory read / write control unit 8 for each frame trigger generated by the first timing detection unit 13. The state of the second memory 10 and the state of the third memory 15 are always contradictory.

The memory read / write controller 8 inserts a line gate marker into image data when each memory is in a write state and a line gate is detected. The line gate detecting device 16 detects a line gate marker in the image data input from each memory, and invalidates an address counter referred to by the detected memory. The display of the image data in the horizontal direction is stopped at the position where the address counter becomes invalid. When a line gate marker is detected in both the first memory 9 and the image data in the second memory 10 or the third memory 15, the address counter is enabled again. The screen image then wraps horizontally. The synthesis determination device 17 performs the synthesis determination of the first memory 9 and the second memory 10 in the frame trigger period generated by the first timing detection device 13. The determination method compares the image data output from the first memory 9 with a preset luminance level for each pixel, and when the luminance level of the first memory 9 is higher than that, the image data in the first memory 9 is compared. Is smaller than the above, the image data in the second memory 10 or the third memory 15 is output to the D / A converter 12 for each pixel. The D / A converter 12 is the synthesis determination device 1
The D / A converter 7 performs D / A conversion on the composite image data output from the controller 7 and superimposes a synchronizing signal and a blank signal on the image data at the timing input from the timing controller 11 to output a composite image signal.

As described above, the present invention has a resolution adjusting circuit, has two memories in one system to which data of the image generating device is input, has a timing detecting device for each image generating device, and has a line gate detecting device. By providing the device and the synthesis determination device, the vertical synchronization signal is asynchronously input, the horizontal scanning frequencies are different, the horizontal scanning frequencies are equal, and the image data having different resolutions can be synthesized and output to the image display device on the same scale. Become.

Embodiment 6 FIG. 9 is a diagram showing a configuration of an asynchronous image synthesizing apparatus to which a memory is added according to Embodiment 6 of the present invention. In FIG. 6 is a first A / D converter, 7 is a second A / D converter, 8 is a memory read / write controller, 9 is a first memory, 10 is a second memory, and 11 is timing. Control device, 12 is D / A
A conversion device, 13 is a first timing detection device, 14 is a second timing detection device, 15 is a third memory, 16 is a line gate detection device, 17 is a synthesis determination device, 18 is a fourth memory, 19 is A resolution adjustment circuit, 22 is a first pixel enlargement processor, and 23 is a second pixel enlargement processor.

The operation principle of the image synthesizing apparatus configured as described above will be described with reference to FIGS. 3, 5, and 9. FIG. When two asynchronous still images or continuous image data having different horizontal scanning frequencies and equal vertical scanning frequencies are output from the first image generation device 1 and the second image generation device 2,
The first A / D converter 6 converts image data input as analog RGB signals into digital signals. Second
The A / D converter 7 converts image data input as analog RGB signals into digital signals in the same manner as the first A / D converter 6. The first timing detecting device 13 detects a system clock from the first image generating device 1, detects a vertical synchronizing signal and a horizontal synchronizing signal from image data, and generates a frame trigger and a trigger (line gate) for each line. Generate. The second timing detection device 14 detects a system clock from the image data output from the second image generation device 2 and generates a frame trigger and a line gate in the same manner as the first timing detection device 13. The memory read / write controller 8 counts up with the system clock from the first timing detector 13 and counts up with the address counter reset by the frame trigger and the system clock from the second timing detector 14, Address control and input / output timing to and from the memory are controlled by an address counter reset by a trigger. The resolution adjustment circuit 19 compares the resolutions of the image data input from the first A / D converter 6 and the second A / D converter 7 and converts the low resolution image data to the high resolution image data. The control signal for matching is set to the first
Are output to the pixel enlargement processor 22 and the second pixel enlargement processor 23. The first pixel enlargement processor 22 converts the image data input from the first A / D converter 6 into a resolution adjustment circuit 1
According to the control signal generated in step 9, the digital image signal is subjected to pixel enlargement processing. Similarly to the first pixel enlargement processor 22, the second pixel enlargement processor 23 converts the image data input from the second A / D converter 7 into a digital image according to the control signal generated by the resolution adjustment circuit 19. The pixel enlargement processing of the signal is performed. The first memory 9 inputs the image data subjected to the pixel enlargement processing by the first pixel enlargement processor 22 to the address generated by the first timing detection device 13. As the output, the data of the address generated by the first timing detection device 13 is output.

The input / output is switched by the memory read / write controller 8 for each frame trigger generated by the first timing detector 13. The fourth memory 18 inputs the image data subjected to the pixel enlargement processing by the second pixel enlargement processor 23 to the address generated by the first timing detection device 13. As the output, the data of the address generated by the first timing detection device 13 is output. The input and output are switched by the memory read / write control unit 8 for each frame trigger generated by the first timing detection unit 13. The state of the first memory 9 and the state of the fourth memory 18 are always contradictory. The second memory 10 is a second pixel enlargement processor 2
The image data subjected to the pixel enlargement processing in step 3 is input to the address generated by the second timing detection device 14.
As the output, the data of the address generated by the first timing detection device 13 is output. The input and output are switched by the memory read / write control unit 8 for each frame trigger generated by the first timing detection unit 13. The third memory 15 is a second pixel enlargement processor 23
Is input to the address generated by the second timing detection device 14. As the output, the data of the address generated by the first timing detection device 13 is output. The input and output are switched by the memory read / write control unit 8 for each frame trigger generated by the first timing detection unit 13. The state of the second memory 10 and the state of the third memory 15 are always contradictory.

The memory read / write controller 8 inserts a line gate marker into image data when each memory is in a write state and a line gate is detected. The line gate detecting device 16 detects a line gate marker in the image data input from each memory, and invalidates an address counter referred to by the detected memory. The display of the image data in the horizontal direction is stopped at the position where the address counter becomes invalid. If a line gate marker is detected in both the first memory 9 or the fourth memory 18 and the image data in the second memory 10 or the third memory 15, the address counter is enabled again. The screen image then wraps horizontally. Composition determination device 17
Performs the synthesis determination of the first memory 9 and the second memory 10 and the synthesis determination of the fourth memory 18 and the third memory 15 in the frame trigger period generated by the first timing detection device 13. The determination method compares the image data output from the first memory 9 or the fourth memory 18 with a preset brightness level for each pixel, and determines whether the brightness level of the first memory 9 or the fourth memory 18 is In the above case, the image data in the first memory 9 or the fourth memory is stored in the D / A converter 12 in pixel units. Output. The D / A converter 12 performs D / A conversion on the synthesized image data output from the synthesis determination device 17 and superimposes a synchronizing signal and a blank signal on the image data at the timing input from the timing control device 11 to convert the synthesized image signal. Output.

As described above, the present invention has a resolution adjusting circuit, has two memories for both streams to which the data of the image generating device is input, has a timing detecting device for each image generating device, and has a line gate. By providing a detection device and a synthesis determination device, it is possible to asynchronously input a vertical synchronization signal, synthesize and output image data with different horizontal scanning frequencies, equal horizontal scanning frequencies, and different resolutions to the image display device on the same scale. Becomes

[0043]

According to the first aspect of the present invention, in the image synthesizing apparatus, even when the vertical synchronizing signal is asynchronous and an image signal having a different vertical scanning frequency and an equal horizontal scanning frequency is input, the image synthesizing device is still stationary. Image or moving picture image composition becomes possible.

According to the second aspect of the present invention, in the image synthesizing apparatus, even when the vertical synchronizing signal is asynchronous and an image signal having a different vertical scanning frequency and an equal horizontal scanning frequency is input, the image synthesizing device is still stationary. Image or moving image synthesis can be performed in real time.

According to the third aspect, in the image synthesizing apparatus, even when the vertical synchronizing signal is asynchronous, the vertical scanning frequencies are different, the horizontal scanning frequencies are equal, and the image signals having different resolutions are input, the same is applied. Image synthesis of a still image or a moving image can be performed on an image display device on a scale.

According to the fourth aspect of the invention, in the image synthesizing apparatus, even when image signals having different vertical scanning frequencies, equal horizontal scanning frequencies, and different resolutions are input, the vertical synchronizing signals are asynchronous. Image synthesis of a still image or a moving image can be performed in real time on an image display device on a scale.

According to the fifth aspect, in the image synthesizing apparatus, even when image signals having different vertical scanning frequencies, equal horizontal scanning frequencies, and different resolutions are input, the same vertical synchronizing signals are asynchronous. Image synthesis of a still image or a moving image can be performed on an image display device on a scale.

According to the sixth aspect, in the image synthesizing apparatus, even when image signals having different vertical scanning frequencies, different horizontal scanning frequencies, and different resolutions are input, the same vertical synchronizing signals are asynchronous. Image synthesis of a still image or a moving image can be performed in real time on an image display device on a scale.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an asynchronous image synthesizing apparatus according to Embodiment 1 of the present invention.

FIG. 2 is a timing chart for capturing the operation principle of the asynchronous image synthesizing apparatus according to the first, third and fifth embodiments of the present invention.

FIG. 3 is a timing chart for capturing the operating principle of the asynchronous image synthesizing apparatus according to the first, second, third, fourth, fifth and sixth embodiments of the present invention. is there.

FIG. 4 is a block diagram showing a configuration of an asynchronous image synthesizing apparatus according to Embodiment 2 of the present invention.

FIG. 5 is a timing chart for capturing the operation principle of the asynchronous image synthesizing apparatus according to the second, fourth, and sixth embodiments of the present invention.

FIG. 6 is a block diagram showing a configuration of an asynchronous image synthesizing apparatus according to Embodiment 3 of the present invention.

FIG. 7 is a block diagram showing a configuration of an asynchronous image synthesizing apparatus according to Embodiment 4 of the present invention.

FIG. 8 is a block diagram showing a configuration of an asynchronous image synthesizing apparatus according to Embodiment 5 of the present invention.

FIG. 9 is a block diagram showing a configuration of an asynchronous image synthesizing apparatus according to Embodiment 6 of the present invention.

FIG. 10 is a diagram showing the concept of the configuration of a conventional image synthesizing apparatus.

FIG. 11 is a block diagram illustrating a configuration of a conventional image synthesizing apparatus.

[Explanation of symbols]

1 first image generation device, 2 second image generation device, 3
Image synthesis device, 4 image display device, 5 synchronizer, 6
First A / D converter, 7 Second A / D converter, 8
Memory WRITE / READ control device, 9 first memory, 10 second memory, 11 timing control device,
12 D / A converter, 13 1st timing detection device, 14 2nd timing detection device, 15 3rd memory, 16 line gate detection device, 17 synthesis judgment device, 18 4th memory, 19 resolution adjustment circuit , 20
First data sampler, 21 second data sampler, 22 first pixel enlargement processor, 23 second
Pixel enlargement processor.

Claims (6)

[Claims] An analog RGB (Red Green Bl) is generated from a first image generating apparatus that generates a still image or a moving image.
ue) signal, and a first A / D (Analog to analog / digital) for converting the input signal into digital image data.
(Digital) conversion device, a first memory for storing digital image data output from the first A / D conversion device, and an output signal of the first image generation device. Analog RGB signals are input from a first timing detection device that detects a signal and a second image generation device that generates a still image or a moving image, and a second A / D converter that converts the input signal into digital image data Device, a second memory and a third memory having a double buffer structure capable of alternately storing digital image data output from the second A / D converter for each screen, and the second image generating device A second timing detecting device for inputting an output signal of the first timing detecting device and detecting a synchronizing signal of the input signal, and a second input terminal for inputting an output signal of the first timing detecting device to a first input terminal. A memory read / write control device that receives an output signal of the second timing detection device and generates an input / output control signal for each memory, and a trigger (line) for each line from digital image data input from each memory. (Gate) and a line gate detecting device for generating an input / output control signal for the memory, and a synthesizing unit for judging a synthesizing condition from the luminance level of the digital image data inputted from the line gate detecting device and synthesizing the image signal. A determination device, a timing control device that inputs an output signal of the first timing generation device, controls a timing of a synchronization signal and a blank period, and inputs an output signal of the synthesis determination device to a first input terminal; An output signal of the timing control device is input to a second input terminal, and output from the synthesis determination device in synchronization with the second input signal. Image synthesizing apparatus characterized by having a Ijitaru image data D / A (Digital to Analog) for converting the D / A converter. 2. A method according to claim 1, wherein the first image generating apparatus for generating a still image or a moving image receives analog RGB (Red Green Bl).
ue) signal, and a first A / D (Analog to analog / digital) for converting the input signal into digital image data.
(Digital) conversion device; a first memory and a fourth memory having a double buffer structure capable of alternately storing digital image data output from the first A / D conversion device for each screen; An analog RGB signal is input from a first timing detection device that receives an output signal of the image generation device and detects a synchronization signal of the input signal, and a second image generation device that generates a still image or a moving image. A / D converter for converting digital image data into digital image data, and a second memory having a double buffer structure capable of alternately storing digital image data output from the second A / D converter for each screen And a third memory, a second timing detection device that receives an output signal of the second image generation device, and detects a synchronization signal of the input signal, and a first input terminal that is connected to the first input terminal. A memory read / write control device that receives an output signal of the timing detection device, inputs an output signal of the second timing detection device to a second input terminal, and generates an input / output control signal for each memory; A line gate detecting device for detecting a trigger (line gate) for each line from the digital image data input from the memory and generating an input / output control signal for the memory; and a digital image data input from the line gate detecting device. A synthesizing judging device for judging a synthesizing condition from a luminance level and synthesizing an image signal, a timing control device for inputting an output signal of the first timing generating device, and controlling a timing of a synchronizing signal and a blank period; An output signal of the synthesizing determination device is input to one input terminal, and an output signal of the timing control device is input to a second input terminal. D / A digital image data outputted from the combination judging device in synchronization with the second input signal (Digital to Analog)
An image synthesizing apparatus, comprising: a D / A converter for performing conversion. 3. A first A / D converter for inputting an analog RGB signal from a first image generation device for generating a still image or a moving image and converting the input signal into digital image data, and a still image or a moving image And a second A / D converter for converting the input signal into digital image data, and a first A / D converter connected to a first input terminal. An output signal of the converter is input, and an output signal of the second A / D converter is input to a second input terminal. The resolutions of the two input digital image data are compared with each other, and a control signal is output. A resolution adjusting circuit for outputting, and the first A
A first data sampler for inputting an output signal of a / D conversion device, inputting an output signal of the resolution adjustment circuit to a second input terminal, and thinning out digital image data; and a first data sampler. A first memory for storing digital image data output from the first device, a first timing detection device for inputting an output signal of the first image generation device and detecting a synchronization signal of the input signal, The output signal of the second A / D converter is input to the input terminal,
A second data sampler for inputting an output signal of the resolution adjusting circuit to an input terminal of the digital data processor and thinning out digital image data, and digital image data output from the second data sampler alternately for each screen. A second memory and a third memory having a double buffer structure which can be stored in the first and second buffers, a second timing detection device which receives an output signal of the second image generation device and detects a synchronization signal of the input signal, The input signal of the first timing detection device is input to the input terminal of the first device, the output signal of the second timing detection device is input to the second input terminal, and an input / output control signal for each memory is generated. Detects a trigger (line gate) for each line from a memory read / write controller and digital image data input from each memory, and generates a memory input / output control signal A line gate detecting device, a synthesizing judging device for judging a synthesizing condition from a luminance level of digital image data inputted from the line gate detecting device, and synthesizing an image signal; and an output signal of the first timing generating device. And a timing control device for controlling the timing of the synchronization signal and the blank period, an output signal of the synthesis determination device being input to a first input terminal, and an output signal of the timing control device being input to a second input terminal. And a D / A converter for performing D / A conversion of digital image data input from the synthesizing determination device in synchronization with the second input signal. 4. A first A / D converter for inputting an analog RGB signal from a first image generating device for generating a still image or a moving image and converting the input signal into digital image data, and a still image or a moving image And a second A / D converter for converting the input signal into digital image data, and a first A / D converter connected to a first input terminal. An output signal of the converter is input, and an output signal of the second A / D converter is input to a second input terminal. The resolutions of the two input digital image data are compared with each other, and a control signal is output. A resolution adjusting circuit for outputting, and the first A
A first data sampler for inputting an output signal of a / D conversion device, inputting an output signal of the resolution adjustment circuit to a second input terminal, and thinning out digital image data; and a first data sampler. A first memory and a fourth memory having a double buffer structure capable of alternately storing digital image data output from
A first timing detection device for inputting an output signal of the image generation device of (1) and detecting a synchronizing signal of the input signal, and an output signal of the second A / D conversion device at a first input terminal; Input the output signal of the resolution adjustment circuit to the input terminal
A second data sampler for thinning out digital image data, a second memory having a double buffer structure capable of alternately storing digital image data output from the second data sampler for each screen, and a third memory; A memory, and an output signal of the second image generation device,
A second timing detection device for detecting a synchronization signal of the input signal; an output signal of the first timing detection device being input to a first input terminal; and a second input terminal having an output signal of the second timing detection device. A memory read / write control device for inputting an output signal and generating an input / output control signal for each memory, and detecting a trigger (line gate) for each line from digital image data input from each memory, A line gate detecting device for generating an input / output control signal, a synthesizing judging device for judging a synthesizing condition from a luminance level of digital image data inputted from the line gate detecting device, and synthesizing an image signal; A timing control device for inputting an output signal of the timing generation device and controlling the timing of a synchronization signal and a blank period; The output signal of the location, the output signal of the timing controller to the second input terminal, a second
And a D / A converter for performing D / A conversion of digital image data output from the synthesizing determination device in synchronization with the input signal. 5. A first A / D converter for inputting an analog RGB signal from a first image generating device for generating a still image or a moving image and converting the input signal into digital image data, and a still image or a moving image And a second A / D converter for converting the input signal into digital image data, and a first A / D converter connected to a first input terminal. An output signal of the converter is input, and an output signal of the second A / D converter is input to a second input terminal. The resolutions of the two input digital image data are compared with each other, and a control signal is output. A resolution adjusting circuit for outputting, and the first A
A first pixel enlargement processor for inputting an output signal of the / D conversion device, inputting an output signal of the resolution adjustment circuit to a second input terminal, and enlarging pixels of digital image data; A first memory that stores digital image data output from the enlargement processor, a first timing detection device that receives an output signal of the first image generation device, and detects a synchronization signal of the input signal; The second input is connected to the first input terminal.
A second pixel enlargement processor that inputs an output signal of the A / D converter of the above, inputs an output signal of the resolution adjustment circuit to a second input terminal, and enlarges pixels of digital image data; A second memory and a third memory having a double buffer structure capable of alternately storing digital image data output from the pixel enlargement processor for each screen, and an output signal of the second image generation device, A second timing detection device for detecting a synchronization signal of the input signal, and an output signal of the first timing detection device input to a first input terminal,
A memory read / write control device for inputting an output signal of the second timing detection device to an input terminal and generating an input / output control signal for each memory; and a digital image data input from each memory for each line. And a line gate detecting device for detecting a trigger (line gate) of the image signal and generating a memory input / output control signal; and determining a synthesizing condition from a luminance level of the digital image data input from the line gate detecting device. A synthesizing determination device that performs synthesis, a timing control device that receives an output signal of the first timing generation device, and controls a timing of a synchronization signal and a blank period, and an output signal of the synthesis determination device at a first input terminal Is input to the second input terminal, and the output signal of the timing control device is input to the second input terminal. Image synthesizing apparatus characterized by having a D / A converter for performing D / A conversion of the digital image data. 6. A first A / D converter for receiving an analog RGB signal from a first image generating device for generating a still image or a moving image and converting the input signal into digital image data, and a still image or a moving image And a second A / D converter for converting the input signal into digital image data, and a first A / D converter connected to a first input terminal. An output signal of the converter is input, and an output signal of the second A / D converter is input to a second input terminal. The resolutions of the two input digital image data are compared with each other, and a control signal is output. A resolution adjusting circuit for outputting, and the first A
A first pixel enlargement processor for inputting an output signal of the / D conversion device, inputting an output signal of the resolution adjustment circuit to a second input terminal, and enlarging pixels of digital image data; A first memory and a fourth memory having a double buffer structure capable of alternately storing digital image data output from the enlargement processor for each screen, and an output signal of the first image generating apparatus, and an input signal A first timing detection device for detecting the synchronization signal of the first and second input terminals, an output signal of the second A / D converter device is input to a first input terminal, and an output signal of the resolution adjustment circuit is input to a second input terminal. A second pixel enlargement processor for inputting and enlarging pixels of digital image data;
A second memory and a third memory having a double buffer structure capable of alternately storing digital image data output from the second pixel enlargement processor for each screen, and an output signal of the second image generation device. A second timing detection device for inputting and detecting a synchronization signal of an input signal; an output signal of the first timing detection device being input to a first input terminal; and a second timing detection device being connected to a second input terminal. A memory read / write control device that receives an output signal of the detection device and generates an input / output control signal for each memory, and detects a trigger (line gate) for each line from digital image data input from each memory. Determining a synthesizing condition from a line gate detecting device for generating an input / output control signal of a memory, and a luminance level of digital image data input from the line gate detecting device. A synthesizing determination device for synthesizing an image signal, a timing control device for inputting an output signal of the first timing generation device and controlling the timing of a synchronization signal and a blank period, and a synthesizing determination device at a first input end , An output signal of the timing control device is input to a second input terminal, and D / A conversion of digital image data output from the synthesis determination device is performed in synchronization with the second input signal. An image synthesizing device, comprising: a D / A converter.