JP2000124750A - Current source circuit and gain control amplifier - Google Patents

Abstract

PROBLEM TO BE SOLVED: To relieve the limitation of an input signal level and also attain the output control by providing a MOS transistor TR in series to a reference current path of a current mirror circuit so as not to make the current depend on the on-resistance of the MOS TR and reducing the variations of increment value of the output level of a gain control amplifier with respect to the constant increment value of the control step of a control terminal. SOLUTION: The AC signals which are inputted to the input terminals Vin1 52 and Vin2 53 are inputted to the bases of NPN TR 20 and 21, respectively. The AC signal currents accordant with the amplitudes of inputted AC signals are turned by a current mirror circuit consisting of P-channel MOS TR 3 and 4 and a current mirror circuit consisting of P-channel MOS TR 5 and 6 and then inputted to a current mirror circuit consisting of NPN TR 22 and 23. The current difference of a current mirror circuit is defined as the input/output current to be supplied to the load resistance.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for inputting, amplifying and outputting power, and more particularly to a circuit using a differential amplifier circuit.

[0002]

2. Description of the Related Art Generally, in order to input a certain value of power and to enable the amplification of the power, it is necessary to have an amplifier circuit in an electric circuit, and it is more stable to reduce the gain fluctuation of the amplifier. Necessary for amplifier circuits.

An example of a conventional gain control amplifier will be described with reference to FIGS. FIG. 6 is a circuit diagram of a conventional gain control amplifier. FIG. 7 is a diagram showing the control step of the control terminal versus the output level of the gain control amplifier in the conventional example.

FIG. 6 shows an example of a configuration of a conventional gain control amplifier.
It will be described based on. NPN to input terminal IN1 701
The base of the transistor 711 is connected, and the input terminal IN2
The base of an NPN transistor 712 is connected to 702, the emitters of the NPN transistors are connected to each other, and the emitters are connected to the collectors of another two NPN transistors 722 and 723. An NPN transistor 722, which is one of the two NPN transistors, is an NPN transistor 72 having a reference side forming a part of a current mirror circuit.
1 and a current mirror circuit, the NPN transistor 721 and the base are connected to each other, and the emitter is connected to the drain of the N-channel MOS transistor 732. The emitter of NPN transistor 721 is connected to the drain of N-channel MOS transistor 731,
The gate of the channel MOS transistor 731 is connected to the gate of the N-channel MOS transistor 732. The other NPN transistor 723 has a base connected to the base of the previous NPN transistor 722, an emitter connected to the drain of the N-channel MOS transistor 733, and
The control terminal CTL1 741 is connected to the gate of 33. Further, the collector of the NPN transistor 711 is connected to the base of the NPN transistor 713 and the resistor 75.
1 is connected. Another end of the resistor 751 is connected to a voltage source VC.
It is connected to C705. The collector of the NPN transistor 712 is connected to the base of the NPN transistor 714 and the resistor 752. Another end of the resistor 752 is connected to the voltage source VCC 705.

The connection of the NPN transistor 713 and the emitter and collector of the NPN transistor 714
The connection is the same as that of the NPN transistor 711 and the emitter and collector of the NPN transistor 712, respectively. That is, the resistor 751 is replaced by the resistor 753,
2 to the resistor 754, and the NPN transistor 722 to the NPN
The NPN transistor 723 is set to N
An N-channel MOS transistor 732 is replaced with an N-channel MOS transistor 734
And the N-channel MOS transistor 733 to the N-channel MOS transistor 735 and the control terminal C
When the TL1 741 is converted to the control terminal CTL2 742, the connection becomes the same as the connection between the NPN transistor 711 and the NPN transistor 712. Regarding the connection with other elements of the other NPN transistors 715 and 716, the NPN transistors 713 and NP
The N transistor 714 and the NPN transistor 7
15 and the output terminal OUT2 70 of the NPN transistor 716.
Exactly the same except 4 is connected. In addition, differential amplifier circuits 711 and 71 composed of respective NPN transistors
The gains of 2, 713, 714, 715, and 716 are arbitrarily set by setting the current value of a current mirror circuit serving as a constant current source.

In the conventional gain control amplifier having the above configuration, since the differential amplifier circuit has a multi-stage configuration, the gain variation of the differential amplifier at each stage is directly reflected on the relative variation of the gain. The switch of the N-channel MOS transistor uses the ON resistance when the N-channel MOS transistor is ON as a feedback resistance of the current mirror, and the ON resistance value of the N-channel MOS transistor contributes to the gain of the differential amplifier. For this reason, gain fluctuation is likely to occur due to variations in output of the N-channel MOS transistor and temperature dependency. The main effect of these two factors is that the increase in the gain control amplifier output level with respect to the increase in the control terminal control step becomes unstable in the control terminal control step vs. gain control amplifier output level diagram in FIG. appear. As a result, control for obtaining a stable output cannot be executed. In addition, in order to obtain a signal having no distortion in the output, the amplitude level of the input signal must be limited so as to be within the input dynamic range of the final stage of the cascade-connected amplifiers. Since the input dynamic range of the amplifier is insufficient, the signal is distorted there. Further, at a low power supply voltage, there is a problem that the output amplitude of the gain control amplifier is easily restricted in order to prevent the transistor from being saturated due to the voltage drop of the load resistance of the differential amplifier.

To solve some of the above problems, Japanese Patent Application Laid-Open No. 3-228412 discloses an output current of a hyperbolic characteristic and a square-wave dual-rectification characteristic by a differential pair using bipolar transistors and MOS transistors having different sizes. It is said that the accuracy of the logarithmic amplifier can be improved by adding a load to the output and connecting a load resistor.

[0008]

However, Japanese Patent Application Laid-Open No. Hei 3-2
No. 28412 can certainly improve the accuracy of the logarithmic amplifier circuit, operate from a low voltage and have a wide dynamic range, but the multi-stage configuration of the bipolar transistor differential amplifier circuit and the MOS transistor differential amplifier circuit is possible. Therefore, it is difficult to stabilize the increase in the output level of the gain control amplifier with respect to the increase in the control step of the control terminal due to variations in the quality of the transistors and the like. Therefore, a differential amplifier that has a stable increase in the output level of the gain control amplifier with respect to the increase in the control step of the control terminal, obtains a signal without distortion in the output, and is not easily limited by the output amplitude of the gain control amplifier. It is hard to recognize that it is possible.

In order to solve these problems, the present invention provides:
It is possible to make the amount of increase in the output level of the gain control amplifier substantially equal to the fixed amount of increase in the control step of the control terminal.
The state can be made independent of the ON resistance of the S-transistor, and the relative variation in the gain of the gain control amplifier can be suppressed. In addition, the limitation of the input / output signal level due to the dynamic range of the input / output signal is eased as compared with the conventional case. It is an object of the present invention to provide a current source circuit and a gain control amplifier capable of performing control to obtain a stable output.

[0010]

According to a first aspect of the present invention, there is provided a current source circuit in which a MOS transistor is provided on a reference side of a current mirror circuit in the current source circuit.

Therefore, according to the current source circuit of the first invention of the present application, in the current source circuit, since the MOS transistor is provided on the reference side of the current mirror circuit, the current does not depend on the ON resistance of the MOS transistor. This makes it possible to reduce the variation in the amount of increase in the gain control amplifier output level with respect to a certain amount of increase in the control step of the control terminal.

A current source circuit according to a second aspect of the present invention is characterized in that a MOS transistor is connected to a line connecting the base and the collector of a transistor in a current mirror circuit.

Therefore, according to the current source circuit of the second invention of the present application, by connecting the MOS transistor to the line connecting the base and the collector of the transistor in the current mirror circuit, the current can be reduced by the MOS transistor. Can be made independent of the ON resistance of
Variations in the amount of increase in the output level of the gain control amplifier with respect to a certain amount of increase in the control step of the control terminal can be reduced.

According to a third aspect of the present invention, in the current source circuit according to the first or second aspect of the present invention, the emitter resistance of the current mirror circuit of the current source circuit includes a resistance element.

Therefore, according to the current source circuit of the third invention of the present application, since the emitter resistance of the current mirror circuit of the current source circuit includes a resistance element, the desired current ratio can be set by the ON resistance of the MOS transistor. It becomes possible not to depend on.

The gain control amplifier according to a fourth aspect of the present invention is characterized in that the gain control amplifier is provided with a MOS transistor on a reference side of a current mirror circuit of a current source circuit.

Therefore, according to the gain control amplifier of the fourth invention of the present application, the MOS transistor is provided on the reference side of the current mirror circuit of the current source circuit in the gain control amplifier, so that the current can be reduced by the MOS transistor.
It becomes possible not to depend on the N resistance, and it is possible to reduce the variation of the increase amount of the gain control amplifier output level with respect to a fixed increase amount of the control step of the control terminal. Furthermore, it is possible to suppress the relative variation of the gain of the gain control amplifier, and control to obtain a stable output becomes possible.

According to a fifth aspect of the present invention, in the gain control amplifier according to the fourth aspect of the present invention, the output side currents of the respective current mirror circuits operated by N control signals from the outside are connected by a single line. It is characterized by entertaining.

Therefore, according to the gain control amplifier of the fifth invention of the present application, the currents on the output side of each current mirror circuit operated by N control signals from the outside are connected by a single line. , It is easy to monotonously increase the gain of the gain control amplifier.

A gain control amplifier according to a sixth aspect of the present invention receives power from two input terminals for inputting an AC power supply and the two input terminals, amplifies and outputs a difference between voltages applied between the input terminals. A differential amplifier circuit, a current logarithmic converter circuit connected to the emitter side of the differential amplifier circuit for converting a constant current of the differential amplifier circuit into a logarithm, and a current for controlling a current input to the current logarithmic converter circuit. A mirror circuit, two current mirror circuits respectively controlling two output signals from the differential amplifier circuit, and another different one of each of the two current mirror circuits connected to the output terminal of the differential amplifier circuit. A differential amplifier having a current mirror circuit for connecting terminals to control a signal, and a gain setting load resistor and a buffer circuit connected to an output terminal of the current mirror circuit. And wherein the door.

Therefore, according to the gain control amplifier of the sixth aspect of the present invention, two input terminals for inputting AC power and power are received from the two input terminals, and the difference between the voltages applied between the input terminals is amplified. A differential amplifier circuit connected to the emitter side of the differential amplifier circuit for converting a constant current of the differential amplifier circuit into a logarithm, and a current input to the current logarithmic converter circuit. , Two current mirror circuits respectively controlling two output signals from the differential amplifier circuit, and two current mirror circuits connected to the output terminals of the differential amplifier circuit. A differential circuit having a current mirror circuit for connecting each other terminal to control a signal, a gain setting load resistor and a buffer circuit connected to an output terminal of the current mirror circuit; With the provision of the width member, the load resistance between the power supplies can be driven by the output current source circuit of the current mirror, and therefore, the limitation of the input / output signal level due to the dynamic range of the input / output signal is eased as compared with the conventional case. In addition, the maximum amplitude of the gain control amplifier can be increased more than before, and control for obtaining a stable output can be performed.

According to a seventh aspect of the present invention, in the gain control amplifier according to the sixth aspect of the present invention, the gain control amplifier is connected to a reference side of a current mirror circuit connected to a reference side of a current logarithmic conversion circuit of the differential amplifier. N (N is a natural number) constant current setting current mirror circuits, MOS transistors connected to the reference sides of the respective constant current setting current mirror circuits, and N transistors connected to the respective MOS transistors.
A current source circuit having a staged current mirror circuit and a control terminal connected to each of the MOS transistors is provided.

Therefore, according to the gain control amplifier of the seventh aspect of the present invention, N (N) connected to the reference side of the current mirror circuit connected to the reference side of the current logarithmic conversion circuit of the differential amplifier. Is a natural number) constant current setting current mirror circuits, MOS transistors connected to the reference sides of the respective constant current setting current mirror circuits, N-stage current mirror circuits connected to the respective MOS transistors, By providing a current source circuit having a control terminal connected to each of the MOS transistors, it is possible to reduce a variation in an increase in the output level of the gain control amplifier with respect to a fixed increase in the control step of the control terminal. And the setting of the desired current ratio does not depend on the ON resistance of the MOS transistor. Possible to become.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention and the method will be described below with reference to FIGS.

Embodiment 1 FIG. 1 is a circuit diagram of a current source circuit and a gain control amplifier according to an embodiment of the present invention in which N is an arbitrary natural number. FIG. 2 is a circuit diagram of a current source circuit according to one embodiment when N is 6 in the present invention. FIG. 3 is a list of control steps of the control terminal of the current source circuit according to one embodiment of the present invention. FIG. 4 is a diagram showing a control step of a control terminal and an output level of a gain control amplifier according to an embodiment of the present invention. Hereinafter, the first embodiment in which N is 6 in the current source circuit will be described. In the present invention, it is possible to take an arbitrary natural number as N. In this case, the configuration and operation of the present invention will be described by converting the quantity 6 into an arbitrary natural number N in the following description.

The structure of the first embodiment of the present invention will be described with reference to FIGS. The configuration of the gain control amplifier 100 will be described. The input terminal Vin1 52 and the input terminal Vin
253 each constituting the differential amplifier circuit 110
The bases of the PN transistor 20 and the NPN transistor 21 are connected to each other, the emitters of the NPN transistors are connected to each other, and the emitters are connected to another two NP transistors.
It is connected to the collectors of the N transistor 17 and the NPN transistor 19. An NPN transistor 19, one of the two NPN transistors, forms a current logarithmic conversion circuit 120 with an NPN transistor 18 having a reference side forming a part of the current logarithmic conversion circuit 120.
The NPN transistor 18 and the base are connected to each other, and the emitter is connected to the GND 54. The emitter of the NPN transistor 18 is connected to the resistor 33, and another end of the resistor 33 is connected to GND 54. Further, the base of the NPN transistor 18 is also connected to the collector of the NPN transistor 18. The NPN transistor 18
Is connected to the drain of the P-channel MOS transistor 2, and the gate of the P-channel MOS transistor 2 is connected to the gate of the P-channel MOS transistor 1 and the drain of the P-channel MOS transistor 1. The sources of the P-channel MOS transistor 1 and the P-channel MOS transistor 2 are connected to a voltage source VC.
Connected to C51. On the other hand, the drain of the P-channel MOS transistor 1 is connected to the current source circuit 200. The NPN transistor 17 has a base connected to the base and the collector of the NPN transistor 16, and an emitter connected to the GND 54. NPN transistor 16
Has an emitter connected to the GND 54 and a collector connected to the voltage source VCC 51 through the constant current source 44. Further, the collector of the NPN transistor 20 is connected to the drain and the gate of the P-channel MOS transistor 3. The source of the P-channel MOS transistor 3 is
It is connected to the voltage source VCC51. The collector of the NPN transistor 21 is connected to the drain and the gate of the P-channel MOS transistor 5. The source of the P-channel MOS transistor 5 is a voltage source VCC 51
Connected to. The gate of the P-channel MOS transistor 3 is also connected to the gate of the P-channel MOS transistor 4. P channel MOS transistor 4
Is connected to the voltage source VCC51, and the drain is NP.
Connected to the collector and base of N transistor 22. On the other hand, the gate of the P-channel MOS transistor 5 is also connected to the gate of the P-channel MOS transistor 6. The source of the P-channel MOS transistor 6 is connected to the voltage source VCC51, and the drain is connected to the collector of the NPN transistor 23, the resistors 34 and 35, and the buffer circuit 130. The base of the NPN transistor 22 is also connected to the base of the NPN transistor 23. NPN transistors 22 and N
The emitter of the PN transistor 23 is connected to the GND 54. The buffer circuit 130 includes the NPN transistor 24 and the constant current source 45. One ends of the resistors 34 and 35, the base of the NPN transistor 24, the drain of the P-channel MOS transistor 6, and the collector of the NPN transistor 23 are connected. Another end of the resistor 34 is connected to the voltage source VCC51, and another end of the resistor 35 is connected to the GND 54. The emitter of the NPN transistor 24 is connected to GND 54 through the OUT 55 and the constant current source 45, and the collector of the NPN transistor 24 is connected to the voltage source VCC51.

Next, the configuration of the current source circuit 350 will be described. Here, description will be made based on FIG. 2 which is a current source circuit when N is 6 in FIG. The drain and gate of the P-channel MOS transistor 1 of the gain control amplifier 100 are
It is connected to current mirror circuits 301-306. The current mirror circuits 301 to 306 each have a different line from the line connected to the gain control amplifier,
Connected to the drains of OS transistors 307-312. Also, the P-channel MOS transistors 307 to
The respective drains of 312 are connected by different lines of a six-stage current mirror circuit (generally, an N-stage current mirror circuit). Furthermore, P-channel MOS
Control terminals CTL1 to CTL6 are connected to the gates of the transistors 307 to 312 through NOT gates. The current source circuit 350 will be described in more detail. The drain and gate of the P-channel MOS transistor 1 of the gain control amplifier 100 are connected to the collectors of the NPN transistors on the current mirror circuits 301 to 306 which are not on the reference side. The emitter of this NPN transistor is connected to GND through a resistor. On the other hand, this NPN
The base of the transistor is connected to the base and collector of the reference NPN transistor, and the emitter is connected to GND through a resistor. The collector of the reference-side NPN transistor is connected to the drains of the P-channel MOS transistors 307 to 312. The sources of the P-channel MOS transistors 307 to 312 are connected to the drains of the P-channel MOS transistors 314 to 319 in the current mirror circuit 351. The gates of the P-channel MOS transistors 314 to 319 are connected to the gate and the drain of the P-channel MOS transistor 313, and the sources are connected to the voltage source VCC. The drain of the P-channel MOS transistor 313 is connected to GND through a constant current source.

Next, the operation of the embodiment of the present invention will be described with reference to FIG.
Explanation will be made based on FIG. In the embodiment of the differential amplifier and the current source circuit shown in FIGS. 1 and 2 (when N is 6), the AC signals input to the input terminal Vin1 52 and the input terminal Vin2 53 are the NPN transistor 20 and the NPN transistor 21 respectively. An AC signal current corresponding to the amplitude of the input AC signal is supplied to a base of a P-channel MOS transistor 3 and a P-channel MOS transistor 4, and a P-channel MOS transistor 5 and a P-channel MOS transistor. The signal is turned back by a current mirror circuit formed by the transistor 6 and is input to a current mirror circuit formed by the NPN transistor 22 and the NPN transistor 23. The difference between the currents of the current mirror circuit constituted by the NPN transistors becomes the input / output current to the load resistor constituted by the resistors 34 and 35, and the base of the NPN transistor 24 is provided with the amplitude of the input signal and the differential amplifier circuit. An AC amplitude corresponding to the constant current value and the load resistance value is obtained. The signal having this AC amplitude is impedance-converted by the NPN transistor 24 and then output from the output terminal OUT55. Next,
The operation of the current source circuit 350 when N is 6 will be described. When the control terminal CTL1 is High (equivalent to the VCC voltage), the P-channel MOS transistor 307 is turned ON, and a current flows to the output of the current mirror circuit 301 of the NPN transistor. Conversely, when the control terminal CTL1 is low, the P-channel MOS transistor 307 is turned off (high resistance) and the P-channel
S transistors 313 and 314 and 315 and 316
And the drain-source voltage of the P-channel MOS transistor 314 of the six-stage current mirror circuit composed of the current mirror circuit 301 and the current mirror circuit 301 of the NPN transistor has almost no influence on the others. Become smaller. Further, FIG.
In the embodiment of the control step list of the control terminal of the current source circuit, when the control step is 0, CTLs 1 and 2 and 3 and 4 and 5 and 6 are all Low, and P-channel MOS transistors 314, 315 and 316 and All gate voltages of 317, 318 and 319 are High.
h, and all the P-channel MOS transistors 30
7 to 319 are OFF, and almost no current of icon flows. By providing a MOS transistor on the reference side of the current mirror circuit in this manner, as shown in FIG. 4, the amount of increase in the output level of the gain control amplifier with respect to a constant increase in the control step of the control terminal can be reduced. Comparing with FIG. 7, which is a diagram of the control step of the terminal versus the output level of the gain control amplifier, it can be seen that they can be made substantially equal. When the control step is 1, the current of the icon becomes 2 μA, when the control step is 3, the current becomes 6 μA, and when this operation is further continued, when the control step is 63, the current becomes 126 μA. The current of the icon controlled by the control terminal is the P-channel MOS transistors 1 and 2 shown in FIG.
, And is input to the current logarithmic conversion circuit 120, and the logarithmically converted current becomes a current source for controlling the gain of the differential amplifier.

In the current source circuit and the gain control amplifier of the present invention described above, the current source circuit is provided with a MOS transistor on the reference side of the current mirror circuit.
It becomes possible to make the current independent of the ON resistance of the MOS transistor, and to reduce the variation in the increase in the output level of the gain control amplifier with respect to a fixed increase in the control step of the control terminal as shown in FIG. Can be. Furthermore, the output current of each current mirror circuit operated by N control signals from the outside is not connected by a single line, and the differential amplifier circuit has a one-stage configuration instead of a multi-stage configuration as in the prior art. The variable gain that controls the constant current value of the amplifier circuit makes it possible to ease the limitation of the input / output signal level due to the dynamic range of the input / output signal compared to the past, and the maximum amplitude of the gain control amplifier can be increased compared to the past. Thus, control for obtaining a stable output becomes possible.
Further, it is possible to suppress the relative variation of the gain of the gain control amplifier.

Second Embodiment FIG. 5 is a circuit diagram of a current source circuit and a gain control amplifier according to a second embodiment of the present invention where N is an arbitrary natural number. The configuration of the second embodiment of the present invention will be described with reference to FIG.
The configuration of the gain control amplifier 400 will be described. Current source circuit 5
00 is directly connected to the current logarithmic conversion circuit 420.
Connected to. The current mirror circuit including the P-channel MOS transistors 1 and 2 according to the first embodiment does not exist in the circuit according to the second embodiment. Other configurations of the gain control amplifier 400 of the second embodiment are the same as those of the gain control amplifier 100 of the first embodiment. Next, the configuration of the current source circuit 500 will be described. N-channel MOS
The N-channel MOS transistor of the N-stage current mirror circuit 510 having N-stage transistors has a source connected to GND and a drain connected to the drain of a P-channel MOS transistor connected to the control terminal. Furthermore, the P connected to the control terminal
The source of the channel MOS transistor has two PNs.
One for each P transistor and each PNP transistor
Each of the resistors is connected to a reference-side collector of a current mirror circuit configured by connecting the resistors. The other end of the resistance of the current mirror having the PNP transistor connected to the PNP transistor is connected to the voltage source VCC. Other Current Source Circuit 50 of Second Embodiment
The configuration of 0 is equal to the configuration of the current source circuit 200 of the first embodiment.

Next, the operation of the second embodiment of the present invention will be described. In the first embodiment, the current of icont input to the current logarithmic conversion circuit 120 is turned back by the current mirror circuit including the P-channel MOS transistors 1 and 2, but in the second embodiment, the current is turned back by the current mirror circuit. Therefore, the icont current flows directly to the reference side of the current logarithmic conversion circuit 420. The operation according to the other configuration is the same as that of the first embodiment.

In the current source circuit and the gain control amplifier of the present invention described above, since the current flows directly from the current source circuit to the current logarithmic conversion circuit of the gain control amplifier, the P-channel MOS transistors 1 and 2 of the first embodiment are used. Of the current mirror circuit constituted by the current mirror circuit is reduced, and the current consumption by this current can be suppressed. Other configurations and operations and effects of the configurations are the same as those of the first embodiment.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a current source circuit and a gain control amplifier according to an embodiment of the present invention, where N is an arbitrary natural number.

FIG. 2 is a circuit diagram of a current source circuit according to an embodiment when N is 6 in the present invention.

FIG. 3 is a control step list of control terminals of a current source circuit according to an embodiment of the present invention.

FIG. 4 is a diagram illustrating a control step of a control terminal and an output level of a gain control amplifier according to an embodiment of the present invention.

FIG. 5 is a circuit diagram of a current source circuit and a gain control amplifier according to a second embodiment of the present invention, where N is an arbitrary natural number.

FIG. 6 is a circuit diagram of a conventional gain control amplifier.

FIG. 7 shows a control step of a control terminal in a conventional example.
It is a figure of the gain control amplifier output level.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 Gain control amplifier 110 Differential amplifier circuit 120 Current logarithmic conversion circuit 130 Buffer circuit 200 Current source circuit 210 N-stage current mirror circuit

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[Procedure amendment]

[Submission date] October 28, 1999 (1999.10.
28)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Full text

[Correction method] Change

[Correction contents]

[Document Name] Statement

Patent application title: Current source circuit and gain control amplifier

[Claims]

4. A reference side of the current mirror circuit, M
Output of current mirror circuit composed of OS transistor
And the MOS transistors are connected in series between
The electronic device according to claim 1 or 2, wherein
Source circuit.

6. A reference side of the current mirror circuit, M
Output of current mirror circuit composed of OS transistor
And the MOS transistors are connected in series between
6. The gain control amplification according to claim 5, wherein
vessel.

7. The output-side current of the respective current mirror circuit which operates by N control signals from the outside, the gain control amplifier according to claim 5, characterized in that formed by connecting a single line.

8. An input terminal for inputting AC power,
A differential amplifier circuit that receives power from the two input terminals, amplifies and outputs a difference between voltages applied between the input terminals, and a constant current of the differential amplifier circuit that is connected to an emitter side of the differential amplifier circuit. A current logarithmic conversion circuit that converts a current into a logarithm, a current mirror circuit that controls a current input to the current logarithmic conversion circuit, two current mirror circuits that respectively control two output signals from the differential amplifier circuit, The other terminals of the two current mirror circuits connected to the output terminal of the differential amplifier circuit are connected to each other to connect the two current mirror circuits.
A current mirror circuit for controlling the output signal of Ntomira circuit, a load resistor and a buffer circuit gain settings for connecting the output terminal of the current mirror circuit, a differential amplifier having a current logarithmic converter of the differential amplifier N (N is a natural number) constant current setting current mirror circuits connected to the reference side of the current mirror circuit connected to the reference side, and the reference side current paths of the respective constant current setting current mirror circuits in series a MOS transistor connected to a N-stage structure a current mirror circuit connected with each of the MOS transistors, be made having a control terminal connected to the each of the MOS transistors, a current source circuit having, a Current source circuit and
And gain control amplifier .

9. N pieces of the constant current setting current mirror times
The current consisting of each reference side of the path and the MOS transistor
Between the output of the mirror circuit and the MOS transistor
9. The device according to claim 8, wherein the components are connected in series.
Current source circuit and gain control amplifier .

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for inputting, amplifying and outputting power, and more particularly to a circuit using a differential amplifier circuit.

[0002]

2. Description of the Related Art Generally, in order to input a certain value of power and to enable the amplification of the power, it is necessary to have an amplifier circuit in an electric circuit, and it is more stable to reduce the gain fluctuation of the amplifier. Necessary for amplifier circuits.

An example of a conventional gain control amplifier will be described with reference to FIGS. FIG. 6 is a circuit diagram of a conventional gain control amplifier. FIG. 7 is a diagram showing the control step of the control terminal versus the output level of the gain control amplifier in the conventional example.

FIG. 6 shows an example of a configuration of a conventional gain control amplifier.
It will be described based on. NPN to input terminal IN1 701
The base of the transistor 711 is connected, and the input terminal IN2
The base of an NPN transistor 712 is connected to 702, the emitters of the NPN transistors are connected to each other, and the emitters are connected to the collectors of another two NPN transistors 722 and 723. An NPN transistor 722, which is one of the two NPN transistors, is an NPN transistor 72 having a reference side forming a part of a current mirror circuit.
1 and a current mirror circuit, the NPN transistor 721 and the base are connected to each other, and the emitter is connected to the drain of the N-channel MOS transistor 732. The emitter of NPN transistor 721 is connected to the drain of N-channel MOS transistor 731,
The gate of the channel MOS transistor 731 is connected to the gate of the N-channel MOS transistor 732. The other NPN transistor 723 has a base connected to the base of the previous NPN transistor 722, an emitter connected to the drain of the N-channel MOS transistor 733, and
The control terminal CTL1 741 is connected to the gate of 33. Further, the collector of the NPN transistor 711 is connected to the base of the NPN transistor 713 and the resistor 75.
1 is connected. Another end of the resistor 751 is connected to a voltage source VC.
It is connected to C705. The collector of the NPN transistor 712 is connected to the base of the NPN transistor 714 and the resistor 752. Another end of the resistor 752 is connected to the voltage source VCC 705.

The connection of the NPN transistor 713 and the emitter and collector of the NPN transistor 714
The connection is the same as that of the NPN transistor 711 and the emitter and collector of the NPN transistor 712, respectively. That is, the resistor 751 is replaced by the resistor 753,
2 to the resistor 754, and the NPN transistor 722 to the NPN
The NPN transistor 723 is set to N
An N-channel MOS transistor 732 is replaced with an N-channel MOS transistor 734
And the N-channel MOS transistor 733 to the N-channel MOS transistor 735 and the control terminal C
When the TL1 741 is converted to the control terminal CTL2 742, the connection becomes the same as the connection between the NPN transistor 711 and the NPN transistor 712. Regarding the connection with other elements of the other NPN transistors 715 and 716, the NPN transistors 713 and NP
The N transistor 714 and the NPN transistor 7
15 and the output terminal OUT2 70 of the NPN transistor 716.
Exactly the same except 4 is connected. In addition, differential amplifier circuits 711 and 71 composed of respective NPN transistors
The gains of 2, 713, 714, 715, and 716 are arbitrarily set by setting the current value of a current mirror circuit serving as a constant current source.

In the conventional gain control amplifier having the above configuration, since the differential amplifier circuit has a multi-stage configuration, the gain variation of the differential amplifier at each stage is directly reflected on the relative variation of the gain. The switch of the N-channel MOS transistor uses the ON resistance when the N-channel MOS transistor is ON as a feedback resistance of the current mirror, and the ON resistance value of the N-channel MOS transistor contributes to the gain of the differential amplifier. For this reason, gain fluctuation is likely to occur due to variations in output of the N-channel MOS transistor and temperature dependency. The main effect of these two factors is that the increase in the gain control amplifier output level with respect to the increase in the control terminal control step becomes unstable in the control terminal control step vs. gain control amplifier output level diagram in FIG. appear. As a result, control for obtaining a stable output cannot be executed. In addition, in order to obtain a signal having no distortion in the output, the amplitude level of the input signal must be limited so as to be within the input dynamic range of the final stage of the cascade-connected amplifiers. Since the input dynamic range of the amplifier is insufficient, the signal is distorted there. Further, at a low power supply voltage, there is a problem that the output amplitude of the gain control amplifier is easily restricted in order to prevent the transistor from being saturated due to the voltage drop of the load resistance of the differential amplifier.

To solve some of the above problems, Japanese Patent Application Laid-Open No. 3-228412 discloses an output current of a hyperbolic characteristic and a square-wave dual-rectification characteristic by a differential pair using bipolar transistors and MOS transistors having different sizes. It is said that the accuracy of the logarithmic amplifier can be improved by adding a load to the output and connecting a load resistor.

[0008]

However, Japanese Patent Application Laid-Open No. Hei 3-2
No. 28412 can certainly improve the accuracy of the logarithmic amplifier circuit, operate from a low voltage and have a wide dynamic range, but the multi-stage configuration of the bipolar transistor differential amplifier circuit and the MOS transistor differential amplifier circuit is possible. Therefore, it is difficult to stabilize the increase in the output level of the gain control amplifier with respect to the increase in the control step of the control terminal due to variations in the quality of the transistors and the like. Therefore, a differential amplifier that has a stable increase in the output level of the gain control amplifier with respect to the increase in the control step of the control terminal, obtains a signal without distortion in the output, and is not easily limited by the output amplitude of the gain control amplifier. It is hard to recognize that it is possible.

In order to solve these problems, the present invention provides:
It is possible to make the amount of increase in the output level of the gain control amplifier substantially equal to the fixed amount of increase in the control step of the control terminal.
The state can be made independent of the ON resistance of the S-transistor, and the relative variation in the gain of the gain control amplifier can be suppressed. In addition, the limitation of the input / output signal level due to the dynamic range of the input / output signal is eased as compared with the conventional case. It is an object of the present invention to provide a current source circuit and a gain control amplifier capable of performing control to obtain a stable output.

[0010]

According to a first aspect of the present invention, there is provided a current source circuit in which a MOS transistor is provided in series on a reference side current path of a current mirror circuit. Features.

Therefore, according to the current source circuit of the first invention of the present application, in the current source circuit, by providing the MOS transistor in series on the reference side current path of the current mirror circuit, the current is turned on by the MOS transistor. It becomes possible not to depend on the resistance, and it is possible to reduce the variation in the amount of increase in the output level of the gain control amplifier with respect to a certain amount of increase in the control step of the control terminal.

In the current source circuit according to the second aspect of the present invention, a drain of a P-channel MOS transistor is connected in series to a current path of a line connecting a base and a collector of a transistor in a current mirror circuit. It is characterized by.

Therefore, according to the current source circuit of the second invention of the present application, the P channel is connected to the current path of the line connecting the base and the collector of the transistor in the current mirror circuit.
By connecting the drains of the MOS transistors in series , the current can be made independent of the ON resistance of the MOS transistor, and the output of the gain control amplifier for a certain amount of increase in the control step of the control terminal can be increased. Variations in the level increase can be reduced.

According to a third aspect of the present invention, in the current source circuit according to the first or second aspect of the present invention, the emitter resistance of the current mirror circuit of the current source circuit includes a resistance element.

Therefore, according to the current source circuit of the third invention of the present application, since the emitter resistance of the current mirror circuit of the current source circuit includes a resistance element, the desired current ratio can be set by the ON resistance of the MOS transistor. It becomes possible not to depend on.

The current source circuit of the present application the fourth invention, the present application
In the current source circuit according to the first or second aspect of the present invention,
Whether the reference side of the current mirror circuit and the MOS transistor
Between the output of the current mirror circuit
Characterized in that transistors are connected in series
You.

[0017] Thus, the current source times of the application fourth invention
According to the path, the current depends on the ON resistance of the MOS transistor.
Control end.
Gain control amplification for a constant increment of the control step
Can reduce variations in the output level of the
You. Furthermore, the relative variation in the gain of the gain control amplifier
Control to obtain stable output.
It will work.

The gain control amplifier of the present application the fifth invention, in the gain control amplifier, and wherein the forming provided MOS transistor in series with the reference side current path of the current mirror circuit of the current source circuit.

[0019] Thus, according to the gain control amplifier of the present application the fifth invention, in the gain control amplifier, by forming provided MOS transistor in series with the reference side current path of the current mirror circuit of the current source circuit, the current It becomes possible not to depend on the ON resistance of the MOS transistor, and it is possible to reduce the variation in the amount of increase in the output level of the gain control amplifier with respect to a certain amount of increase in the control step of the control terminal. Furthermore, it is possible to suppress the relative variation of the gain of the gain control amplifier, and control to obtain a stable output becomes possible.

[0020] This application sixth aspect of the present invention, the present application fifth invention
In the gain control amplifier, the base of the current mirror circuit is used.
Current mirror circuit consisting of the quasi side and MOS transistor
The MOS transistor is connected in series between the output of the
It is characterized by being continued .

[0021] Thus, according to the gain control amplifier of the present application sixth aspect, ON resistance of the current MOS transistor
Can be made independent of
Control for a fixed increment of the control step of the terminal
It is possible to reduce the variation in the amount of increase in the amplifier output level.
it can. Also, the relative variation of the gain of the gain control amplifier
Control to obtain stable output
Becomes possible.

According to a seventh aspect of the present invention, in the gain control amplifier according to the fifth aspect of the present invention, the output side currents of the respective current mirror circuits operated by N control signals from the outside are connected by a single line. It is characterized by entertaining.

[0023] Thus, according to the gain control amplifier of the present application seventh invention, the output-side current of the respective current mirror circuit which operates by N control signals from the outside, by forming connected by a single line , It is easy to monotonously increase the gain of the gain control amplifier.

The current source circuit and gain system of the present application eighth aspect of
The control amplifier includes two input terminals for inputting AC power, a differential amplifier circuit that receives power from the two input terminals, amplifies and outputs a difference between voltages applied between the input terminals, and the differential amplifier circuit. A current logarithmic converter connected to the emitter side of the differential amplifier to convert a constant current of the differential amplifier into a logarithm; a current mirror circuit controlling a current input to the current logarithmic converter; Two current mirror circuits respectively controlling two output signals, and two different current mirror circuits connected to output terminals of the differential amplifier circuit, respectively, to connect two different current mirror circuits.
A current mirror circuit for controlling the output signal of Ntomira circuit, a load resistor and a buffer circuit gain settings for connecting the output terminal of the current mirror circuit, a differential amplifier having a current logarithmic converter of the differential amplifier N (N is a natural number) constant current setting current mirror circuits connected to the reference side of the current mirror circuit connected to the reference side, and the reference side current paths of the respective constant current setting current mirror circuits in series a MOS transistor connected to a N-stage structure a current mirror circuit connected with each of the MOS transistors, be made having a control terminal connected to the each of the MOS transistors, a current source circuit having, a It is characterized by.

[0025] Thus, the current source times of the invention of this application eighth
According to the circuit and the gain control amplifier , the load resistance between
It can be driven by the output current source circuit of the current mirror.
And therefore depends on the dynamic range of the input / output signals.
I / O signal level restrictions can be more relaxed than before.
Function and further increase the maximum amplitude of the gain control amplifier
Control can be performed to obtain a stable output.
Further, it is possible to reduce the variation in the amount of increase in the output level of the gain control amplifier with respect to a certain amount of increase in the control step of the control terminal.
It is possible to make the state independent of the ON resistance of the transistor.

The current source circuit and the gain control of the ninth invention of the present application
The control amplifier includes N constant current setting current mirror circuits.
Current reference composed of MOS transistors
The MOS transistor is directly connected between the output of the
It is characterized by being connected to a column.

Therefore, the current source circuit of the ninth invention of the present application is
According to the circuit and the gain control amplifier, the current is
It is possible not to depend on the ON resistance of the
To a certain increase in the control step of the control terminal.
Variation in the gain control amplifier output level
Can be reduced. In addition, the gain of the gain control amplifier
It is possible to suppress the relative variation, and stable
Control to obtain an output becomes possible.

[0028]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention and the method will be described below with reference to FIGS.

[0029] First Embodiment FIG. 1 is a circuit diagram of a current source circuit and the gain control amplifier of one embodiment of N is any natural number in the present invention. FIG. 2 is a circuit diagram of a current source circuit according to one embodiment when N is 6 in the present invention. FIG. 3 is a list of control steps of the control terminal of the current source circuit according to one embodiment of the present invention. FIG. 4 is a diagram showing a control step of a control terminal and an output level of a gain control amplifier according to an embodiment of the present invention. Hereinafter, the first embodiment in which N is 6 in the current source circuit will be described. In the present invention, it is possible to take an arbitrary natural number as N. In this case, the configuration and operation of the present invention will be described by converting the quantity 6 into an arbitrary natural number N in the following description.

[0030] be described with reference to the configuration of the first embodiment of the present invention in FIGS. The configuration of the gain control amplifier 100 will be described. The input terminal Vin1 52 and the input terminal Vin
253 each constituting the differential amplifier circuit 110
The bases of the PN transistor 20 and the NPN transistor 21 are connected to each other, the emitters of the NPN transistors are connected to each other, and the emitters are connected to another two NP transistors.
It is connected to the collectors of the N transistor 17 and the NPN transistor 19. An NPN transistor 19, one of the two NPN transistors, forms a current logarithmic conversion circuit 120 with an NPN transistor 18 having a reference side forming a part of the current logarithmic conversion circuit 120.
The NPN transistor 18 and the base are connected to each other, and the emitter is connected to the GND 54. The emitter of the NPN transistor 18 is connected to the resistor 33, and another end of the resistor 33 is connected to GND 54. Further, the base of the NPN transistor 18 is also connected to the collector of the NPN transistor 18. The NPN transistor 18
Is connected to the drain of the P-channel MOS transistor 2, and the gate of the P-channel MOS transistor 2 is connected to the gate of the P-channel MOS transistor 1 and the drain of the P-channel MOS transistor 1. The sources of the P-channel MOS transistor 1 and the P-channel MOS transistor 2 are connected to a voltage source VC.
Connected to C51. On the other hand, the drain of the P-channel MOS transistor 1 is connected to the current source circuit 200. The NPN transistor 17 has a base connected to the base and the collector of the NPN transistor 16, and an emitter connected to the GND 54. NPN transistor 16
Has an emitter connected to the GND 54 and a collector connected to the voltage source VCC 51 through the constant current source 44. Further, the collector of the NPN transistor 20 is connected to the drain and the gate of the P-channel MOS transistor 3. The source of the P-channel MOS transistor 3 is
It is connected to the voltage source VCC51. The collector of the NPN transistor 21 is connected to the drain and the gate of the P-channel MOS transistor 5. The source of the P-channel MOS transistor 5 is a voltage source VCC 51
Connected to. The gate of the P-channel MOS transistor 3 is also connected to the gate of the P-channel MOS transistor 4. P channel MOS transistor 4
Is connected to the voltage source VCC51, and the drain is NP.
Connected to the collector and base of N transistor 22. On the other hand, the gate of the P-channel MOS transistor 5 is also connected to the gate of the P-channel MOS transistor 6. The source of the P-channel MOS transistor 6 is connected to the voltage source VCC51, and the drain is connected to the collector of the NPN transistor 23, the resistors 34 and 35, and the buffer circuit 130. The base of the NPN transistor 22 is also connected to the base of the NPN transistor 23. NPN transistors 22 and N
The emitter of the PN transistor 23 is connected to the GND 54. The buffer circuit 130 includes the NPN transistor 24 and the constant current source 45. One ends of the resistors 34 and 35, the base of the NPN transistor 24, the drain of the P-channel MOS transistor 6, and the collector of the NPN transistor 23 are connected. Another end of the resistor 34 is connected to the voltage source VCC51, and another end of the resistor 35 is connected to the GND 54. The emitter of the NPN transistor 24 is connected to GND 54 through the OUT 55 and the constant current source 45, and the collector of the NPN transistor 24 is connected to the voltage source VCC51.

[0031] Next, the configuration of the current source circuit 350. Here, description will be made based on FIG. 2 which is a current source circuit when N is 6 in FIG. The drain and gate of the P-channel MOS transistor 1 of the gain control amplifier 100 are
It is connected to current mirror circuits 301-306. The current mirror circuits 301 to 306 each have a different line from the line connected to the gain control amplifier,
Connected to the drains of OS transistors 307-312 . Sarah, P-channel MOS transistor 307 to
The gate of 312, a control terminal CTL1~6 Through a NOT gate is connected. The current source circuit 350 will be described in more detail. The drain and gate of the P-channel MOS transistor 1 of the gain control amplifier 100 are connected to the collectors of the NPN transistors on the current mirror circuits 301 to 306 which are not on the reference side. The emitter of this NPN transistor is connected to GND through a resistor. On the other hand, the base of this NPN transistor is connected to the base and collector of the reference-side NPN transistor, and the emitter is connected to GND through a resistor. The collector of the reference NPN transistor is
It is connected to the drains of P-channel MOS transistors 307 to 312. The sources of the P-channel MOS transistors 307 to 312 are connected to the current mirror circuit 351.
Connected to the drains of P-channel MOS transistors 314 to 319 in the inside. The gates of the P-channel MOS transistors 314 to 319 are connected to the gate and the drain of the P-channel MOS transistor 313, and the sources are connected to the voltage source VCC. The drain of the P-channel MOS transistor 313 is connected to GND through a constant current source.

Next, FIG. 1 the operation of the embodiment of the present invention
Explanation will be made based on FIG. In Figure 1 and the differential amplifier and the current source circuits of FIG. 2 (if N is 6), the input terminal Vin
The AC signal input to the input terminal 52 and the input terminal Vin2 53 is input to the bases of the NPN transistor 20 and the NPN transistor 21, respectively. The AC signal current corresponding to the amplitude of the input AC signal is converted to a P-channel MOS.
Transistor 3 and P-channel MOS transistor 4
And a P-channel M
Folded by a current mirror circuit composed of an OS transistor 5 and a P-channel MOS transistor 6,
It is input to a current mirror circuit composed of a PN transistor 22 and an NPN transistor 23. This NPN
The difference between the currents of the current mirror circuit constituted by the transistors becomes the input / output current to the load resistor constituted by the resistor 34 and the resistor 35, and the amplitude of the input signal and the constant current of the differential amplifier circuit are provided at the base of the NPN transistor 24. An AC amplitude corresponding to the value and the load resistance value is obtained. The signal having this AC amplitude is impedance-converted by the NPN transistor 24 and then output from the output terminal OUT55. Next, the operation of the current source circuit 350 when N is 6 will be described.
When the control terminal CTL1 is High (corresponding to the VCC voltage), the P-channel MOS transistor 307 is
N, the current mirror circuit 3 of the NPN transistor
A current flows to the output of No. 01. Conversely, control terminal C
When TL1 is Low, the P-channel MOS transistor 307 becomes OFF (high resistance) and the P-channel MOS transistor
P-channel MOS transistor 3 of a six-stage current mirror circuit composed of transistors 313 and 314 and 315 and 316 and 317 and 318 and 319
Since the drain-source voltage of the NPN transistor 14 disappears, the output current of the current mirror circuit 301 of the NPN transistor is reduced to such an extent that it hardly affects the other components. Further, in the control step a list of the control terminal of the current source circuit of FIG. 3,
If the control step is 0, CTLs 1 and 2 and 3 and 4
, And 5 and 6 are all Low and P-channel MOS
All the gate voltages of the transistors 314 and 315 and 316 and 317 and 318 and 319 become High,
All P-channel MOS transistors 307 to 319
Is turned off, and almost no current of icon flows. By providing the MOS transistors in series on the reference side current path of the current mirror circuit in this manner, as shown in FIG. 4, the amount of increase in the output level of the gain control amplifier with respect to a constant increase in the control step of the control terminal is reduced. Comparing with FIG. 7, which is a diagram of the control step of the control terminal of the conventional example versus the output level of the gain control amplifier, it can be seen that they can be made substantially equal. When the control step is 1, the current of the icon becomes 2 μA, when the control step is 3, the current becomes 6 μA, and when this operation is further continued, when the control step is 63, the current becomes 126 μA. The current of the icon controlled by the control terminal is the P-channel MOS transistors 1 and 2 shown in FIG.
, And is input to the current logarithmic conversion circuit 120, and the logarithmically converted current becomes a current source for controlling the gain of the differential amplifier.

In the current source circuit and the gain control amplifier of the present invention described above, in the current source circuit 350 , the MOS transistors (307 to 312) are provided in the reference current paths of the current mirror circuits (301 to 306) . By providing in series , the current is reduced by the ON resistance of the MOS transistor (307 to
312) , it is possible to reduce variation in the amount of increase in the output level of the gain control amplifier with respect to a certain amount of increase in the control step of the control terminal, as shown in FIG. In addition, N
The output currents of the respective current mirror circuits operated by the control signals (CTL1 to CTLN) are not connected by a single line, and the differential amplifier circuit has a single-stage configuration instead of a multistage configuration as in the related art. The variable gain that controls the constant current value of the circuit makes it possible to relax the limitation of the input / output signal level due to the dynamic range of the input / output signal as compared to the past, and the maximum amplitude of the gain control amplifier can be increased compared to the past. Control to obtain a stable output becomes possible. Further, it is possible to suppress the relative variation of the gain of the gain control amplifier.

[0034] Second Embodiment FIG. 5 is a circuit diagram of a N is an arbitrary natural number of a current source circuit of the second embodiment and the gain control amplifier of the present invention. The configuration of the second embodiment of the present invention will be described with reference to FIG.
The configuration of the gain control amplifier 400 will be described. Current source circuit 5
00 is directly connected to the current logarithmic conversion circuit 420.
Connected to. The current mirror circuit including the P-channel MOS transistors 1 and 2 according to the first embodiment does not exist in the circuit according to the second embodiment. Other configurations of the gain control amplifier 400 of the second embodiment are the same as those of the gain control amplifier 100 of the first embodiment. Next, the configuration of the current source circuit 500 will be described. N-channel MOS
The N-channel MOS transistor of the N-stage current mirror circuit 510 having N-stage transistors has a source connected to GND and a drain connected to the drain of a P-channel MOS transistor connected to the control terminal. Furthermore, the P connected to the control terminal
The source of the channel MOS transistor has two PNs.
One for each P transistor and each PNP transistor
Each of the resistors is connected to a reference-side collector of a current mirror circuit configured by connecting the resistors. The other end of the resistance of the current mirror having the PNP transistor connected to the PNP transistor is connected to the voltage source VCC. Other Current Source Circuit 50 of Second Embodiment
The configuration of 0 is equal to the configuration of the current source circuit 200 of the first embodiment.

[0035] Next, the operation of the second embodiment of the present invention. In the first embodiment, the current of icont input to the current logarithmic conversion circuit 120 is turned back by the current mirror circuit including the P-channel MOS transistors 1 and 2, but in the second embodiment, the current is turned back by the current mirror circuit. Therefore, the icont current flows directly to the reference side of the current logarithmic conversion circuit 420. The operation according to the other configuration is the same as that of the first embodiment.

In the current source circuit and the gain control amplifier of the present invention described above, since the current flows directly from the current source circuit to the current logarithmic conversion circuit of the gain control amplifier, the P-channel MOS transistors 1 and 2 in the first embodiment are used. Of the current mirror circuit constituted by the current mirror circuit is reduced, and the current consumption by this current can be suppressed. Other configurations and operations and effects of the configurations are the same as those of the first embodiment.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a current source circuit and a gain control amplifier according to an embodiment of the present invention, where N is an arbitrary natural number.

FIG. 2 is a circuit diagram of a current source circuit according to an embodiment when N is 6 in the present invention.

FIG. 3 is a control step list of control terminals of a current source circuit according to an embodiment of the present invention.

FIG. 4 is a diagram illustrating a control step of a control terminal and an output level of a gain control amplifier according to an embodiment of the present invention.

FIG. 5 is a circuit diagram of a current source circuit and a gain control amplifier according to a second embodiment of the present invention, where N is an arbitrary natural number.

FIG. 6 is a circuit diagram of a conventional gain control amplifier.

FIG. 7 shows a control step of a control terminal in a conventional example.
It is a figure of the gain control amplifier output level.

[Description of Signs] 100 Gain control amplifier 110 Differential amplifier circuit 120 Current logarithmic conversion circuit 130 Buffer circuit 200 Current source circuit 210 N-stage current mirror circuit

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5J066 AA01 AA12 CA15 CA32 CA88 FA20 HA02 HA08 HA10 HA17 HA18 HA25 KA00 KA02 KA03 KA05 KA06 KA09 MA08 ND01 ND11 ND22 ND23 PD02 TA02 5J091 AA01 AA12 CA15 CA32 HA08 HA17 HA25 KA00 KA02 KA03 KA05 KA06 KA09 MA08 TA02

Claims (7)

[Claims] 1. A current source circuit comprising a MOS transistor provided on a reference side of a current mirror circuit in a current source circuit. 2. The current source circuit according to claim 1, wherein a MOS transistor is connected to a line connecting a base and a collector of the transistor in the current mirror circuit. 3. The current source circuit according to claim 1, wherein the emitter resistance of the current mirror circuit of the current source circuit includes a resistance element. 4. A gain control amplifier, wherein a MOS transistor is provided on a reference side of a current mirror circuit of a current source circuit. 5. The gain control amplifier according to claim 4, wherein the output currents of the respective current mirror circuits operated by N control signals from the outside are connected by a single line. 6. An input terminal for inputting AC power,
A differential amplifier circuit that receives power from the two input terminals, amplifies and outputs a difference between voltages applied between the input terminals, and a constant current of the differential amplifier circuit that is connected to an emitter side of the differential amplifier circuit. A current logarithmic conversion circuit for converting a current into a logarithm, a current mirror circuit for controlling a current input to the current logarithmic conversion circuit, two current mirror circuits for controlling two output signals from the differential amplifier circuit, respectively, A current mirror circuit for controlling signals by connecting different terminals of the two current mirror circuits connected to the output terminal of the differential amplifier circuit, and a gain setting for connecting to the output terminal of the current mirror circuit. A load resistor and a buffer circuit;
A gain control amplifier comprising: a differential amplifier having: 7. N (N is a natural number) constant current setting current mirror circuits connected to a reference side of a current mirror circuit connected to a reference side of a current logarithmic conversion circuit of the differential amplifier, respectively. A MOS transistor connected to the reference side of the constant current setting current mirror circuit, an N-stage current mirror circuit connected to each MOS transistor, and a control terminal connected to each MOS transistor. 7. The gain control amplifier according to claim 6, further comprising a current source circuit.