JP2000122893A - Logic integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a microcontroller, etc., which is provided with an evaluation chip incorporating a dynamic RAM as a substitute memory of a read only memory and performs perfect emulation and also to provide an effective accessing method and refreshing method for the dynamic RAM, etc., provided as the substitute memory of the read only memory. SOLUTION: A memory controller ROMC that includes an address comparator circuit ADDC which holds a previously accessed row address in a bus status controller BSC of a logic integrated circuit device such as a microcontroller and compares and collates it with a row address to be next accessed and a pseudo-refresh controller RFCP which generates a pseudo-refresh request signal RFQP in the same cycle as a dynamic RAM provided in an evaluation chip are provided, and the bus status controller BSC is made to have a function which makes the number of access cycles of a read only memory ROM incorporated in a product chip coincide with the access cycle of the dynamic RAM of the evaluation chip.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic integrated circuit device, for example, a microcontroller having an evaluation chip (evaluation chip) having a built-in read-only memory and a dynamic RAM (random access memory) as a substitute memory. In addition, the present invention relates to a technology that is particularly effective for realizing the complete emulation.

[0002]

2. Description of the Related Art A central processing unit (central processing unit / CPU) of a stored program system and a read only memory such as a mask ROM, a flash memory, and an EEPROM for storing a control program for controlling the operation of the central processing unit and fixed data. There is a single-chip microcontroller in which a memory (read only memory) is mounted on the same chip. In these microcontrollers and the like, so-called emulation for replacing a read-only memory with a rewritable random access memory and debugging a control program and checking the performance of a system including the microcontroller is generally performed.

[0003]

Prior to the present invention, the present inventors have developed a microcontroller having a read-only memory as described above, and have noticed the following problems in emulating the microcontroller. That is, in this microcontroller, an evaluation chip having a built-in static RAM as a substitute for the read-only memory is prepared for the emulation.
A static RAM requires a relatively large layout area and consumes a relatively large amount of power, so it has to be provided outside the evaluation chip. As is well known, in recent years, the performance of digital systems has been remarkably improved, and the machine cycle of a microcontroller has been constantly increasing. For this reason, when a static RAM serving as a substitute memory for the read-only memory is provided outside the evaluation chip as described above, the high-speed operation of the microcontroller is hindered by the parasitic capacitance of the connection path and the like, and the operation in a prescribed machine cycle Emulation has become difficult to implement.

In order to cope with this, the present inventors have considered to incorporate a dynamic RAM, which is rewritable, requires a small layout area and consumes low power, in an evaluation chip as an alternative memory to a read-only memory.
However, as is well known, a dynamic RAM is different from a read-only memory in a combination of activation control signals, and requires a refresh cycle at a predetermined cycle. The bus access cycle differs from that of an evaluation chip having a built-in RAM. As a result, although the problem of external memory replacement is solved,
A complete emulation cannot be performed in a specified machine cycle, and a sufficient evaluation result cannot be obtained.

An object of the present invention is to provide a dynamic RAM
It is an object of the present invention to provide a logic integrated circuit device such as a microcontroller or the like, which is provided with an evaluation chip which incorporates a memory as a substitute memory for a read-only memory and is capable of complete emulation. Another object of the present invention is to provide an effective access method and refresh method for a dynamic RAM provided as a substitute memory for a read-only memory.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0007]

The following is a brief description of an outline of typical inventions disclosed in the present application. That is, the number of access cycles of the read-only memory built in the product chip of the logic integrated circuit device such as the microcontroller is substantially the same as the number of access cycles of the dynamic RAM built in the evaluation chip as a substitute memory for the read-only memory. It is configured so that

For this reason, the dynamic RAM incorporated in the evaluation chip is set to a so-called RAS down state in which the previously accessed row address is kept in a selected state and the so-called RAS down state is set. A bus status controller including an address comparison circuit for holding and comparing this row address with a portion corresponding to the row address among addresses output at the next access is provided, and an address similar to the bus status controller of the product chip is provided. A comparison circuit is provided to extend the access cycle to the read-only memory for a predetermined period when a row address mis-hits.

The bus status controller of the evaluation chip is provided with a refresh controller for executing a refresh cycle of the dynamic RAM at a predetermined cycle, and the bus status controller of the product chip is also provided with a pseudo refresh at the predetermined cycle. A pseudo refresh controller for generating a request signal is provided. Then, the bus status controllers of the product chip and the evaluation chip receive the refresh request signal or the pseudo refresh request signal prior to the access to the read-only memory or the dynamic RAM, and the bus status controller of the product chip transmits the pseudo refresh signal. When the request signal is set to the valid level, a function is provided to extend the access cycle to the read-only memory by a period necessary for refreshing the dynamic RAM.

[0010] Further, the bus status controller of the product chip and the evaluation chip receives access to the read-only memory or the dynamic RAM in preference to the refresh request signal or the pseudo refresh request signal. In addition, a function to execute the waiting refresh cycle while another bus command other than the dynamic RAM is executed or the bus command is not executed is provided. At this time, the generation cycle of the refresh request signal or the pseudo refresh request signal is set shorter than the prescribed refresh cycle of the dynamic RAM.

In addition, the dynamic RA of the evaluation chip
M is provided with a plurality of banks which are placed in a standby state while different row addresses are kept in a selected state, and which are alternatively specified by setting a corresponding row address strobe signal to a valid level.

According to the above-mentioned means, the configuration is such that the access cycle of the product chip to the read-only memory and the access cycle of the evaluation chip to the dynamic RAM are substantially the same number of cycles. Full emulation in cycles can be realized.

For this reason, the dynamic type R of the evaluation chip
By setting the AM to the RAS down state during standby, a dynamic RAM requiring a row address cycle and a column address cycle can be accessed in one cycle, and an address comparison circuit is provided in a bus status controller of a product chip. By providing a function of extending the access cycle to the read-only memory at the time of a mishit, by a predetermined period, the access cycle to the read-only memory of the product chip and the access cycle to the dynamic RAM of the evaluation chip are substantially the same as described above. It can be the number of cycles.

A pseudo refresh controller is provided in a bus status controller of a product chip, and a function of extending an access cycle to a read-only memory for a predetermined period when a pseudo refresh request signal is set to an effective level is provided. Dynamic RA requiring access cycle to read-only memory and refresh cycle of evaluation chip
The number of access cycles to M can be substantially the same as described above.

Further, an access to the read-only memory or the dynamic RAM is accepted prior to a refresh request signal or a pseudo refresh request signal,
The awaited refresh cycle is executed while another bus command other than the dynamic RAM is executed or the bus command is not executed, and the generation cycle of the refresh request signal or the pseudo refresh request signal is set to the prescribed refresh cycle. By making the cycle shorter, the influence of the refresh cycle of the dynamic RAM on the processing capability of the microcontroller can be suppressed while satisfying the prescribed refresh cycle of the dynamic RAM.

In addition, dynamic RA of the evaluation chip
M is provided with a plurality of banks that are alternately designated as being in the RAS down state during standby, thereby reducing the probability of a row miss hit and substantially equalizing the access cycles of the product chip and the evaluation chip. A decrease in the processing capacity of the microcontroller can be suppressed.

[0017]

FIG. 1 shows a product chip of a microcontroller (logic integrated circuit device) to which the present invention is applied (hereinafter referred to as an evaluation chip provided for emulation of a microcontroller). FIG. 2 shows a block diagram of a first embodiment of the present invention, and FIG. 2 shows a partial connection diagram of the first embodiment. FIG. 3 is a block diagram of a first embodiment of an evaluation chip of a microcontroller to which the present invention is applied, and FIG. 4 is a partial connection diagram of the first embodiment. I have. Based on these figures, first, the outlines and features of the configuration and operation of the product chip and the evaluation chip of the microcontroller according to this embodiment will be described, and the differences between them will be described.

The circuit elements constituting each block of FIGS. 1 and 3 are known MOSFETs (metal oxide semiconductor type field effect transistors; in this specification, MOSFE
It is formed on a single chip surface such as single crystal silicon by an integrated circuit manufacturing technique (T is a generic name of insulated gate field effect transistors). 3 and 4
Among the blocks, signals, and the like shown in (1) and (2), those given the same name correspond to each other as they are and have the same functions. Therefore, in the description regarding FIGS. 3 and 4,
Description will be added only to the parts different from those in FIGS.

In FIG. 1, the product chip of the microcontroller of this embodiment comprises a so-called stored program type central processing unit CPU and a clock generation circuit C.
PG. The central processing unit CPU is coupled with a bus status controller BSC via an internal bus IBUS, and is coupled with a read only memory ROM, a static RAM (SRAM) and a direct memory access controller DMAC, and a clock generation circuit. A crystal oscillator XTAL having a predetermined natural vibration number is coupled to the CPG via external terminals XTAL and EXTAL. The microcontroller also has external terminals VCC and VS from an external power supply.
A power supply voltage VCC and a ground potential VSS, which are main operating power supplies, are supplied via S, respectively, and an external terminal HSTBYb (here, a so-called inverted signal which is selectively set to a low level when it is enabled, ,
The name is represented by adding "b" to the end. Hereinafter the same) and RE
The standby signal HSTBYb and the reset signal RESb are supplied via Sb.

The central processing unit CPU of the microcontroller performs a step operation in accordance with a control program stored in the read-only memory ROM, performs various arithmetic processes, and controls and supervises each part of the microcontroller. In addition, the clock generation circuit CPG forms a clock signal having a predetermined frequency and phase corresponding to its natural frequency together with the external crystal oscillator XTAL, and supplies the clock signal to each unit of the microcontroller. The read-only memory ROM is composed of a nonvolatile memory such as a mask ROM, a flash memory, or an EEPROM (electrically erasable / programmable read-only memory). Stores fixed data, etc.

On the other hand, a static RAM (SRAM)
Is a relatively small-capacity memory that enables relatively high-speed access, and is used to temporarily store the calculation results of the central processing unit CPU, control data, and the like. Also, a direct memory access controller DMAC
Supports high-speed data transfer between, for example, a static RAM (SRAM) and an external device without requiring the intervention of a central processing unit CPU. Further, the bus controller BUSC supervises and manages a bus access to the internal bus IBUS, and reads the read only memory RO.
M or a static RAM, and controls the internal bus IBUS and the peripheral bus PBU.
S, that is, a connection process with various devices coupled thereto is performed. The specific configuration of the read-only memory ROM of the bus status controller BSC will be described later in detail.

The microcontroller further includes an interrupt controller INTC, and its peripheral bus PBUS is not particularly limited, but further includes a serial communication interface SCI, a timer circuit TIM, an analog / digital conversion circuit A / D, and five input / output circuits. Ports IOP1 to IOP5 are connected. Among them, the serial communication interface SCI supports serial data transfer in accordance with a predetermined algorithm with an external serial input / output device coupled to a predetermined input / output port, and the timer circuit TIM includes a clock generation circuit. In accordance with the internal clock signal supplied from the CPG, time management necessary for waiting processing of the central processing unit CPU is performed. Also, an analog / digital conversion circuit A
The / D converts an analog input signal input from, for example, various external sensors or the like into a digital signal of a predetermined bit and transmits the digital signal to a central processing unit CPU or the like. Further, the input / output ports IOP1 to IOP5 function as interface circuits that mediate signal transmission and reception between each unit of the microcontroller and various external devices.

As shown in FIG. 2, the central processing unit CPU, the bus status controller BSC and the read-only memory ROM of the product chip of the microcontroller operate synchronously in accordance with the internal clock signal CPI supplied from the clock generation circuit CPG. I do.
Of these, the bus status controller BSC is connected to the central processing unit C via the command bus BCMD, the internal address bus IAB, and the bus ready signal line BRDYb.
PU and a module select signal MSR
OMb, read / write signal MRWb, and a 2-bit data size designation signal DSIZE are coupled to the read only memory ROM. Read only memory ROM
Is further connected to a central processing unit CPU via a predetermined bit internal address bus IAB and an internal data bus IDB.
Is combined with

In this embodiment, the central processing unit CPU of the product chip outputs various commands to the command bus BCMD, and specifies a functional block to receive the command by a predetermined bit of the internal address bus IAB. Also,
Other predetermined bits of the internal address bus IAB, for example, a read only memory ROM or a dynamic RAM (D
RAM) to specify the memory address to be accessed,
The write data for the designated block is output via the internal data bus IDB, or the read data from the designated function block is fetched. The central processing unit CPU identifies that the operation corresponding to the command has been completed without any problem by setting the bus ready signal BRDYb to the valid level, that is, the low level by the designated function block.

On the other hand, the read-only memory ROM is selectively provided by setting the module selection signal MSROMb to an effective level, that is, a low level such as the ground potential VSS (hereinafter, the low level refers to a level such as the ground potential VSS). The state is selected. At this time, the operation mode of the read-only memory ROM is selectively set to the read mode by setting the read / write signal MRWb to the high level, and set to the write mode by setting this to the low level. The read operation and the write operation of the read only memory ROM are selectively set to a 32-bit long word mode, a 16-bit unit word mode, or an 8-bit unit byte mode in accordance with a 2-bit data size designation signal DSIZE. . When the read-only memory ROM is a mask ROM, it goes without saying that there is no write operation for setting the read / write signal MRWb to low level.

Further, in this embodiment, the number of access cycles to the read-only memory ROM of the product chip of the microcontroller is configured to be substantially the same as the number of access cycles to the dynamic RAM of the evaluation chip described later. For this purpose, a memory controller ROMC including an address comparison circuit ADDC and a pseudo refresh controller RFCP are provided. As will be described later, the dynamic RAM incorporated in the evaluation chip as a substitute memory for the read-only memory ROM uses a RAS down method in which the previously accessed row address is selected as it is during standby, and a predetermined value is set. A refresh cycle is required in a cycle, and the bus status controller BSCE of the evaluation chip holds the previously accessed row address, and compares this with the portion corresponding to the row address of the address output when accessing the dynamic RAM. A memory controller DRAMC including an address comparison circuit ADDC and a refresh controller RFC for generating a refresh request signal RFRQ at a predetermined cycle and managing a refresh address RFAD
And

Therefore, the previously accessed row address is also held in the bus status controller BSC of the product chip, and a portion corresponding to the row address of the address output when accessing the read-only memory ROM is compared and collated. An address comparison circuit ADDC; a pseudo refresh controller RFCP for generating a pseudo refresh request signal RFQP at substantially the same cycle as the refresh request signal RFRQ generated by the refresh controller RFC of the evaluation chip; BSC
Is when the address comparison result by the address comparison circuit ADDC matches, or when the pseudo refresh request signal R
When the FQP is set to an effective level, that is, a high level like the power supply voltage VCC (hereinafter, the high level refers to a potential like the power supply voltage VCC), the read only memory ROM
Are selectively extended by a predetermined period so as to have substantially the same number of cycles as the access cycle of the evaluation chip to the dynamic RAM. This will be described later in detail.

Next, as shown in FIG. 3, the evaluation chip of the microcontroller is rewritten as a non-rewritable mask ROM of a product chip or a flash memory or an alternative memory of an EEPROM which requires a relatively long time for rewriting. A dynamic RAM (DR) capable of operating at a relatively high speed, and having a relatively small layout area and power consumption and being mountable on the same chip surface.
AM). This dynamic RAM (DRA
In M), at the beginning of the development of the microcontroller, a control program under development corresponding to the user of the microcontroller, fixed data, and the like are written, and emulation for performance confirmation is performed.

As shown in FIG.
The AM (DRAM) employs a so-called address multiplex system in which a row address and a column address are input in a time-division manner via a common address input terminal, that is, a memory address signal line MADD. Therefore, the dynamic RAM (DRAM) requires the row address strobe signal RASb and the column address strobe signal CASb as the activation control signals, and according to the row address cycle according to the row address strobe signal RASb and the column address strobe signal CASb. Column address cycle. Therefore, the access mode of the dynamic RAM (DRAM) is naturally different from that of the read-only memory ROM of the product chip which adopts the one access cycle system according to the module selection signal MSROMb.

In order to deal with this, in the dynamic RAM (DRAM) of the evaluation chip of this embodiment, the row address strobe signal RASb is kept at the low level even after the access is completed, so that the previously accessed row address In the so-called RAS down mode in which the standby state is kept in the selected state and the next access is waited for, the required cycle when the same row address is continuously accessed is one cycle. However, when a row address different from the previous access is specified, a row address cycle and a column address cycle are required again. Only in this case, the dynamic RAM (DRA) is used.
The number of access cycles of M) is three times the number of access cycles of the read-only memory ROM of the evaluation chip.

The memory controller DRAMC of the bus status controller BSCE of the evaluation chip holds the previously accessed row address, and is supplied from the central processing unit CPU when this row address and the next access to the dynamic RAM (DRAM) are performed. An address comparison circuit ADDC for comparing and collating a portion of an address corresponding to a row address is provided, and an access mode to a dynamic RAM (DRAM) is selectively switched based on a result of the comparison. Note that a dynamic RAM (DRAM) based on the row address comparison result
The switching of the access mode will be specifically described later.

On the other hand, a dynamic RAM (DRAM)
As is well known, a refresh cycle is required for reading and rewriting data held in all memory cells constituting a memory array at a predetermined cycle and in word line units. The execution of this refresh cycle and the dynamic R
Since the normal access of the AM (DRAM) is performed asynchronously, it may occur at the same time. In this case, in the first embodiment, the refresh cycle is given priority over the normal access, and the normal access waits. receive.

In the memory controller DRAMC of the bus status controller BSCE of the evaluation chip, a refresh request signal RFQ is periodically generated at a predetermined cycle specified in the specification of the dynamic RAM (DRAM), and a built-in counter circuit is provided. Address to be refreshed, ie, refresh address signal RFA
A refresh controller RFC for sequentially generating D is provided. The specific content of the refresh cycle of the dynamic RAM (DRAM) and the processing when the normal access occurs simultaneously will be described later in detail.

FIG. 5 is a timing chart of one embodiment of the microcontroller shown in FIGS. 1 to 4 when the product chip and the evaluation chip are row-missed. With reference to the figure, the operation when the product chip and the evaluation chip of the microcontroller of this embodiment have a row mishit, that is, when the previously accessed row address is different from the next accessed row address will be specifically described.

In the following timing diagrams including FIG. 5, common signals and the like of the product chip and the evaluation chip of the microcontroller, such as the command bus BCMD, the internal address bus IAB, the internal data bus IDB, the data size designation signal DSIZE, and Read / write signal MRW
b are collectively shown in the upper part of each figure, and signals and the like separately provided on the product chip and the evaluation chip, ie, the operation state of the memory controller ROMC, the module selection signal MSROMb, the operation state of the memory controller DRAMC, and the memory address are shown below. MADD, a row address strobe signal RASb, and a column address strobe signal CASb are shown, respectively.

On the other hand, in the following timing diagrams, the operation cycles of the product chip and the evaluation chip are shown as if they were executed in parallel. It is shown in comparison for comparison, and it goes without saying that the product chip and the evaluation chip operate independently. Further, in these timing diagrams, all signals change in synchronization with the internal clock signal CPI, but there are actually time differences due to delay time of related circuits and signal paths. FIG. 5 shows the cycle Cy. 11, the non-selected state of the read-only memory ROM is also described, and the cycle Cy. 12, the operation at the time of a row hit, that is, the operation when the previously accessed row address matches the next accessed row address is also described.

In FIG. 5, the product chip and the evaluation chip of the microcontroller of this embodiment operate synchronously in response to the rising edge of the internal clock signal CPI, and one cycle of the internal clock signal CPI is set as an operation unit, that is, a cycle. .

The first cycle Cy. At 11,
The read-only memory ROM of the product chip is deselected in response to the high level of the module selection signal MSROMb. Also, dynamic RAM of evaluation chip
(DRAM) has a column address strobe signal CAS
b does not perform a substantial write or read operation in response to the high level of the row address strobe signal RAS.
Since b is kept at the low level, the RAS is down, that is, the row address accessed last time, that is, the word line is selected and the standby state is set. At this time, commands for functional blocks other than the read-only memory ROM or the dynamic RAM (DRAM) are issued to the command bus BCMD, the internal address bus IAB, and the internal data bus IDB, or no command is issued.

Next, in the cycle Cy. At 12, the ROM read command, that is, the read command for the read only memory ROM of the product chip or the dynamic RAM (DRAM) of the evaluation chip is output to the command bus BCMD, and the read only memory ROM is designated to the internal address bus IAB. The device code and the memory address to be accessed in the read-only memory ROM are output. The data size designation signal DSIZE is, for example, a combination that selectively designates a long word mode L in 32-bit units, a word mode W in 16-bit units, or a byte mode B in 8-bit units in response to the contents held in the mode register. The read / write signal MRWb is R
It is set to the high level in response to the OM read command.

In a microcontroller product chip,
The address comparison circuit ADDC provided in the memory controller ROMC of the bus status controller BSC compares and compares the previously accessed row address and the portion corresponding to the row address of the memory address output at the time of this access bit by bit. . As a result, a row hit is determined, and upon receiving this row hit,
The module selection signal MSROMb for the read-only memory ROM is set to the low level effective level only for one cycle period. This allows read-only memory ROM
Reads the held data from the specified address, and in the next cycle Cy. At 13, the read result, that is, the read data is sent to the internal data bus IDB.

As described above, the product chip and the evaluation chip of the microcontroller employ a so-called pipeline bus system, and a command is issued for read data from a designated address of a read only memory ROM or a dynamic RAM (DRAM). It is output to internal data bus IDB in the next cycle of the cycle.

On the other hand, in the evaluation chip of the microcontroller, the address comparison circuit A provided in the memory controller DRAMC of the bus status controller BSCE is used.
The DDC compares and compares the previously accessed row address and the portion corresponding to the row address of the memory address output at the time of this access bit by bit. As a result, a row hit is determined. In response to the row hit, the column address strobe signal CASb for the dynamic RAM (DRAM) is set to low level for one cycle period, and the memory address M
The portion corresponding to the column address of the designated address is output as ADD. Thereby, the dynamic RAM
(DRAM) reads the held data from the column address specified by the row address in the selected state, and reads the data in the next cycle Cy. In step 13, the read result, that is, the read data is transmitted to the internal data bus IDB.

As described above, the dynamic RAM (DRAM) of the evaluation chip is set to the RAS down state, and the memory controller DR of the bus status controller BSCE is turned off.
By providing the AMC with an address comparison circuit ADDC for comparing and comparing the previously accessed row address with the next accessed row address, the access cycle of the dynamic RAM (DRAM) at the time of a row hit can be compared with the read only memory ROM of the product chip. The same one access cycle can be used.

Next, in the cycle Cy. In the cycle Cy. As with 12, the command bus BCMD has a ROM
A read command is output, but the internal address bus IA
B includes the last cycle, ie, cycle Cy. A memory address including a row address different from the row address accessed at 12 is output. Data size designation signal DSIZE
Is a combination designating the data size L, W or B, and the read / write signal MRWb is at a high level indicating the read mode.

In the microcontroller product chip,
Address comparison circuit ADD of memory controller ROMC
By C, the row address accessed last time is compared bit by bit with the portion corresponding to the row address of the memory address output at the time of this access. As a result, a row miss is determined, and in response to this, the module selection signal M for the read only memory ROM is received.
SROMb is set to low level only for three cycle periods corresponding to the access cycle of the evaluation chip. The fourth cycle, Cy. At 13, the read data at the specified address of the read only memory ROM is output to the internal data bus IDB.

On the other hand, in the evaluation chip of the microcontroller, a portion corresponding to the row address of the previously accessed row address and the row address of the memory address output in the current access is bit by bit by the address comparison circuit ADDC of the memory controller DRAMC. Compare and match. As a result, the row mishit is also determined, and in response to this, the row address strobe signal RASb for the dynamic RAM (DRAM) is returned to the high level for one cycle period.

The row address strobe signal RASb returned to the high level for one cycle period receives the next cycle Cy. 16 again to the valid level of the low level, and the cycle Cy. At 17, the column address strobe signal CASb is set to the low level for one cycle period. A new row address is supplied to the memory address MADD according to the low level of the row address strobe signal RASb, and a new column address is output according to the low level of the column address strobe signal CASb. Thereby, the dynamic RAM
(DRAM) reselects the word line corresponding to the new row address of the memory array, reads the data held from the designated column address of the selected word line, and reads the data in the next cycle Cy. 18 is the internal data bus ID
B.

As described above, the dynamic RAM (DRAM) of the evaluation chip, when a row mishit occurs,
The row address strobe signal RASb is returned to a high level, and a total of three access cycles including a row address cycle for selecting a word line corresponding to a new row address and a column address cycle corresponding to a new column address are required. . However, in the product chip of the microcontroller of this embodiment, as described above, the address comparison circuit A of the memory controller ROMC is used.
Unnecessary row address comparison and collation operation is performed by the DDC as a read-only memory ROM. When a row miss occurs, the module selection signal MSROMb is set to low level for three cycles, and the access cycle is extended three times. As a result, the read-only memory R of the product chip
Dynamic RAM for OM access and evaluation chip
The number of access cycles at the time of (DRAM) access is unified to three, and emulation for performance confirmation by an evaluation chip can be performed under the same conditions as a product chip.

FIG. 6 is a timing chart showing one embodiment of refreshing the product chip and the evaluation chip of the microcontroller shown in FIGS. Based on the figure, when refreshing a product chip and an evaluation chip, that is, a refresh cycle or a pseudo refresh cycle and a read only memory ROM or a dynamic RAM
The operation when the normal access to (DRAM) occurs simultaneously will be specifically described. In FIG. 6,
Cycle Cy. 21 is a read only memory ROM
, Or the RAS down state of the dynamic RAM (DRAM), respectively, and the cycle Cy.
25 to Cy. As 27, a normal access in the row mishit state executed following the refresh cycle is also described. In addition, FIG. 6 basically follows the embodiment of FIG. 5, and therefore, in the following description, only the different parts will be described.

In FIG. 6, cycle Cy. In 22,
A ROM read command is output to the command bus BCMD, and a memory address to be accessed is output to the internal address bus IAB. At the same time, the pseudo refresh controller RFCP provided in the bus status controller BSC of the product chip outputs the memory controller ROMC.
Refresh request signal RFQP to the memory controller DRAMC from the refresh controller RFC provided in the bus status controller BSCE of the evaluation chip.
(Here, for example, a change in the pseudo refresh controller RFCP or the refresh request signal RFQ from an invalid level to an effective level is referred to as asserted, and the opposite state is referred to as negated. The same applies hereinafter). .

As described above, the bus status controllers BSC and BSCE of the product chip and the evaluation chip are:
A pseudo refresh request signal RFQP or a refresh request signal RFQ output from the pseudo refresh controller RFCP or the refresh controller RFC,
Acceptance is given priority over normal access by the central processing unit CPU. The central processing unit CPU that has issued the command such as the ROM read command receives the command in response to the assertion of the bus ready signal BRDYb (not shown) by the bus status controller BSC or BSCE, and the corresponding read operation or the like is completed. Identify that.

In this embodiment, the cycle Cy. 22
The bus status controller BSC of the product chip, which has simultaneously received the ROM read command by the central processing unit CPU and the pseudo refresh request signal RFQP by the pseudo refresh controller RFCP, first receives the pseudo refresh request signal RFQP according to the above-mentioned priority order, Bus ready signal B for CPU
Without asserting RDYb, the effective start of the ROM read command is delayed by three cycle periods corresponding to the refresh cycle of the evaluation chip.

On the other hand, RO by the central processing unit CPU
The bus status controller BSCE of the evaluation chip which has simultaneously received the M read command and the refresh request signal RFQ based on the refresh request signal RFQ receives the refresh request signal RFQ with priority according to the above priority order, and the row for the dynamic RAM (DRAM). The address strobe signal RASb is once returned to a high level to start a refresh cycle, and a bus ready signal BRDY to the central processing unit CPU.
Without asserting b, the effective start of the ROM read command is delayed by three cycle periods corresponding to the refresh cycle.

Next, the bus status controller BSC of the product chip executes the cycle Cy. 3 cycles after the completion of the refresh cycle. At 25, the module selection signal MSROMb is set to low level, and the read only memory R
The OM read operation is started. However, at this time, the row address of the specified memory address has a probability close to 100% of the dynamic RAM (DRA) of the evaluation chip.
Since the row address M) is different from the previously accessed row address, that is, the refresh address, the row is in a row mishit state. The bus status controller BSC sends a module selection signal MSR to the read only memory ROM.
OMb is set to 3 necessary for switching the row address of the evaluation chip.
The read-only memory ROM sets the read data to cycle Cy. At 28, it is output to the internal data bus IDB. At this time, the bus ready signal BRDYb is asserted to a low level to report that the read operation to the central processing unit CPU has been completed.

On the other hand, the bus status controller BSCE of the evaluation chip also outputs the cycle Cy. At 25, the read operation of the dynamic RAM (DRAM) is started. Since the row is in the row mishit state as described above, the row address strobe signal RASb for the dynamic RAM (DRAM) is set to the high level for one cycle period. In the next cycle Cy. At 26, the row address strobe signal RASb is set to the low level again, the row address is output as the memory address MADD, and the row address is switched. Then, the cycle Cy. 27, the column address strobe signal CA
Sb is set to low level only for one cycle period,
The column address is output as the memory address MADD, and the next cycle Cy. After the read data is output to the internal data bus IDB at 28, the bus ready signal BRDYb
Is asserted to a low level.

As described above, the bus status controller BSC of the product chip is the dynamic type R of the evaluation chip.
A pseudo refresh request signal RFQP is periodically generated at a prescribed period of the AM (DRAM). A pseudo refresh request signal RFQP is periodically generated. And the start of the substantial read operation of the read-only memory ROM is delayed by three cycle periods corresponding to the refresh cycle of the evaluation chip. At the end of the refresh cycle of the evaluation chip, the waited normal access, that is, the ROM read command, etc. is started, and the access cycle to the read-only memory ROM is added to the row mishit generated at this time. The countermeasures are extended by three cycle periods required for row address switching.

As a result, the number of access cycles to the read-only memory ROM of the product chip can be matched with the number of access cycles to the dynamic RAM (DRAM) of the evaluation chip including the refresh cycle. The emulation for checking the performance by the chip is performed under the same conditions as the product chip, and the complete emulation can be realized.

FIG. 7 is a partial connection diagram of a second embodiment of the evaluation chip of the microcontroller to which the present invention is applied. Since the evaluation chip of this embodiment basically follows the embodiment of FIG. 4, in the following description relating to FIG. 7, only the portions different from the embodiment of FIG. 4 will be described.

In FIG. 7, a dynamic RA provided on the evaluation chip of the microcontroller of this embodiment is shown.
M (DRAM) has m + 1 banks BANK0 to BANK
NKm, and one interface circuit IF provided commonly to these banks. Dynamic RA
M (DRAM) is coupled to central processing unit CPU via internal data bus IDB. Further, in the dynamic RAM (DRAM), a memory address MADD, a column address strobe signal CASb, and a read / write signal MRWb are sent from the bus status controller BSCE.
In addition, a data size designation signal DSIZE is supplied, and row address strobe signals RAS0b to RASmb of m + 1 bits are supplied.

In this embodiment, the dynamic RA
M (DRAM) banks BANK0 to BANKm include:
Prior to emulating the microcontroller,
The same information including the control program and fixed data is written all at once. In addition, banks BANK0 to BANK
m denotes a row address strobe signal RAS0 when a dynamic RAM (DRAM) is normally accessed.
When the corresponding bits b to RASmb are set to the valid level, that is, the low level, they are selectively activated, and when the dynamic RAM (DRAM) is set to the refresh mode, they are simultaneously activated to perform the refresh operation.

On the other hand, the dynamic RAM of this embodiment
(DRAM) adopts the RAS down method and the bank BA
NK0 to BANKm are put into a standby state with the word lines corresponding to the previously accessed row address being selected, by keeping the bits corresponding to the row address strobe signals RAS0b to RASmb at the low level even after the access is completed. You. The address comparison circuit ADDC provided in the bus status controller BSCE of the evaluation chip holds the previously accessed row addresses for each of the banks BANK0 to BANKm, and stores these row addresses and the memory addresses supplied at the next access. Has a function of comparing and collating with a portion corresponding to the row address of each bank.

As described above, the access cycle of the read-only memory ROM and the dynamic RAM (DRAM) in the product chip and the evaluation chip is based on the row hit, that is, the row address accessed last time and the row address specified next. When they match, the cycle is the same as that of the read-only memory ROM of the product chip. However, when a row miss occurs, that is, when the previously accessed row address does not match the next specified row address, the evaluation is performed. Dynamic RAM (D
3 cycles necessary for switching the row address of the RAM). Therefore, the processing capability of a microcontroller as a product chip increases as the probability of a row hit increases, and decreases as the probability of a row hit decreases.

As described above, the dynamic RAM (D
(RAM) holding the same information in m + 1 banks RAS
0b to RASmb, and these banks are set to RA in accordance with row address strobe signals RAS0b to RASmb.
By setting the S-down state, the dynamic RAM (D
RAM) row hit probability Prh
+1 and the total number of word lines provided in each bank is Nw
Then, Prh = (m + 1) / Nw. Needless to say, in the case of the embodiment in FIG. 4, the number of banks m + 1 is 1, and the probability Prh of the row hit is Prh = 1 / Nw. When the number of banks m + 1 is equal to the number of word lines Nw, that is, when banks BANK0 to BANKm are provided for each word line, Prh = Nw / Nw = 1, that is, 100%, and row miss hits occur. No longer.

In any case, m + 1 banks BANK0 are stored in the dynamic RAM (DRAM) of the evaluation chip.
ＢBANKm, the probability Prh of the row hit of the evaluation chip becomes m + 1 times that of the embodiment of FIG.
This results in a corresponding increase in the throughput of the product chips. Immediately after the power is turned on and immediately after the end of the refresh cycle, the probability Rhh of the row hit is temporarily reduced and the processing performance is reduced.
It doesn't matter much.

FIG. 8 is a timing chart of a third embodiment of a product chip and an evaluation chip of a microcontroller to which the present invention is applied. Since this embodiment basically follows the embodiment shown in FIGS. 5 and 6, only the portions different from these embodiments will be described in the following description.

In FIG. 8, the memory controller R provided in the bus status controller BSC of the product chip and the evaluation chip of the microcontroller of this embodiment.
OMC and DRAMC are provided for normal access by the central processing unit CPU and a pseudo refresh controller RFC.
P or the pseudo refresh request signal RFQP or the refresh request signal R by the refresh controller RFC
When the FQ and the FQ occur simultaneously, the normal access is preferentially accepted and the refresh cycle is performed in the read only memory R.
It waits until a cycle in which another command for a functional block other than the OM or the dynamic RAM (DRAM) is issued.

That is, RO on the command bus BCMD
M read command and the pseudo-refresh request signal RFQP or refresh request signal RFQ by the product chip or the evaluation chip simultaneously occur in the cycle Cy. At 32, first, the ROM read command on the command bus BCMD is preferentially accepted by the memory controller ROMC or DRAMC of the bus status controller BSC or BSCE. This ROM read command is brought into a row hit state and the cycle Cy. 32 and the next cycle Cy. At 33, read data of a read only memory ROM or a dynamic RAM (DRAM) is output to the internal data bus IDB.

On the other hand, the waited pseudo refresh request signal RFQP or refresh request signal RFQ
Is the cycle Cy. Since the command output on the command bus BCMD to the command bus BCMD is another command for a functional block other than the read-only memory ROM or the dynamic RAM (DRAM), this cycle Cy. 33 to cycle Cy. Between 35, a corresponding refresh cycle is started. Note that the cycle Cy. 33, the data cycle of the other command is cycle C
y. 34 to Cy. 38 over 5 cycles.

Next, the central processing unit CPU executes the next cycle Cy. 34, a ROM read command is output to the command bus BCMD again. This ROM read command is provided with a cycle Cy. After the completion of the refresh cycle and the completion cycle of the data cycle of another command. It starts from 36. Needless to say, the cycle Cy. The ROM read command started at 36 is in a row mishit state, and row addresses are switched in the dynamic RAM (DRAM) of the evaluation chip. In addition, the memory controller ROMC of the product chip has three cycles corresponding to a refresh cycle.
During the cycle period, the output of the bus ready signal BRDYb to the central processing unit CPU is refrained, and the next RO
Module select signal MSR corresponding to M read command
OMb is set to the low level for only three cycle periods required for switching the row address of the dynamic RAM (DRAM).

Therefore, in this embodiment, the access cycle of the product chip to the read-only memory ROM is the same as that of the evaluation chip to the dynamic RAM (DRAM), as in the embodiments of FIGS. The number of cycles becomes the same, complete emulation can be realized, and the normal access is performed by the pseudo refresh request signal RFQP or the refresh request signal RFQ.
, It is possible to reduce the overhead due to the insertion of a pseudo refresh cycle and to suppress a reduction in the processing capability of a product chip.

In this embodiment, the bus status controllers BSC and BSCE of the product chip and the evaluation chip have a function of monitoring the period during which the refresh cycle is waiting, and the waiting time of the refresh cycle exceeds the specified value. In this case, the pseudo refresh request signal RFQP or the refresh request signal R
FQ is accepted prior to normal access. Further, the cycle of the pseudo refresh request signal RFQP and the refresh request signal RFQ generated by the pseudo refresh controller RFCP or the refresh controller RFC is several cycles to several tens of cycles from the cycle specified in the specification of the dynamic RAM (DRAM). Set short. As a result, it is possible to prevent the refresh cycle from exceeding the specified value due to the waiting of the refresh cycle and the loss of the data held in the dynamic RAM (DRAM).

The functions and effects obtained from the above embodiment are as follows. (1) The access cycle of a read-only memory built in a product chip of a logic integrated circuit device such as a microcontroller is substantially the same as the access cycle of a dynamic RAM built in the evaluation chip as a substitute memory for the read-only memory. By configuring so that the number of cycles is the same, the number of access cycles to the read-only memory of the product chip matches the access cycle to the dynamic RAM of the evaluation chip, and complete emulation in a specified machine cycle of a microcontroller or the like is realized. The effect that it can be obtained is obtained.

(2) In the above item (1), the so-called R in which the dynamic RAM of the evaluation chip is set in the standby state while the row address accessed last time is kept in the selected state.
AS down state, evaluation type dynamic R
A bus status controller including an address comparison circuit for identifying that a portion corresponding to a row address of an address output at the time of access to an AM matches a previous row address is provided, and a bus status controller of a product chip is similarly provided. A dynamic address comparison circuit which has a function of selectively extending the access cycle to the read-only memory for a predetermined period when the row address mis-hits is provided. RAM can be accessed in one cycle,
The effect is obtained that the number of access cycles to the read-only memory of the product chip can be matched with the number of access cycles to the dynamic RAM of the evaluation chip.

(3) In the above items (1) and (2), the bus status controller of the evaluation chip is provided with a refresh controller for executing a refresh cycle of the dynamic RAM at a predetermined cycle. The status controller is also provided with a pseudo-refresh controller that generates a pseudo-refresh request signal at the above-mentioned predetermined period, and the bus status controllers of the product chip and the evaluation chip receive the refresh request signal or the pseudo-refresh request signal from the read-only memory or the dynamic When the pseudo refresh request signal is set to a valid level, the access cycle to the read-only memory is dictated by the bus status controller of the product chip. By providing a function to selectively extend only the period required for refreshing the Mick RAM, the number of access cycles to the read-only memory of the product chip matches the access cycle of the Dynamic RAM that requires the refresh cycle of the evaluation chip The effect is obtained.

(4) In the above items (1) and (2), the read-only memory or the dynamic RA is provided in the bus status controllers of the product chip and the evaluation chip.
In addition to allowing the normal access to the M to be accepted prior to the refresh request signal or the pseudo refresh request signal, the bus status controller of the evaluation chip transmits the waited refresh cycle to another bus command to a functional block other than the dynamic RAM. To suppress the influence of the refresh cycle of the dynamic RAM of the evaluation chip on the processing capability of the product chip of the microcontroller by providing a function to execute the command selectively while the bus is not executed or the bus command is not executed. Is obtained. (5) In the above item (4), the refresh cycle is specified by making the refresh cycle of the refresh request signal or the pseudo refresh request signal shorter than the specified refresh cycle of the dynamic RAM. The effect of exceeding the value and preventing loss of data held in the dynamic RAM can be obtained.

(6) In the above items (1) to (5), the dynamic RAM of the evaluation chip is placed in a standby state while different row addresses are selected, and the corresponding row address strobe signal is set to an effective level. By providing a plurality of banks which are alternatively specified by the above, the probability of occurrence of row misses is reduced, and the processing cycle of the microcontroller is achieved by substantially equalizing the access cycle of the product chip and the evaluation chip. The effect that reduction can be suppressed is obtained.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the above embodiment, and various modifications can be made without departing from the gist of the invention. Needless to say, there is. For example, in FIGS. 1 and 3, the product chip and the evaluation chip of the microcontroller do not necessarily need to include all the illustrated functional blocks, but may include other various functional blocks. The block configuration, the bus configuration, and the like of the microcontroller can take various embodiments without being limited by this embodiment.

In FIGS. 2, 4 and 7, the block configuration of the bus status controllers BSC and BSCE is not restricted by each embodiment, and the central processing unit CPU and the bus status controller BSC or BSCE and the read only memory ROM or The same applies to the connection form with the dynamic RAM. The name and effective level of each signal, the number of bits, and the like can take various embodiments.

In FIGS. 5, 6 and 8, the absolute level and time relationship of each signal does not affect the gist of the present invention. Further, the relationship between each cycle of the internal clock signal CPI and the command or refresh cycle is not restricted by these embodiments, and the same applies to the effective level of each signal.

Further, in the above embodiment, the ROM read command, that is, the read only memory RO of the product chip is used.
Dynamic RAM (DRAM) of M or evaluation chip
Has been described only for the read operation of the read-only memory ROM or the dynamic type RA.
It can also be applied to the write operation of M (DRAM). However, read only memory ROM and dynamic RA
The frequency of writing to M is extremely low, and is unlikely to be the target of emulation.

In the above description, the case where the invention made by the present inventor is mainly applied to the microcontroller which is the field of application as the background has been described.
The present invention is not limited to this, and can be applied to, for example, a single-chip microcomputer and an ASIC (application-specific integrated circuit). The present invention relates to a dynamic RAM which incorporates at least a read-only memory in a product chip thereof, and
The present invention can be widely applied to a logic integrated circuit device having an evaluation chip incorporating the same and a device or system including the same.

[0082]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, the number of access cycles of the read-only memory built in the product chip such as the microcontroller is substantially the same as the number of access cycles of the dynamic RAM built in the evaluation chip as a substitute memory for the read-only memory. By evaluating the number of access cycles to the read-only memory of the product chip, the dynamic RAM of the evaluation chip
And complete emulation in a prescribed machine cycle of a microcontroller or the like.

In the above-mentioned microcontroller or the like, the dynamic RAM provided on the evaluation chip is set to the RAS down state in which the row address accessed last time is kept in the selected state and the standby state is maintained. A bus status controller including an address comparison circuit for identifying that a portion corresponding to a row address of the output address matches the previous row address is provided, and a similar address comparison circuit is provided for a bus status controller of a product chip. And a function to selectively extend the access cycle to the read-only memory for a predetermined period when the row address mishits, so that a row address cycle and a column address cycle are required as a start cycle. A dynamic RAM can be accessed in one cycle, and the number of access cycles to the read-only memory of a product chip such as a microcontroller matches the access cycle to the dynamic RAM of the evaluation chip as described above. it can.

In the microcontroller and the like, the bus status controller of the evaluation chip is provided with a refresh controller for executing a refresh cycle of the dynamic RAM at a predetermined cycle, and the bus status controller of the product chip is also provided with the predetermined cycle. A pseudo-refresh controller for generating a pseudo-refresh request signal, and causing the bus status controllers of the product chip and the evaluation chip to receive the refresh request signal or the pseudo-refresh request signal in preference to the normal access. Has a function of selectively extending the access cycle to the read-only memory for a period required for the refresh cycle when the pseudo refresh request signal is set to the valid level. By causing, can the number of access cycles for the read only memory of the product chip microcontroller or the like to match the access cycle refresh cycle for the dynamic RAM required.

In the above-mentioned microcontroller and the like, the bus status controller of the product chip and the evaluation chip receives access to the read-only memory or the dynamic RAM in preference to the refresh request signal or the pseudo refresh request signal. The bus status controller sends the waited refresh cycle to the dynamic RAM.
By providing a function to execute the bus command while the other bus command is executed or the bus command is not executed, the influence of the refresh cycle of the dynamic RAM on the processing capability of the product chip of the microcontroller can be suppressed.

At this time, the generation cycle of the refresh request signal or the pseudo refresh request signal is changed to the dynamic RA
By making the refresh cycle shorter than the specified refresh cycle of M, it is possible to prevent the refresh cycle from exceeding the specified value due to the waiting of the refresh cycle and losing the data held in the dynamic RAM.

In the above-mentioned microcontroller or the like, the dynamic RAM constituting the evaluation chip is placed in a standby state with different row addresses being selected, and the corresponding row address strobe signal is set to an effective level. By providing a plurality of banks specified in a row, the probability of a row miss hit is reduced, and a decrease in the processing capability of the microcontroller due to substantially equalizing the access cycles of the product chip and the evaluation chip can be suppressed. .

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a product chip of a microcontroller to which the present invention is applied.

FIG. 2 is a partial connection diagram showing one embodiment of a product chip of the microcontroller of FIG. 1;

FIG. 3 is a block diagram showing a first embodiment of an evaluation chip of a microcontroller to which the present invention is applied.

FIG. 4 is a partial connection diagram showing one embodiment of an evaluation chip of the microcontroller of FIG. 3;

FIG. 5 is a timing chart showing an embodiment of the microcontroller shown in FIGS. 1 to 4 at the time of a row miss hit of a product chip and an evaluation chip.

FIG. 6 is a timing chart showing an embodiment at the time of refreshing a product chip and an evaluation chip of the microcontroller of FIGS. 1 to 4;

FIG. 7 is a partial connection diagram showing a second embodiment of the evaluation chip of the microcontroller to which the present invention is applied.

FIG. 8 is a timing chart showing a third embodiment at the time of refreshing a product chip and an evaluation chip of a microcontroller to which the present invention is applied.

[Explanation of symbols]

CPU: Central processing unit, CPG: Clock generation circuit, IBUS: Internal bus, PBUS: Peripheral bus,
BSC: Bus status controller, ROM: Read only memory, SRAM: Static RAM
(Random access memory), DMAC ... direct memory access controller, INTC ... interrupt controller, SCI ... serial communication interface, TIM ... timer circuit, A / D ... analog / digital conversion circuit, IOP1 to IOP5 ... input Output port, XTAL ...... Crystal oscillator, XTAL, EX
TAL: Crystal oscillator connection terminal, HSTBYb: Standby signal or its input terminal, RESb: Reset signal or its input terminal, VCC: Power supply voltage or its input terminal, VSS ... Ground potential or its input terminal. CPI internal clock signal, BCMD bus command or command bus, BRDYb bus ready signal
IAB: Internal address bus, IDB: Internal data bus, ROMC: Memory (ROM) controller, AD
DC: Address comparison circuit, RFCP: Pseudo refresh controller, RFQP: Pseudo refresh request signal, MSROMb: Module selection signal, MRWb
...... Read / write signal, DSIZE ...... Data size designation signal. BSCE: Bus status controller, DRAM ...
... Dynamic RAM. DRAMC: Memory (DRAM) controller, RF
CE ... refresh controller, RFQ ... refresh request signal, RFAD ... refresh address signal, MADD ... address signal, RASb ... row address strobe signal, CASb ... column address strobe signal. IF: Interface circuit, BANK0-BANKm
... Bank, RAS0b to RASmb... Row address strobe signal.

Claims (9)

[Claims] 1. An evaluation chip comprising: a central processing unit; and a read-only memory accessed by a functional block including the central processing unit, wherein an evaluation chip in which the read-only memory or a part thereof is replaced with a dynamic RAM is prepared. And the access cycle to the read-only memory is:
A logic integrated circuit device, which is configured to be equivalent to an access cycle of the evaluation chip to the dynamic RAM. 2. The dynamic RAM according to claim 1, wherein the dynamic RAM is provided on the evaluation chip.
Is set to a standby state while keeping the previously accessed row address in the selected state. The product chip and the evaluation chip of the logic integrated circuit device hold the previously accessed row address, and A bus status controller including an address comparison circuit for identifying that a portion corresponding to the row address in the address output at the time of the next access matches the bus address controller; A logic integrated circuit device having a function of selectively extending an access cycle to the read-only memory for a predetermined period when a comparison result of a row address by a circuit does not match. 3. The refresh controller according to claim 1, wherein the evaluation chip generates a refresh request signal for executing a refresh cycle for the dynamic RAM at a predetermined cycle and manages a refresh address. The product chip includes a pseudo refresh controller that generates a pseudo refresh request signal substantially at the predetermined period, and the bus status controller of the product chip includes the pseudo refresh request signal in response to the pseudo refresh request signal. A logic integrated circuit device having a function of extending an access cycle to the read-only memory generated simultaneously with or during a corresponding pseudo refresh cycle by a predetermined period. 4. The bus status controller according to claim 3, wherein the bus status controller of the product chip and the evaluation chip gives priority to the refresh request signal or the pseudo refresh request signal over normal access to the read-only memory or the dynamic RAM. A logic integrated circuit device, which is to be accepted. 5. The bus status controller according to claim 3, wherein the bus status controller of the product chip and the evaluation chip gives priority to the normal access to the read-only memory or the dynamic RAM over the refresh request signal or the pseudo refresh request signal. A logic integrated circuit device, which is to be accepted. 6. The dynamic RAM according to claim 5, wherein the refresh operation of the dynamic RAM corresponding to the refresh request signal or the pseudo refresh request signal in a waiting state is performed by the dynamic RA.
A logic integrated circuit device, which is executed while another bus command other than M is executed or while a bus command is not executed. 7. The method according to claim 5, wherein a generation cycle of the refresh request signal or the pseudo refresh request signal is shorter than a refresh cycle specified as a specification of the dynamic RAM. Logic integrated circuit device. 8. The dynamic RAM according to claim 1, wherein the dynamic RAM keeps different row addresses selected. Logic integration comprising a plurality of banks in a standby state, wherein each of the banks is alternatively designated in response to a valid level of a corresponding activation control signal. Circuit device. 9. The logic integrated circuit device according to claim 1, wherein the logic integrated circuit device is a microcontroller. A logic integrated circuit device, wherein at least the control program or fixed data of the central processing unit is stored in the read-only memory or the dynamic RAM.