JP2000121700A5 - - Google Patents
Download PDFInfo
- Publication number
- JP2000121700A5 JP2000121700A5 JP1999290335A JP29033599A JP2000121700A5 JP 2000121700 A5 JP2000121700 A5 JP 2000121700A5 JP 1999290335 A JP1999290335 A JP 1999290335A JP 29033599 A JP29033599 A JP 29033599A JP 2000121700 A5 JP2000121700 A5 JP 2000121700A5
- Authority
- JP
- Japan
- Prior art keywords
- branch
- rank order
- branch voltage
- subset
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 description 11
- 230000000638 stimulation Effects 0.000 description 9
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US169597 | 1998-10-09 | ||
| US09/169,597 US6266787B1 (en) | 1998-10-09 | 1998-10-09 | Method and apparatus for selecting stimulus locations during limited access circuit test |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2000121700A JP2000121700A (ja) | 2000-04-28 |
| JP2000121700A5 true JP2000121700A5 (https=) | 2006-11-24 |
Family
ID=22616365
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11290335A Pending JP2000121700A (ja) | 1998-10-09 | 1999-10-12 | アクセスを制限した回路テストにおいて刺激位置を選択するための方法及び装置 |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US6266787B1 (https=) |
| EP (1) | EP0992804B1 (https=) |
| JP (1) | JP2000121700A (https=) |
| DE (1) | DE69923045T2 (https=) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6968285B1 (en) * | 2003-04-09 | 2005-11-22 | Hamid Adnan A | Method and apparatus for scenario search based random generation of functional test suites |
| US7111198B2 (en) * | 2003-06-12 | 2006-09-19 | Inventec Corporation | Multithread auto test method |
| US7779374B1 (en) | 2006-09-29 | 2010-08-17 | Breker Verification Systems, Inc. | Generating self-checking test cases from reduced case analysis graphs |
| WO2014121138A2 (en) * | 2013-01-31 | 2014-08-07 | The Regents Of The University Of California | Method and apparatus for solving an optimization problem using an analog circuit |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4012625A (en) * | 1975-09-05 | 1977-03-15 | Honeywell Information Systems, Inc. | Non-logic printed wiring board test system |
| US4204633A (en) * | 1978-11-20 | 1980-05-27 | International Business Machines Corporation | Logic chip test system with path oriented decision making test pattern generator |
| US5012180A (en) * | 1988-05-17 | 1991-04-30 | Zilog, Inc. | System for testing internal nodes |
| JPH07113898B2 (ja) * | 1989-05-09 | 1995-12-06 | 株式会社日立製作所 | 障害検出方式 |
| US5323108A (en) * | 1992-01-23 | 1994-06-21 | Hewlett-Packard Company | Method for generating functional tests for printed circuit boards based on pattern matching of models |
| US5808919A (en) | 1993-11-23 | 1998-09-15 | Hewlett-Packard Company | Diagnostic system |
| US5530372A (en) * | 1994-04-15 | 1996-06-25 | Schlumberger Technologies, Inc. | Method of probing a net of an IC at an optimal probe-point |
| US5521513A (en) * | 1994-10-25 | 1996-05-28 | Teradyne Inc | Manufacturing defect analyzer |
| US5732209A (en) * | 1995-11-29 | 1998-03-24 | Exponential Technology, Inc. | Self-testing multi-processor die with internal compare points |
| EP0794495A3 (en) * | 1996-03-08 | 1998-07-22 | Hewlett-Packard Company | Automated analysis of a model-based diagnostic system |
| US5734661A (en) * | 1996-09-20 | 1998-03-31 | Micron Technology, Inc. | Method and apparatus for providing external access to internal integrated circuit test circuits |
-
1998
- 1998-10-09 US US09/169,597 patent/US6266787B1/en not_active Expired - Fee Related
-
1999
- 1999-09-16 EP EP99118403A patent/EP0992804B1/en not_active Expired - Lifetime
- 1999-09-16 DE DE69923045T patent/DE69923045T2/de not_active Expired - Fee Related
- 1999-10-12 JP JP11290335A patent/JP2000121700A/ja active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Jenkins et al. | An application of functional dependencies to the topological analysis of protection schemes | |
| Flanders | Infinite networks: I--Resistive networks | |
| CA2171802A1 (en) | Comparative performance modeling for distributed object oriented applications | |
| RU95121102A (ru) | Способ инициализации и актуализации модели сети | |
| SE9702763D0 (sv) | Metod vid databas | |
| WO2007076357A3 (en) | System and method for finite element based topology optimization | |
| WO2000072256A3 (de) | Neuronales netz zum computergestützten wissensmanagement | |
| JPH11330967A5 (https=) | ||
| JP2000121700A5 (https=) | ||
| DE60323532D1 (de) | Schnelle wiederherstellung von einem unbrauchbaren heimat-server | |
| CN106709134B (zh) | 一种煤矿高压电网短路电流并行计算方法 | |
| CN108959300A (zh) | 文件存储方法和存储装置 | |
| Segal | Two-sided ideals in operator algebras | |
| JP2000121698A5 (https=) | ||
| CN109412138A (zh) | 均流控制系统和方法 | |
| DE60131889D1 (de) | Verfahren und telekommunikationsknoten zur verteilung von abschlussverkehr in einem telekommunikationsknoten | |
| JPH10327211A5 (https=) | ||
| Tippe et al. | Modular simulation of zonal architectures and ring topologies for automotive power nets | |
| Watanabe | A method of tree expansion in network topology | |
| JP2003067440A5 (https=) | ||
| JP2002313307A5 (https=) | ||
| JP2021170511A5 (https=) | ||
| JPS5812424A (ja) | 逐次比較型a/d変換器 | |
| CN111626463B (zh) | 一种基于Hadoop架构的电力系统短路电流并行协调方法 | |
| CN106528573B (zh) | HBase数据库的数据查询方法和装置 |