JP2000115186A - Parameter setting circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a parameter setting circuit capable of preventing the racing generation of the input data and input clock of an F/F for outputting an operation parameter to the circuit of a main signal processing system and eliminating the possibility of setting an erroneous parameter to the F/F for outputting the operation parameter to the circuit of the main signal processing system. SOLUTION: The F/F 3 tentatively holds the information of the operation parameter set from an asynchronously operated device control system CPU completely different from a main signal processing system clock 101 as being asynchronous as it is. A differentiation circuit 5 monitors the clock input signals of the F/F 3, the rising edge of the clock input signals is detected, the output of a 2-1 selector 6 connected to the output of the F/F 3 is switched by the detection signals of the rising edge, the information of the set operation parameter is outputted to the F/F 4 and the information is held in the F/F 4.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parameter setting circuit, and more particularly to a B-ISDN [BroadbandAsp].
ects of ISDN (Integrated S
services Digital Network (ATM): ATM (Asynch) for Realizing Broadband ISDN]
TECHNICAL FIELD The present invention relates to a parameter setting circuit of an ATM transmission device used in a network (asynchronous transfer mode).

[0002]

2. Description of the Related Art Conventionally, this type of ATM transmission apparatus has
In an ATM network for realizing ISDN, this is a device used for connecting a plurality of ATM transmission lines, performing multiplexing processing and line separation processing of ATM cells, and realizing a virtual path.

[0003] When an ATM transmission device transmits a signal such as data or voice, which is a non-ATM signal, using an ATM network, the ATM transmission device converts the non-ATM signal into an ATM cell and transmits the data to an ATM cell.
ATM sent to TM transmission line and received from ATM transmission line
CLAD (Cell) for reproducing non-ATM signals from cells
Assembly and Dis-assembl
This is a device for realizing a function called y).

In a digital transmission device such as the above-described ATM transmission device, a parameter setting circuit for setting operation parameters from a device control system CPU (central processing unit) to a circuit of a main signal processing system is shown in FIG. It has such a configuration. That is, the parameter setting circuit includes a decoder 1, an OR (OR) gate 2, and flip-flops (hereinafter, referred to as F / F) 3, 4.

Generally, there are a plurality of types of operation parameters.
The conventional method is prepared as an / O (input / output) register. In FIG. 5, F / F3 corresponds to an I / O register.

The decoder 1 decodes a control system address bus and generates an access signal to a target I / O register. The OR gate 2 outputs the output signal of the decoder 1 and the control system CP.
OR with a write signal from U (not shown). F /
F3 fetches and holds target parameters from the control system data bus 102. The F / F 4 synchronizes the output 301 of the F / F 3 with the main signal processing system clock 101. Where F
/ F3 and F / F4 are D flip-flops that hold data at the rising edge of the clock (CLK) signal.

Generally, the operation clock of the control system CPU operates completely asynchronously with the main signal processing system clock 101. The parameter setting circuit temporarily holds the operation parameter from the control CPU in the F / F3 while keeping it asynchronous, and thereafter outputs and holds the operation parameter from the F / F3 to the F / F4 operated by the main signal processing system clock 101. As described above, the parameter information synchronized with the main signal processing system clock 101 is F
/ F4 to the main signal processing circuit (not shown).

Here, when there are a plurality of types of operation parameters and there are a plurality of F / Fs 3 which fetch and hold the operation parameters, the decoder 1 determines which F / F 3 is the operation parameter to be held. This is a circuit provided to generate a signal. The control CPU manages the setting locations of the plurality of operation parameters by dividing the addresses.

The operation of the setting circuit shown in FIG. 5 is shown in a time chart of FIG. Here, a control system address bus is omitted to show an operation example of F / F3 of a certain address. In FIG. 6, the F / F 3 latches and holds data on the control system data bus 102 at the rising edge of the output signal of the OR gate 2. The value “7” is held at the first rising edge, and the value “4” is held at the second rising edge.

Next, the F / F 4 is the main signal processing system clock 1
Although the value “7” is held at the rising edge of the clock pulse CK7 of “01”, racing occurs at the rising edge of the clock pulse CK16 because it competes with the change point of the output 301 of the F / F3, and “4” The value "5" is held where the value should be held, and the normal value "4" is held at the next rising edge of the clock pulse CK17. There is a problem that the value of "5" during one clock may cause a malfunction in the circuit of the main signal processing system.

In this example, the parameter information is 3-bit information having a value from 0 to 7, and the clock pulse CK1
In the example of the rising edge of 6, the least significant bit should retain "0" for the occurrence of racing, but retain the previous value "1".

As described above, in the parameter setting circuit as shown in FIG. 5, when the operation clocks of the F / F3 and the F / F4 are completely asynchronous, it is inevitable that racing will occur and an erroneous operation will occur. It is inevitable that the parameter information is output to the circuit of the main signal processing system.

[0013]

In the above-mentioned conventional digital transmission apparatus, the operation parameters are set by the apparatus control system CPU for the main signal processing system circuit using the setting circuit as shown in FIG. Therefore, the rising edge of the clock between the F / F that receives the operation parameter from the device control system CPU and the F / F that outputs the operation parameter to the circuit of the main signal processing system is detected. This may cause erroneous parameter information to be set in the F / F that outputs operation parameters to the main signal processing circuit.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and to prevent occurrence of racing between input data of an F / F for outputting an operation parameter and an input clock to a circuit of a main signal processing system. It is another object of the present invention to provide a parameter setting circuit that can eliminate the possibility that an erroneous parameter is set in an F / F that outputs an operation parameter to a circuit of a main signal processing system.

[0015]

A parameter setting circuit according to the present invention sets operation parameters for a main signal processing circuit from a central processing unit of an apparatus control system asynchronously with the operation of the main signal processing circuit. A first holding unit for receiving and holding an operation parameter from a central processing unit of the device control system;
A second holding means for receiving the content held by the holding means and outputting the content to the main signal system circuit; and a second holding means provided between the first holding means and the second holding means, and Selecting means for selecting one of the output of the holding means and the output of the second holding means and outputting the selected output to the second holding means; and the first control parameter of the operation parameter from the central processing unit of the apparatus control system. And detecting means for detecting a setting to the holding means and outputting a switching signal to the selecting means when the setting is detected.

In the ATM transmission apparatus, the operation clock of the main signal processing circuit and the operation clock of the control CPU circuit are generally clock signals that operate in completely different asynchronous operations. In this case, the setting of the operation parameters from the device control system CPU to the main signal processing system is set completely asynchronously with the operation of the main signal system circuit.

According to the present invention, in the circuit for transferring the operation parameter information set asynchronously to the operation clock of the main signal system, the main signal is set even when the timing of the parameter setting conflicts with the operation clock of the main signal processing system. A parameter setting circuit that does not adversely affect the operation of the processing system and does not cause a malfunction is realized.

The present invention relates to an operation parameter setting circuit from a device control system CPU to a circuit of a main signal processing system in a digital transmission device as in the conventional example. According to the present invention, a device control system C
A 2-1 selector is added between a first F / F that receives an operation parameter from the PU and a second F / F that outputs an operation parameter to a circuit of the main signal processing system. A / F clock input signal is connected to a differentiating circuit, and its output signal is connected to a 2-1 selector select signal.

In the present invention, information on operation parameters set by the device control system CPU which operates completely asynchronously with the operation clock of the circuit of the main signal processing system is once held as asynchronous with the first F / F. This is the same as in the conventional example.

The clock input signal of the first F / F is monitored by a differentiating circuit to detect a rising edge of the clock input signal of the first F / F. In response to the rising edge detection signal, the output of the 2-1 selector connected to the output of the first F / F is switched, and information on the set operation parameters is output to the second F / F. The second F / F holds it.

Accordingly, the setting of the parameter information for the circuit of the main signal processing system is performed only when the second F / F detects the setting of the first F / F from the device control system CPU. The information will be captured, and the first
No lacing occurs between the change point of the output data of the F / F and the clock of the main signal processing system, and parameter information having an incorrect value is transmitted to the main signal processing system circuit as described in the conventional example. It is no longer output.

[0022]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a diagram showing a configuration of a parameter setting circuit according to one embodiment of the present invention. In the figure, a parameter setting circuit according to one embodiment of the present invention includes a decoder 1, an OR (OR) gate 2, flip-flops (hereinafter referred to as F / F) 3, 4, a differentiating circuit 5,
And one selector 6. Here, F / F3
Corresponds to an I / O register (not shown) of the control system CPU (not shown).

The decoder 1 decodes a control system address bus and generates an access signal 104 for accessing a target I / O register. OR gate 2 is the output signal 104 of decoder 1
And a write signal from the control system CPU to generate a write signal 201 to the target I / O register.

The F / F 3 takes in target parameter information from the control system data bus signal 102 and holds it. F / F4
Synchronizes the parameter information with the main signal processing system clock 101. The differentiating circuit 5 detects a rising edge of the output signal 201 of the OR gate 2.

The 2-1 selector 6 outputs the output of the F / F3 and the F / F
The output signal 5 of the differentiating circuit 5 is arranged between the input of F4
01 supplies an output signal 301 of the F / F3 to the F / F4.

2-1 F / F4 is input to the A side input of the selector 6
, Ie, parameter information 103 output to the main signal processing system, and an output signal 301 of the F / F 3 is connected to the B-side input. The output signal 501 of the differentiating circuit 5 is connected to the select control signal of the 2-1 selector 6, and the output of the 2-1 selector 6 is controlled by the output signal 501.

The differentiating circuit 5 has a main signal processing system clock 101.
Two series-connected F / Fs 5A and 5B operating on
It comprises an AND gate 5C for ANDing the Q output 502 of the F / F 5A and the Q bar output (inverted output) 503 of the F / F 5B. In the differentiating circuit 5, the rising edge of the signal input to the F / F 5A is detected by these circuits and output as the output of the AND gate 5C, that is, the output 501 of the differentiating circuit.

This output 501 is the main signal processing system clock 1
It becomes a pulse of “H” having one clock width of 01. In the circuit shown in FIG. 1, the output of the OR gate 2 is
1 is connected, the output 501 of the differentiating circuit 5 is F
/ F3 is a signal indicating that parameter information has been set from the control system CPU.

Since the output 501 of the differentiating circuit 5 controls the output of the 2-1 select 6, the 1 immediately after the control system CPU sets the parameter information for the F / F3.
The input on the B side is selected as the output of the 2-1 selector 6 only during the clock width, and the control system CPU outputs the parameter information set in the F / F3.

At the next rising edge of the main signal processing clock 101, it is held in the F / F4. Thereafter, the A-side input is again selected and output as the output of the 2-1 selector 6, so that the F / F 4 keeps holding the value.

The output of the F / F 4 is not only fed back as an A-side input of the 2-1 selector 6 but also output as parameter information 103 to a main signal processing system circuit (not shown).

FIG. 2 is a time chart showing the operation of the parameter setting circuit according to one embodiment of the present invention. In the figure, reference numerals CK1 to CK19 denote main signal processing system clock 1
This is a reference numeral added for convenience to indicate 01 individual pulses.

In FIG. 2, the control system CP for the F / F3, which is an I / O register at a specific address, is shown.
Since the setting of the parameter information from U is shown, the control system address bus and the signal relating to the operation of the decoder 1 of the chip select signal are omitted. That is, it is assumed that the output signal 104 of the decoder 1 has an "L" level. In this case, the write signal input is also omitted as it is the output 201 of the OR gate 2 as it is.

In FIG. 2, the output signal 20 of the OR gate 2 is shown.
1 at the rising edge of the control system data bus 102
And latches and holds the data. The value “7” is held at the first rising edge, and the value “4” is held at the second rising edge. This is indicated by the output 301 of F / F3. Where "X"
Indicates that any value may be used, and is a value of a parameter set at a time before writing in the time chart of FIG.

The F / F 5A is connected to the output 2 of the OR gate 2.
A signal obtained by latching 01 with the main signal processing system clock 101 is the Q output 502 of the F / F 5A. In FIG. 2, the second falling edge of the output 201 of the OR gate 2 corresponds to the clock pulse CK.
13 and the rising edge of the clock pulse CK
There is a possibility that racing may occur at the rising edge of the clock pulse 16, but no problem occurs because the F / F 5 A can be normally latched at the rising edge of the clock pulses CK 15 and CK 17.

Next, the output Q of the F / F 5B obtained by latching the output 502 of the F / F 5A with the main signal processing system clock 101 is 503. The AND of these outputs 502 and 503 is the output 501 of the AND gate 5C. The output 501 controls the 2-1 selector 6.

When the output 501 is "H", the output 301 of the F / F 3 is selected as the output 601 of the 2-1 selector 6, and the output 301 latched by the F / F 4 with the main signal processing system clock 101 is 103. It is. In FIG. 2, "7" is latched at the rising edge of the clock pulse CK8, and "4" is latched at the rising edge of the clock pulse CK18. F / F4 here
Is the value of the output 301 of the F / F 3 selected by the 2-1 selector 6.

Since the output 501 is a signal generated at the output of the F / F operating on the main signal processing system clock 101, its change point is later than the rising edge of the main signal processing system clock 101. Further, the output 601 of the 2-1 selector 6 selected by the output 501 is further delayed. For these reasons, no racing occurs in the F / F4.

In the time chart of FIG. 6 showing the operation of the conventional example, the rising edge of the output 201 of the OR gate 2 and the rising edge of the clock pulse CK16 compete with each other, so that racing occurs and the output 103 of the F / F 4 becomes "5". In the time chart of FIG. 2 showing the operation of the embodiment of the present invention, even if the rising edge of the output 201 of the OR gate 2 and the rising edge of the clock pulse CK16 conflict with each other, No racing occurs at / F4, and no erroneous value occurs at its output 103.

In one embodiment of the present invention, a delay calculation is performed between each F / F operated by the main signal processing system clock 101 so that no racing occurs, and each F / F is arranged according to the calculation result. It is assumed that

In the embodiment of the present invention, the operation is performed as described above. However, there are important conditions for applying the parameter setting circuit according to the embodiment of the present invention, and these conditions will be described below.

In one embodiment of the present invention, an F / F operated by the main signal processing system clock 101 is used in the differentiating circuit 5, and an output 201 of the OR gate 2 which is an input of the differentiating circuit 5 is used.
In order to reliably detect the rising edge of the input signal in the configuration of this differentiating circuit 5, the period of the operation clock of the differentiating circuit 5, the parameter according to one embodiment of the present invention, In the setting circuit, an “L” section and an “H” section that are longer than the period of the main signal processing system clock 101 are required for the input signal. Also, a certain period is required in a cycle from the fall of the input signal to the fall of the input signal.

FIG. 3 is a diagram for explaining conditions to which an example of a parameter setting circuit according to an embodiment of the present invention can be applied. FIG. 4 does not apply to an example of a parameter setting circuit according to an embodiment of the present invention. It is a figure for explaining a possible condition.

In the parameter setting circuit according to one embodiment of the present invention, the period of the main signal processing system clock 101 is t, and the time when the output 201 of the OR gate 2 is "L" is t.
1, and when the period from one falling edge to the next falling edge is t2, t1 ≧ t and t2 ≧ 3t must be satisfied.

That is, the time during which the write signal from the control CPU is "L" is equal to or longer than the cycle of the main signal processing clock 101, and the minimum cycle of parameter setting for the same I / O register from the control CPU. Means that the period of the main signal processing system clock 101 must be three times or more.

FIG. 3 is a time chart of the differentiating circuit 5 when t1 = t and t2 = 3t. That is, FIG. 3 is a diagram for explaining conditions to which an example of the parameter setting circuit according to one embodiment of the present invention can be applied.

In FIG. 3, since the "L" and "H" times of the output 201 of the OR gate 2 are both longer than t,
The F / F 5A can reliably latch the "L" and "H" of the output of the OR gate 2, and each signal becomes as shown in a time chart, and the output of the differentiating circuit 5 is normally generated. F4 can normally latch the output of F / F3 at the rising edge of clock pulses CK31 and CK32.

FIG. 4 is a time chart of the differentiating circuit 5 when t1 = t and t2 = 2t. That is, FIG. 4 is a diagram for explaining conditions to which an example of the parameter setting circuit according to one embodiment of the present invention cannot be applied.

In FIG. 4, since the "L" and "H" times of the output 201 of the OR gate 2 are both equal to or longer than t,
The F / F 5A can surely latch "L" and "H" of the output of the OR gate 2, and each signal becomes as shown in a time chart, and the output of the differentiating circuit 5 is normally generated.

However, when the F / F4 latches the output of the F / F3 at the rising edge of the clock pulse CK41, the clock input of the F / F3, that is, the output 201 of the OR gate 2 also rises at the same time. This may cause the F / F 4 to latch an erroneous value. Therefore, when t1 = t and t2 = 2t, the parameter setting circuit according to the embodiment of the present invention cannot be applied.

The above conditions are conditions that can be applied to the parameter setting circuit according to one embodiment of the present invention.
In the case of a TM transmission device, the main signal processing system clock 101 is very high-speed, so that it is generally faster than the operation clock of the control system CPU. In addition, since it is unlikely that the operation parameter setting for the main signal processing system is frequently required, these conditions do not cause any problem.

As described above, the 2-1 selector 6 is added between the F / F 3 for receiving the operation parameters from the device control system CPU and the F / F 4 for outputting the operation parameters to the main signal processing system circuit. Further, the clock input signal of the F / F 3 is connected to the differentiating circuit 5, and the output signal 501 is connected to the select signal of the 2-1 selector 6.

That is, the information of the operation parameter set from the device control system CPU which operates completely asynchronously with the main signal processing system clock 101 is temporarily held in the F / F3 as asynchronous, and the clock input signal of the F / F3 is held. Is monitored by the differentiating circuit 5, the rising edge of the clock input signal of the F / F3 is detected, and the output of the 2-1 selector 6 connected to the output of the F / F3 is switched and set by the detection signal of the rising edge. The information of the operating parameters is output to the F / F 4, and the F / F 4 holds the information, so that the setting of the parameter information for the circuit of the main signal processing system is performed by the F / F 4.
The F / F 4 takes in the parameter information only when it is detected that the setting has been made by the device control system CPU with respect to 3.

Therefore, no racing occurs between the change point of the output data of the F / F 3 and the main signal processing system clock 101, and the parameter information of an erroneous value is stored in the main signal processing system as described in the conventional example. No signal is output to the circuit.

As described above, by controlling the 2-1 selector 6 disposed between F / F3 and F / F4 by the pulse of the clock input of F / F3 by the differentiating circuit 5, the input data of F / F4 is controlled. Prevents the occurrence of racing between the input clock and
It is possible to eliminate the possibility that an incorrect parameter is set in / F4.

[0056]

As described above, according to the present invention, the parameter for setting the operation parameters for the circuit of the main signal processing system from the central processing unit of the device control system asynchronously with the operation of the circuit of the main signal system. A setting circuit for receiving a first operating parameter from the central processing unit of the apparatus control system and holding the first operating mode; and a second F / F for receiving the stored content of the first F / F and outputting to the main signal system circuit A 2-1 selector for selecting one of the output of the first F / F and the output of the second F / F and outputting the selected output to the second F / F between the F / F; When a setting of an operation parameter from the central processing unit of the device control system to the first F / F is detected, a switching signal to the 2-1 selector is output, so that input data and input of the second F / F are input. The occurrence of racing with the clock can be prevented, and the second / Wrong parameter F is an effect that it is possible to eliminate the possibility of setting.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a parameter setting circuit according to one embodiment of the present invention.

FIG. 2 is a time chart showing an operation of a parameter setting circuit according to one embodiment of the present invention.

FIG. 3 is a diagram for explaining conditions to which an example of a parameter setting circuit according to an embodiment of the present invention can be applied;

FIG. 4 is a diagram for explaining conditions to which an example of a parameter setting circuit according to an embodiment of the present invention cannot be applied;

FIG. 5 is a diagram showing a configuration of a parameter setting circuit according to a conventional example.

FIG. 6 is a time chart showing an operation of a parameter setting circuit according to a conventional example.

[Explanation of symbols]

 Reference Signs List 1 decoder 2 OR gate 3, 4 flip-flop 5 differentiating circuit 6 2-1 selector

Claims (4)

[Claims] 1. A parameter setting circuit for setting operation parameters for a circuit of a main signal processing system from a central processing unit of a device control system asynchronously with the operation of the circuit of the main signal system. A first holding unit for receiving and holding an operation parameter from the central processing unit of the above, a second holding unit for receiving the held content of the first holding unit and outputting the received content to a circuit of the main signal system, And one of the output of the first holding means and the output of the second holding means is selected between the holding means and the second holding means, and is selected by the second holding means. Selecting means for outputting,
Detecting means for detecting a setting of the operation parameter from the central processing unit of the apparatus control system to the first holding means and outputting a switching signal to the selecting means when the setting is detected. Parameter setting circuit. 2. The apparatus according to claim 1, wherein said detecting means includes means for detecting a rising edge of a clock input signal to said first holding means, and outputs a switching signal to said selecting means when said rising edge is detected. 2. The parameter setting circuit according to claim 1, wherein: 3. The parameter setting circuit according to claim 2, wherein said detecting means comprises a differentiating circuit for detecting said rising edge. 4. The apparatus according to claim 1, wherein said selection means outputs the contents held by said first holding means to said second holding means when said switching signal is input from said detection means. The parameter setting circuit according to any one of claims 1 to 3.