JP2000114959A - Inverter circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an inverter circuit which suppresses a through current to realize the reduction of power consumption and power supply noise and the acceleration of a transmission speed. SOLUTION: Power supply potential and ground potential are respectively imparted to the source terminals of a P-channel field effect transistor MP1 and an N-channel field effect transistor MN1, and the drain terminals of the transistors MP1 and MN1 are connected with each other to define them as an output terminal 2. It is possible to make a through current almost zero by temporally separating the conduction of the P-channel field effect transistor and the N-channel field effect transistor. Consequently, it is possible to reduce power consumption and power supply noise.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic circuit,
In particular, the present invention relates to an inverter circuit characterized by suppressing common current.

[0002]

2. Description of the Related Art FIG. 8 shows a configuration of a conventional inverter circuit described in Integrated Circuit Engineering published by Corona (p. 150). In the conventional inverter circuit, the respective gate terminals of the N-channel field-effect transistor MN1 and the P-channel field-effect transistor MP1 are connected, and the respective sources of the N-channel field-effect transistor MN1 and the P-channel field-effect transistor MP1 are connected. Configure by connecting the terminals. A power supply potential and a ground potential are applied to the source terminal of the P-channel field-effect transistor MP1 and the source terminal of the N-channel field-effect transistor MN1, respectively. A data signal is input to an input terminal 1 and an output signal obtained by logically inverting the data signal from an output terminal 2 is obtained.

For example, when a data signal is at a Low level (eg, ground potential), the source-drain terminal of the N-channel field-effect transistor MN1 is turned off, and the P-channel field-effect transistor MP1 is connected to the source-drain terminal. The space between them becomes conductive. Charge is supplied from the drain terminal of the P-channel field-effect transistor to the load capacitance Co present at the output terminal 2, and the output signal becomes Hi level. On the other hand, when the data signal is at Hi level (for example, power supply potential), the N-channel field effect transistor M
The source-drain terminal of N1 becomes conductive, and the source-drain terminal of P-channel field-effect transistor MP1 becomes nonconductive. The charge stored in the load capacitance Co is extracted from the drain terminal of the N-channel field-effect transistor MN1, and the output signal becomes Low level. As an example, FIG. 9 shows waveforms at various parts in a conventional inverter circuit.

[0004]

However, in the conventional inverter circuit, when the data signal level changes, the source-drain terminal of the N-channel field-effect transistor MN1 and the source-drain of the P-channel field-effect transistor MP1 are changed. Since both of the drain terminals are in a semi-conductive state, a through current flows from the power supply potential supply terminal 3 to the ground potential supply terminal 4.

The amount of through current increases as the gate width of an N-channel field-effect transistor and a P-channel field-effect transistor increases. Particularly, when an inverter circuit is used as an output buffer circuit having a large current driving capability, a through current reaches about several 10 mA because a field-effect transistor having a relatively large gate width (several 100 μm) is used. In such a case, the through current causes an increase in power consumption and generates noise on the power supply line and the ground line.

In addition, in the conventional inverter circuit, since a part of the electric charge necessary for changing the output signal level becomes a through current, the accumulation or extraction of the electric charge with respect to the load capacitance becomes insufficient, and the transition of the output signal changes. It was difficult to increase the speed.

As described above, in the conventional inverter circuit, it is difficult to reduce power consumption due to generation of a through current. In addition, power supply noise generated by the inverter circuit leaks into other circuits due to power / ground lines or airborne transmission, which may interfere with transmission signals. at the same time,
Since it is difficult to increase the transition speed of the output signal, it is difficult to increase the transmission speed.

An object of the present invention is to provide an inverter circuit that suppresses a through current in order to reduce power consumption and power supply noise and increase transmission speed.

[0009]

In order to achieve the above object, according to the present invention, there is provided a differentiation circuit for converting a data signal inputted from the outside into a differentiation signal, and a first level shifter for increasing a DC level of the differentiation signal. A second level shift circuit for lowering the DC level of the differential signal; a P-channel field-effect transistor for inputting an output signal of the first level shift circuit to a gate terminal; An N-channel field-effect transistor for inputting an output signal of the circuit to a gate terminal; providing a power supply potential and a ground potential to source terminals of the P-channel field-effect transistor and the N-channel field-effect transistor, respectively; Connecting the drain terminals of the channel field-effect transistor and the N-channel field-effect transistor to each other to form an output terminal; Providing an inverter circuit, characterized.

That is, in the above configuration, the drain-source terminal of the P-channel field-effect transistor becomes conductive when the data signal rises, while the drain-source terminal of the N-channel field-effect transistor is connected between the drain-source terminal of the data signal. It becomes conductive at the time of falling. By temporally separating the conduction between the P-channel field-effect transistor and the N-channel field-effect transistor, the through current can be reduced to substantially zero. As a result, power consumption and power supply noise can be reduced. Further, since the through current stops flowing, the accumulation and extraction of the electric charge with respect to the load capacitance become effective, and the transition speed of the output signal at the output terminal is improved.

[0011]

FIG. 1 shows a first embodiment of an inverter circuit according to the present invention. In FIG. 1, an inverter circuit includes a differentiating circuit 5 for converting a data signal input from the outside into a differentiated signal, a first level shift circuit 6a for increasing a DC level of the differentiated signal, and a DC level of the differentiated signal. A falling second level shift circuit 6b;
And a N-channel field-effect transistor MN1 for inputting the output signal of the second level shift circuit 6b to the gate terminal, and an N-channel field-effect transistor MN1 for inputting the output signal of the second level shift circuit 6b to the gate terminal.

The P-channel field-effect transistor MP
1 and the source terminal of the N-channel field-effect transistor MN1 are supplied with a power supply potential and a ground potential, respectively.
The drain terminals of the channel field-effect transistor MP1 and the N-channel field-effect transistor MN1 are connected to each other to form an output terminal 2.

Next, the operation of the inverter circuit shown in FIG. 1 will be described. In FIG. 1, a data signal Vi input from the outside is converted into a differentiated signal by a differentiating circuit. The differentiated signal has a signal waveform Va as shown in FIG. 5B in which the signal level differs between the rising and falling of the data signal. The differential signal Va is set to a signal level as shown in FIGS. 5C and 5D via the level shift circuits 6a and 6b, respectively. Here, Vtp and Vtn indicate the threshold voltages of the P-channel field-effect transistor MP1 and the N-channel field-effect transistor MN1, respectively.

P-channel field-effect transistor MP1
Becomes conductive when the signal Vb input to the gate terminal becomes Vb <Vcc-Vtp. On the other hand, the N-channel field-effect transistor MN1 receives the signal Vc input to the gate terminal.
Becomes conductive when Vc> Vtn. As a result, P
In the channel field effect transistor MP1 and the N channel field effect transistor MN1,
Drain currents Ip and In as shown in FIGS. 5E and 5F are generated. P-channel field-effect transistor MP1
Drain current Ip flows only when the data signal falls, while the N-channel field-effect transistor MN1
Drain current In flows only when the data signal falls. On the other hand, since Ip and In do not flow at the same time, the through current It becomes almost zero. As a result, power consumption and power supply noise are reduced. Further, since the through current It stops flowing, the accumulation and extraction of the electric charge with respect to the load capacitance Co become effective, and the output signal V
The transition speed of o improves.

FIG. 2 shows a second embodiment of the inverter circuit according to the present invention. In FIG. 2, a delay circuit 7 for delaying a data signal input from the outside, a comparator 8 for comparing the data signal with an output signal of the delay circuit 7, and a second circuit for increasing the DC level of the output signal of the comparator 8 1 level shift circuit 6a, a second level shift circuit 6b for lowering the DC level of the output signal of the comparator 8, and a P-channel electric field for inputting the output signal of the first level shift circuit 6a to the gate terminal. N which inputs the output signal of the effect type transistor MP1 and the second level shift circuit 6b to the gate terminal.
A channel field effect transistor MN1 is provided.

The P-channel field-effect transistor MP
1 and the source terminal of the N-channel field-effect transistor MN1 are supplied with a power supply potential and a ground potential, respectively.
The drain terminals of the channel field-effect transistor MP1 and the N-channel field-effect transistor MN1 are connected to each other to form an output terminal 2.

Next, the operation of the inverter circuit shown in FIG. 2 will be described. In FIG. 2, a data signal Vi input to an input terminal 1 is branched, and one is input to a delay circuit 7.
The delay circuit 7 generates a signal waveform Vs whose phase is shifted by a delay time td with respect to the data signal Vi. Comparator 8
Are input with the data signal Vi and the output signal Vs of the delay circuit, respectively. As a result, the comparator 8 generates a comparison signal Va as shown in FIG. The comparison signal Va is supplied via the level shift circuits 6a and 6b, as shown in FIG.
The signal level is set as shown in FIG.

At this time, the signal Vb input to the gate terminal of the P-channel field-effect transistor MP1 is Vb <Vcc-
When it reaches Vtp, it becomes conductive. On the other hand, the N-channel field effect transistor MN1 is turned on when the signal Vc input to the gate terminal satisfies Vc> Vtn. As a result, the drain current Ip of the P-channel field-effect transistor MP1 flows only when the data signal falls,
On the other hand, the drain current In of the N-channel field effect transistor MN1 flows only when the data signal falls. Since Ip and In do not flow at the same time, the through current It becomes almost zero. As a result, power consumption and power supply noise are reduced. Further, since the through current stops flowing, the accumulation and extraction of the electric charge with respect to the load capacitance Co become effective, and the transition speed of the output signal Vo at the output terminal 2 is improved.

FIG. 3 shows a third embodiment of the inverter circuit according to the present invention. In FIG. 3, an input terminal 1 is formed by connecting gate terminals of a P-channel field-effect transistor MP1 and an N-channel field-effect transistor MN1 to each other.
And an N-channel field-effect transistor in which the drain terminal is connected to the source terminal of the P-channel field-effect transistor MP1 and the drain terminal is connected to the N-channel field-effect transistor. N-channel field effect transistor M having a drain terminal connected to the source terminal of MN1
N2, a P-channel field effect transistor MP2
And a source potential of the N-channel field-effect transistor MN2, respectively, and a bias voltage is applied to the gate terminal of the P-channel field-effect transistor MP2 and the gate terminal of the N-channel field-effect transistor MN2, respectively. From outside.

Next, the operation of the inverter circuit shown in FIG. 3 will be described. In FIG. 3, a data signal is input to an input terminal 1. Further, bias voltages VBP and VBN are applied to the bias voltage supply terminals 9a and 9b, respectively. At this time, the P-channel field-effect transistor MP2 and the N-channel field-effect transistor MN2 each act as a current source, and a drain current IB controlled by a bias voltage.
P and IBN are output. IBP and IBN are P
When the channel field effect transistor MP1 and the N channel field effect transistor MN1 are turned on,
The rising time and falling time of the output signal Vo are supplied to the output terminal 2 and are independently set. Therefore,
When the inverter circuit of FIG. 3 according to the present invention is used, the rise time and the fall time of the output signal Vo can be independently controlled by controlling the externally applied bias voltages VBP and VBN.

The inverter circuit shown in FIG. 3 has a feature that through current can be suppressed as compared with a conventional inverter circuit by including a P-channel field-effect transistor MP2 and an N-channel field-effect transistor MN2. This is a P-channel field-effect transistor MP
This is because the two-channel and N-channel field-effect transistors MN2 act as current sources and control the drain currents IBP and IBN. FIG. 7 is an example of comparing the through current It between the inverter circuit of FIG. 3 and a conventional inverter circuit. In the conventional inverter circuit, the through current It
Changes according to the input data signal level, and FIG.
The characteristic has a peak value as shown in FIG. On the other hand, in the inverter circuit of FIG.
Determined by either BP or IBN. Therefore,
The through current It is almost constant with respect to the input data signal level Vi as shown in FIG. 7B. As a result, the inverter circuit of FIG. 3 according to the present invention suppresses the through current It as compared with the conventional inverter circuit, and reduces power consumption and power supply noise.

FIG. 4 shows a fourth embodiment of the inverter circuit according to the present invention. FIG. 4 shows an embodiment using an inverter circuit as an output buffer circuit. A data signal is externally applied to the main inverter circuit 100 and the auxiliary inverter circuit 200 via the terminal 1. The output of the main inverter circuit 100 and the output of the auxiliary inverter circuit 200 are connected to form an output terminal 2. Here, as the circuit configuration of the main inverter circuit 100, the inverter circuit shown in FIG. 1 is used. Further, the inverter circuit shown in FIG. 3 is used as the circuit configuration of the auxiliary inverter circuit 200.

The main inverter circuit 100 generates a large current at the output terminal when the data signal makes a transition as described above, and is therefore effective for accumulating charges in the load capacitance or extracting charges. The main inverter circuit 100 is used to increase the transition speed of the output signal.

However, the main inverter circuit 100
In the case where the same code is continuous and the transition of the data signal does not occur, the output signal level may fluctuate.
This is due to a leak current at the output terminal 2. In particular, when an inverter circuit is used as an output buffer circuit, a circuit connected to the output terminal 2 may generate a leakage current of about several hundred μA.

In order to compensate for the leakage current, the auxiliary inverter circuit 200 is used together. Auxiliary inverter circuit 200
Means that the data signal level is Hi or Low as described above.
At this time, current is supplied to the output terminal. Since the value of the current supplied to the output terminal can be controlled by the bias voltage applied to the bias voltage supply terminals 9a and 9b, the bias voltage is set so as to compensate for the leakage current.

According to the above configuration, even when a load capacitance is provided at the output terminal and a leak current is generated, the transition speed of the output signal is increased, and the output level does not fluctuate even when the same sign is continuous. An inverter circuit can be realized.

[0027]

According to the present invention, the through current of the inverter circuit can be suppressed. As a result, power consumption and power supply noise can be reduced. In addition, since the shoot-through current is suppressed, the accumulation and extraction of the charges with respect to the load capacitance become effective, and the transition speed of the output signal at the output terminal is improved.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a basic configuration of an inverter circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating a basic configuration of an inverter circuit according to a second embodiment of the present invention.

FIG. 3 is a diagram illustrating a basic configuration of an inverter circuit according to a third embodiment of the present invention.

FIG. 4 is a diagram illustrating a basic configuration of an inverter circuit according to a fourth embodiment of the present invention.

FIG. 5 is a diagram illustrating waveforms of respective parts of the inverter circuit according to the first embodiment of the present invention.

FIG. 6 is a diagram illustrating waveforms of respective parts of the inverter circuit according to the second embodiment of the present invention.

FIG. 7 is a diagram showing an example in which a through current is compared between a conventional inverter circuit and an inverter circuit according to a third embodiment of the present invention.

FIG. 8 is a diagram showing a basic configuration of a conventional inverter circuit.

FIG. 9 is a diagram showing waveforms at various points in a conventional inverter circuit.

[Explanation of symbols]

1 ... input terminal, 2 ... output terminal, 3 ...
Power supply potential supply terminal, 4 ... ground potential supply terminal,
5 Differentiator circuit 6a First level shift circuit 6b Second level shift circuit 7 Delay circuit 8 Comparator 9a First
9b: second bias voltage supply terminal, 100: main inverter circuit, 200: auxiliary inverter circuit, MN1, MN2: N-channel field effect transistor, MP1, MP2: P-channel field effect transistor, Co: load capacitance parasitic on the output terminal 2;
Vi: data signal, Va: differentiation circuit 5 or comparator 8
Vb: output signal of the first level shift circuit 6a, Vc: output signal of the second level shift circuit 6b, Vo
... Inverter circuit output signal, Ip ... Drain current of P-channel field-effect transistor MP1, In ... Drain current of N-channel field-effect transistor MN1, I
BP: drain current of P-channel field-effect transistor MP2; IBN: drain current of N-channel field-effect transistor MN2; It: through-current or consumption current of the inverter circuit.

Claims (6)

[Claims] 1. A differential circuit for converting a data signal inputted from the outside into a differential signal, a first level shift circuit for increasing a DC level of the differential signal, and a second level circuit for decreasing a DC level of the differential signal. A level shift circuit, a P-channel field effect transistor for inputting an output signal of the first level shift circuit to a gate terminal, and an N-channel field effect type for inputting an output signal of the second level shift circuit to a gate terminal A power supply potential and a ground potential respectively applied to source terminals of the P-channel field-effect transistor and the N-channel field-effect transistor; and drains of the P-channel field-effect transistor and the N-channel field-effect transistor. An inverter circuit, wherein terminals are connected to each other to form an output terminal. 2. A delay circuit for delaying a data signal input from the outside, a comparator for comparing the data signal with an output signal of the delay circuit, and a first level for increasing a DC level of the output signal of the comparator. A shift circuit, a second level shift circuit for lowering a DC level of an output signal of the comparator, a P-channel field effect transistor for inputting an output signal of the first level shift circuit to a gate terminal, An N-channel field-effect transistor for inputting an output signal of the second level shift circuit to a gate terminal, and applying a power supply potential and a ground potential to source terminals of the P-channel field-effect transistor and the N-channel field-effect transistor, respectively. Connecting the drain terminals of the P-channel field-effect transistor and the N-channel field-effect transistor to each other, An inverter circuit characterized by: 3. An inverter in which the gate terminals of the first P-channel field-effect transistor and the first N-channel field-effect transistor are connected to form an input terminal, and the drain terminals are connected to form an output terminal. In the circuit, a drain terminal is connected to a source terminal of the first P-channel field-effect transistor, and a drain terminal is connected to a source terminal of the first N-channel field-effect transistor. A second N-channel field-effect transistor, a source terminal of the second P-channel field-effect transistor, and a second terminal.
The power supply potential and the ground potential are applied to the source terminal of the N-channel field-effect transistor, respectively, and the gate terminal of the second P-channel field-effect transistor and the gate terminal of the second N-channel field-effect transistor, respectively. An inverter circuit characterized in that a bias voltage is externally applied. 4. The inverter circuit according to claim 1, further comprising an inverter circuit, wherein said input terminals are connected to each other and said output terminals are connected to each other. 5. The inverter circuit according to claim 1, wherein a gate terminal of the P-channel field-effect transistor and a gate terminal of the N-channel field-effect transistor are connected to each other as an input terminal, and a drain terminal. An inverter circuit comprising: an inverter circuit that connects the input terminals to each other to form an output terminal; and connects the input terminals to each other and the output terminals to each other. 6. An inverter circuit comprising a transmission device comprising the inverter circuit according to claim 1.