JP2000106653A - Solid-state image pickup device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a CMOS image sensor capable of conducting interface operation in its inside. SOLUTION: A solid-state image pickup element is provided with a plurality of unit cells 1 including a photoelectric conversion section and an amplifier section, that amplifies the output of the photoelectric conversion section and outputs the amplified signal and arranged in two-dimension in row and column directions on a semiconductor substrate 4, a plurality of vertical signal lines 8 through which the amplified signal is transmitted in the column direction, and a vertical register 5 and a horizontal register 11 that respectively scan the unit cells arranged two-dimensionally in the row and column directions. In the element, a 2H line memory +2H line adder circuit 6, that stores the amplified signals of the upper and lower pixels corresponding to 2 pixels at least and sums them, is provided to obtain the objective image pickup device.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state imaging device, and more particularly to a CMOS solid-state imaging device capable of interlaced operation.

[0002]

2. Description of the Related Art In recent years, as a solid-state imaging device, an APS (Active Pixel Sens) has been used for both a CMOS type and an amplification type.
or) type solid-state imaging device (hereinafter referred to as C
MOS image sensors) are being developed and commercialized as low power consumption solid-state imaging devices for mobile devices. Current CMOS image sensors generally use progressive scanning for reading out the signals of a row in order.

FIG. 10 is a diagram schematically showing the internal configuration of a conventional CMOS image sensor. The unit cell 1 includes a photodiode and an amplification transistor that amplifies a detection signal of the photodiode. Here, only one unit cell is described in the image area 2 for simplification of the drawing, but in reality, the unit cells 1 are arranged in a two-dimensional matrix. The row from which the detection signal is read is determined by the vertical register (V register) 5, and the detection signal detected in the unit cell of the corresponding row is stored in the 1H memory 100 in the 1H memory 100 through the first vertical signal line 8. Is done. The detection signal stored in the 1H memory 100 on a row-by-row basis is output from the horizontal selection transistor 1
By turning on / off 4, the signal passes through the horizontal signal line 10, is amplified by the output amplifier 12, and is output. V register 5 and H
The timing generator (TG) 3 drives the register 11 and the like.

[0004] However, although progressive scanning is optimal for personal computers and portable devices, upper and lower rows to be added are different in the A field and the B field in order to support the current television system such as the NTSC system or the PAL system. Must be interlaced.

[0005] However, it is difficult for a CMOS image sensor to perform addition without generating noise inside the sensor.
It was difficult to perform interlaced scanning. In order to solve this problem, for example, Ando of NHK proposes to create an addition means above and below the image area and add the image area (see Reference: Ando et al., "1/4 inch 250,000 pixel amplification type"). Solid State Imaging Device AMI ", Journal of the Institute of Television Engineers of Japan, Vol. 49, No. 2, pp. 188-195, 1995). However, since it is necessary to add the upper and lower pixel signals with a photodiode in a small area of the unit pixel, it is difficult to miniaturize the unit pixel, and since the photodiode potentials of the upper and lower pixels are different for each row, the darkness is low. There was a problem that the current and the fixed pattern noise differed from row to row.

There is also a system in which the output of a chip of a CMOS image sensor is read out in a progressive system and converted into an interlace system by addition of an external system. However, an extra circuit is added to increase the system cost. I will.

[0007]

SUMMARY OF THE INVENTION The present invention has been made in consideration of the above problems, and provides a CMOS image sensor capable of performing an interlace operation inside the sensor. In addition, a function of performing an interlace operation for each column is provided so that random noise and fixed pattern noise can be reduced and a unit cell can be miniaturized.

[0008]

A first invention includes a photoelectric conversion unit and an amplification unit that amplifies an output of the photoelectric conversion unit and outputs an amplified signal. A plurality of unit cells arranged two-dimensionally, a plurality of vertical signal lines transmitting the amplified signal in a column direction, and a vertical line scanning the unit cells arranged two-dimensionally in a row direction and a column direction, respectively. A register, a horizontal register, a storage unit for independently storing at least two amplified signals transmitted through the vertical signal line for each column, and an adding unit for adding the at least two amplified signals. Is a solid-state imaging device.

A second invention includes a photoelectric conversion unit and an amplification unit that amplifies an output of the photoelectric conversion unit and outputs an amplified signal, and is two-dimensionally arranged on a semiconductor substrate in a row direction and a column direction. A plurality of unit cells, a plurality of first vertical signal lines transmitting the amplified signal in a column direction, a vertical register for scanning the unit cells arranged two-dimensionally in a row direction and a column direction, and a horizontal register. A register, a second vertical signal line electrically separated from the first vertical signal line, at least one second vertical signal line provided for each of the first vertical signal lines, and a second vertical signal line for each column. And at least two storage units, each including a transistor and a capacitor for storing the detection signal transmitted through the vertical signal line, and an addition unit for adding the detection signals stored in these storage units. Solid-state imaging device It is.

According to a third aspect of the present invention, in the solid-state imaging device according to the first or second aspect, at least two rows of detection signals accumulated in the accumulation section are added within a horizontal blanking period. Device.

According to the present invention, the interlace operation is performed by C
This can be performed inside the MOS image sensor. In addition, an interlace operation can be performed for each column so that random noise and fixed pattern noise can be reduced, and a case where a unit cell is miniaturized can be handled. In addition, by adding at least the upper and lower two pixels during the horizontal retrace period, the system cost can be reduced as compared with the case where the addition is performed outside the sensor.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram illustrating a schematic configuration of a CMOS image sensor (hereinafter, simply referred to as a sensor) according to an embodiment of the present invention. The sensor drives an image area 2 composed of unit cells 1 on a semiconductor substrate 4, a vertical register (V register) 5 and a horizontal register (H register) 11 for driving the cells, a V register 5 and an H register 11, and the like. Timing generator (TG) 3
And a first vertical signal line 8 serving as an output of the unit cell 1, a line memory for two rows of signals of the first vertical signal line 8, and a 2H line memory + 2H line addition having a line addition function for two rows It comprises a circuit 6, a horizontal selection transistor 14 for selecting each column, a horizontal signal line 10, and an output amplifier 12. Here, only one unit cell is described in the image area 2 for simplification of the drawing, but in reality, the unit cells 1 are arranged in a two-dimensional matrix. Sensor is 60
Hz (50 Hz in the case of the PAL system), the A field and the B field are stored separately. By the 2H line memory + 2H line adding circuit 6, 2 in the A field
Addition of N rows and (2N + 1) rows, and (2N
-1) Addition of rows and 2N rows is performed. N is 1, 2,
It is a natural number of 3, ...

FIG. 2 shows a 2H line memory of this embodiment +
FIG. 3 is a diagram illustrating a schematic configuration of a 2H line addition circuit 6-a.
The first vertical signal line 8 (8-1, 8-2,...) Is connected to the sample and hold transistor 29 (29-1, 29-2,.
..) And the capacitor C1 (C1-1, C1-2,...) And the second vertical signal line 17 (17-1, 17-2,.
…) Is connected. Here, for simplification of the drawing, the first
Although only two vertical signal lines 8 are described, a plurality of vertical signal lines 8 are actually arranged in the horizontal direction. Second vertical signal line 1
7 includes a transistor 23 (23-1, 23-2,...)
, And the capacitor C2 (C2-1, C2-2,...) Are connected in series for two sets (the capacitor C2 and the transistor 23, and the capacitor C3 (C3-1, C3-2,...) And the transistor 26 (26- 1, 26-2,...) Are connected. Here, the signal voltage of the 2N row is the transistor 2
3, and the signal voltage of the (2N + 1) -th row is stored in the capacitor C3 through the transistor 26.
The signal voltage of the 2N-th row and the signal voltage of the (2N + 1) -th row are added by the second vertical signal line 17.

The sample and hold transistor 29 has an S
/ H line 18, the second vertical signal line 1
7 to the signal voltage. Clamp transistor 25 (2
5-1, 25-2,..., Correspond to the ON voltage of the clamp line 20 and correspond to the second vertical signal lines 17 (17-1, 17-2).
2,...) Are arranged to clamp the voltages. The signal voltage of the second vertical signal line 17 is read out to the horizontal signal line 10 via the horizontal selection transistor 14 (14-1, 14-2,...).

Note that the clamp transistor 25 is not always necessary for the interlace operation of the present invention. Therefore, three transistors (23, 26, 2) are provided for each column.
9) If there are three capacitors (C1, C2, C3),
According to the present invention, the interlace operation can be performed with a small number of parts, the system cost can be reduced, and the interval between the first vertical signal lines 8 is not affected.

The details of the 2H line memory + 2H line addition circuit 6-a will be described later with reference to a driving timing chart. FIG. 3 shows a unit cell 1 of the present embodiment.
It is a figure which shows schematic structure of -a. What is necessary for the unit cell 1 only needs to include at least the photoelectric conversion unit that receives light and converts it into an electric signal and the amplifying unit that amplifies the electric signal. FIG. 3 shows a photodiode 37 as a photoelectric conversion unit, a detection node 35 for detecting a signal voltage of the photodiode 37, an amplifying transistor 30 for amplifying the signal voltage detected by the detection node 35, and a circuit for selecting each row. It comprises a selection transistor 32 and a read transistor 36 for reading a signal from the photodiode 37.

The operation of the equivalent circuit 1-a of the unit cell will be briefly described. First, when the row from which the signal voltage is read out is determined by the V register 5 in FIG. 1, the selection transistor 32 connected to the address line 40 corresponding to this row is turned “ON”,
The row is activated. Next, before the signal of the photodiode 37 is read, the reset transistor 34 connected to the reset line 39 is turned “ON” to reset the detection node to the power supply voltage 33. After that, the read transistor 36 connected to the lead wire 38 is turned “ON”, and the signal voltage is read to the detection node 35. Therefore, the reset signal is output to the vertical signal line 8 first, and then the signal voltage is output.

FIG. 4 is a diagram showing a schematic configuration of a unit cell 1-b which is a first modification of the present embodiment and is a modification of the unit cell 1-a. This circuit diagram differs from FIG. 3 in that the read transistor 36 of FIG. 3 is not provided. In this case, a signal voltage is first output to the vertical signal line 8, and then a reset signal is output. In this modification, since the read transistor 36 of FIG. 3 is not required, the unit cell 1 can be made smaller.

FIG. 5 is a diagram schematically showing a drive timing chart of the present embodiment. Here, 2H shown in FIG.
FIG. 2 will be described in detail based on a drive timing chart in the case of the line memory + 2H line addition circuit 6-a and the unit cell equivalent circuit 1-a shown in FIG. During the horizontal flyback period 200, the accumulation of the signal voltage in the 2Nth row, that is, the accumulation of the signal voltage in the capacitor C2, and (2N +
1) The accumulation of the signal voltage in the row, that is, the accumulation of the signal voltage in the capacitor C3, and the addition of the signal voltages accumulated in the capacitors C2 and C3 in the second vertical signal line 17 are performed.

In this case, the address line 40-2 of the 2Nth row
When N is selected, the 2Nth row is activated. At this time,
Only the transistor 23 connected to the H1 line 19 has "O
Since the state is “N”, the second vertical signal line 17 is reset to the clamp voltage.
Is turned ON, and the signal voltage output to the first vertical signal line 8 is stored in the capacitor C2. Similarly, H2 line 2
Only the transistor 26 connected to No. 2 is turned on, and the signal of the (2N + 1) th row is stored in the capacitor C3. Finally, transistors 23 and 26 are simultaneously set to "O"
N ", the signals of the upper and lower two rows are added by the second vertical signal lines 17 (17-1, 17-2, ...). In this case, one second vertical signal line 17 is used. This addition is performed by 2N in the A field.
Addition of (2N + 1) rows and (2N + 1) rows is performed by adding (2N
-1) Addition of rows and 2N rows is performed.

FIG. 6 is a diagram schematically showing a drive timing chart of a first modification of the present embodiment. FIG. 6 shows the 2H line memory + 2H line addition circuit 6-a shown in FIG.
In the case of the combination of the equivalent circuits 1-b of the unit cells described in FIG. During the horizontal flyback period 200, the 2Nth address line is selected, and at this time, the second vertical signal line 17 is clamped. Then, by turning on the reset transistor 34 of the unit cell 1-b, (Vsig-Vre
set) is written to the capacitor C2. The capacitor to be written first may be C2 or C3.
Subsequent operations are performed in the same manner as in FIG. 5, and signal addition is performed using one second vertical signal line 17.

The capacitors C2 and C3 have the same size. If they are set to the same size, the weights of the 2N-row and (2N + 1) -row signals are the same. Can be added, emphasizing edges and improving resolution,
A sensor can be provided. Such a function can be widely performed without departing from the scope of the claims of the present invention.

FIG. 7 shows a second modification of the present embodiment,
3H line memory + 3H which is a modification of the addition circuit 6-a
3 shows a schematic configuration of a line addition circuit 6-b. In this modification, addition of three lines is performed, and therefore, the capacitors C4 (C4-1, C4-2, C4-2, C3-2) for storing the detection signal of the third line.
..), The transistor 43 (43-1, 43-2,...) And the H3 signal line 41 are required. In the case of the present embodiment, the operation is the same as in FIGS. 5 and 6 and the description is omitted, except that the number of rows to be added is increased to three. However, if the above-mentioned weighted addition is performed, Together with the interlacing operation, it is effective for edge enhancement and improvement of light random noise. Further, this circuit configuration can be applied to other uses.
For example, signals of 2N rows are stored in C2 and C3, and (2N +
1) By accumulating the row signals in C4, two-line edge enhancement can be performed. Also, the signals of 2N rows are represented by C2, C
3, the signal can be tripled by storing it in C4.

FIG. 8 shows a schematic configuration of a 2H line memory + 2H line addition circuit 6-c which is a modification 3 of the present embodiment and is a modification of the addition circuit 6-a. In this example, two second vertical signal lines are required for one first vertical signal line 8 (8-1 in FIG. 8). That is, 2N
The signal in the row is a capacitor 51 (51-1, 51-2,
..), And the signal in the (2N + 1) -th row is
7 (57-1, 57-2,...) And the horizontal selection transistors 14, 54 (54-1, 54-2,...), 59
By turning on (59-1, 59-2,...) At the same time, the signal in the 2Nth row and the signal in the (2N + 1) th row can be added. The operation is the same as in the case of FIGS. 5 and 6, and the details are omitted.
Between these operations.

FIG. 9 shows a schematic configuration of a 2H line memory + 2H line addition circuit 6-d which is a modification 4 of the present embodiment and is a modification of the addition circuit 6-a. In this example, two capacitors C2 and C3 are connected to the second vertical signal line 17 via transistors 23 and 26, respectively. The operations are the same as those in FIGS. 5 and 6, and the details are omitted, but these operations are performed during the horizontal blanking period 200. In FIG. 9, the circuit configuration is different because a noise elimination circuit is also added as described below, but the interlace operation can be performed similarly. The slice transistor 70 (70-1, 70
The first vertical signal line 8 is connected to the gate of (−2,...), And the slice capacitance 73 (73-1, 73−) is connected to the source.
2), the slice reset transistor 71 (71−
, 71-2,...) Are connected. The components 70, 71, and 73 of each noise removal circuit are driven by a slice reset transistor drive line 72, a slice reset transistor source line 74, and a slice capacitance drive line 75.

[0026]

According to the present invention, the interlacing operation of the CMOS image sensor can be performed inside the chip while minimizing the generation of random noise and fixed pattern noise and miniaturizing the unit cell.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a schematic configuration of a CMOS image sensor according to an embodiment.

FIG. 2 is a diagram illustrating a schematic configuration of a 2H line memory + 2H line addition circuit 6-a according to the embodiment;

FIG. 3 is a diagram showing a schematic configuration of a unit cell 1-a of the present embodiment.

FIG. 4 is a first modification of the present embodiment, and is a unit cell 1
It is a figure which shows the schematic structure of unit cell 1-b which is a modification of -a.

FIG. 5 is a diagram schematically illustrating a drive timing chart of the present embodiment.

FIG. 6 is a diagram schematically illustrating a drive timing chart of a first modification of the present embodiment.

FIG. 7 is a second modification of the present embodiment, in which an adding circuit 6 is used.
The schematic configuration of a 3H line memory + 3H line addition circuit 6-b, which is a modification example of -a, is shown.

FIG. 8 is a modification example 3 of the embodiment, in which an adding circuit 6 is used.
It is a figure which shows the schematic structure of 2H line memory + 2H line addition circuit 6-c which is a modification of -a.

FIG. 9 is a modification example 4 of the embodiment, in which an addition circuit 6 is used.
It is a figure which shows the schematic structure of 2H line memory + 2H line addition circuit 6-d which is a modification of -a.

FIG. 10 is a diagram schematically showing an internal configuration of a conventional CMOS image sensor.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 unit cell 2 image area 3 TG 4 semiconductor substrate 5 V register 6 2H line memory + 2H line adder circuit 8 first vertical signal line 10 horizontal signal line 11 H register 12 output amplifier 14, 54, 59 horizontal selection transistor 17 second Vertical signal line 18 S / H line 19 H1 line 20 clamp line 21 bias voltage line 22 H2 line 23, 26, 43 transistor 25 clamp transistor 29 sample hold transistor 32 selection transistor 33 power supply voltage 34 reset transistor 35 detection node 36 read transistor 37 Photodiode 38 Lead wire 39 Reset line 40 Address line 43 H3 signal line 70 Slice transistor 71 Slice reset transistor 72 Slice reset transistor drive line 3 slices capacitance 74 slices reset transistor source line 75 slices capacitor driving line 100 IH memories 200 horizontal blanking period C1, C2, C3, C4,50,51,57 capacitor

Claims (3)

[Claims] A plurality of units including a photoelectric conversion unit and an amplification unit that amplifies an output of the photoelectric conversion unit and outputs an amplified signal, the unit being two-dimensionally arranged in a row direction and a column direction on a semiconductor substrate. A plurality of vertical signal lines for transmitting the amplified signal in a column direction; a vertical register and a horizontal register for scanning the unit cells arranged two-dimensionally in a row direction and a column direction; A solid-state imaging device comprising: a storage unit that independently stores at least two amplified signals transmitted through the vertical signal line; and an adding unit that adds the at least two amplified signals. 2. A plurality of units each including a photoelectric conversion unit and an amplification unit that amplifies an output of the photoelectric conversion unit and outputs an amplified signal, and is two-dimensionally arranged on a semiconductor substrate in a row direction and a column direction. A plurality of first vertical signal lines for transmitting the amplified signal in a column direction; a vertical register and a horizontal register for scanning the two-dimensionally arranged unit cells in a row direction and a column direction, respectively; A second vertical signal line electrically separated from the first vertical signal line and provided at least one or more for each of the first vertical signal lines; and a second vertical signal line for each column. A solid-state imaging device, comprising: at least two storage units, each including a transistor and a capacitor that store the detection signal transmitted through the storage unit, and an addition unit that adds the detection signals stored in the storage units. apparatus. 3. The solid-state imaging device according to claim 1, wherein at least two rows of detection signals stored in the storage unit are added during a horizontal blanking period.