JP2000101356A - High frequency power amplifier circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce production cost and to make a communication device small- sized by inputting a positive control signal to the gate electrode of an enhancement field effect transistor and also extracting an amplified high frequency signal from a drain electrode as an output signal. SOLUTION: A control signal S3 is inputted to the gate electrode G of an E-type FET5 via a gate terminal R4. When performing on control of the E-type FET5, a positive signal voltage is applied to the gate electrode G of the E-type FET5. Further, a drain current ID supplied to a D type FET6 is made to change according to the voltage value of the control signal S3. Thus, the amplification of a high frequency signal S1 is subjected to variable control according to the voltage value of the control signal S3. The voltage value of the control signal S3 is lowered, and the E type FET5 is cut off to stop a high-frequency power amplifier circuit 4 in the middle of an amplification operation. Then, a circuit configuration is extremely simplified, because a circuit generating positive and negative signal voltages is no longer needed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high frequency power amplifier circuit.

[0002]

2. Description of the Related Art Two depletion-type field-effect transistors (hereinafter referred to as "D-type FETs") are provided in a signal amplifier of a communication circuit built in a communication device such as a portable telephone or a cordless telephone.
) Is widely used.

First, a D-type FET will be schematically described with reference to FIG. In the D-type FET, the maximum drain current ID flows between the drain electrode D and the source electrode S when the voltage VGS between the gate electrode G and the source electrode S is near zero (V). Furthermore, when the voltage VGS is increased in the negative direction, the drain current ID gradually decreases, and the pinch-off voltage VP
In the following, there is a characteristic that the drain current ID stops flowing.

Next, the circuit configuration and circuit operation of the high-frequency power amplifier circuit 1 will be described with reference to FIG.

[0005] The high-frequency power amplifier circuit 1 comprises a first D-type FE.
It comprises T2 and a second D-type FET3. First D
The source electrode S of the type FET 2 is connected to the drain electrode D of the second D-type FET 3. The drain electrode D of the first D-type FET 2 is connected to a positive power supply Vdd. As a result,
A DC current is supplied to the first D-type FET 2. The source electrode S of the second D-type FET 3 is grounded. In addition,
The power supply Vdd is, for example, a 3.6 V DC power supply.

The gate electrode G of the second D-type FET 3 has:
A signal in a frequency band allocated to the communication device, for example, 8
A high frequency signal S1 such as 00 MHz or 900 MHz
1 is input. Note that the horizontal axis t is a time axis.

The gate electrode G of the first D-type FET 2 has:
The control signal S2 is input via the terminal T2. Usually, the control signal S2 is a square wave, and controls the amplification of the high frequency signal S1.

From the drain electrode D of the first D-type FET 2, an output signal Vout obtained by amplifying the high-frequency signal S1 is taken out via a terminal T3.

When the high-frequency power amplifier 1 amplifies the high-frequency signal S1, the control signal S2 turns on the first D-type FET 2 and supplies a predetermined drain current ID to the second D-type FET 3.

For example, when the first D-type FET 2 is to be turned on during the period from time t1 to t2, the first D-type FET 2 is turned on.
A control signal S2 having a positive voltage value is supplied to the gate electrode G of the type FET2. The drain current I supplied to the second D-type FET 3 depends on the voltage value of the control signal S2.
D changes. Therefore, the amplification of the high-frequency signal S1 is
It is variably controlled by the voltage value of the control signal S2.

On the other hand, when the output signal Vout is set to zero in the high frequency power amplifier circuit 1, the first D-type FET 2 is turned off by the control signal S2, and the second D-type FET is turned off.
The drain current ID supplied to 3 is set to zero.

For example, when the first D-type FET 2 is to be turned off during a period from time t2 to t3, the first D-type FET 2 is turned off.
A control signal S2 having a negative voltage value at which the voltage VGS becomes deeper than the pinch-off voltage Vp is applied to the gate electrode G of the type FET2.
Is supplied.

Hereinafter, the same circuit operation is repeated.

[0014]

However, in the high-frequency power amplifier circuit 1, positive and negative voltage values are required as the control signal S2 input to the gate electrode G of the first D-type FET 2. Therefore, when using the high-frequency power amplifier circuit 1, a circuit for generating positive and negative voltages is separately required, and the circuit configuration of the communication circuit using the high-frequency power amplifier circuit 1 is complicated. Therefore, there are various problems such as a problem that the number of parts increases and the production cost increases, a problem that the communication device cannot be downsized due to a large communication circuit, and an increase in inspection items at the time of production. Was.

Therefore, an object of the present invention is to provide a high-frequency power amplifier circuit for solving the above problem.

[0016]

A high frequency power amplifier circuit according to the present invention is configured as follows to achieve the above object. That is, it has an enhancement type field effect transistor and a depletion type field effect transistor,
A drain electrode of the depletion type field effect transistor is cascade-connected to a source electrode of the enhancement type field effect transistor, and a high frequency signal is inputted to a gate electrode of the depletion type field effect transistor, thereby obtaining the enhancement type. A positive control signal is input to the gate electrode of the field effect transistor, and an amplified high-frequency signal is extracted from the drain electrode as an output signal.

The enhancement-type field-effect transistors connected in cascade are turned on and off by a control signal input to the gate electrode, and control the amplifying action of the depletion-type field-effect transistors. The pinch-off voltage of the enhancement field effect transistor has a positive voltage value. Therefore, the control signal may be a positive potential,
The amplification operation of the amplifier circuit can be controlled by applying a positive voltage to the gate electrode. When the enhancement type field effect transistor is turned off, the control signal input to the gate electrode may be a voltage lower than the pinch off voltage, that is, a positive cutoff voltage or zero voltage. Furthermore, by changing the voltage value of the control signal,
The amplification degree of the amplifier circuit is variably controlled. Thus, a negative voltage is not required as a control signal for the high-frequency power amplifier circuit,
Only a positive voltage is required.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A high-frequency power amplifier circuit 4 according to the present invention comprises a cascade-connected enhancement type field effect transistor (hereinafter referred to as "E-type FET") 5 and a D-type FET 6.

First, an E-type FET will be schematically described with reference to FIG. E-type FET pinch-off voltage VP
Is a positive voltage value. When the voltage VGS of the E-type FET exceeds the pinch-off voltage VP, the drain current ID starts to flow gradually, and when the voltage VGS is further increased, the drain current ID increases.
D saturates. Therefore, the E-type FET can change the current value of the drain current ID at the voltage VGS in the positive potential range.

Next, the circuit configuration and operation of the high-frequency power amplifier circuit 4 will be described with reference to FIG. In addition,
The difference from the high frequency power amplifier circuit 1 in FIG. 3 is that the first D-type FET 2 is replaced with an E-type FET 5.
Therefore, only this point will be described.

The control signal S3 is input to the gate electrode G of the E-type FET 5 via the gate terminal T4. Control signal S
Reference numeral 3 denotes a square wave or a pulse wave, which controls an amplifying operation of the amplifier circuit. One frequency channel assigned to a communication device by a square wave or a pulse wave is used by being alternately divided into a transmission frame and a reception frame.

An output signal Vout obtained by amplifying the high-frequency signal S1 is taken out from an output terminal T5 connected to the drain electrode D of the E-type FET 5.

In the operation of the high-frequency power amplifier circuit 4, the conduction state of the E-type FET 5 is determined by the voltage value of the control signal S3. Accordingly, a predetermined drain current ID determined by the characteristic curve of the E-type FET 5 is supplied to the D-type FET 6.

For example, when the E-type FET 5 is to be turned on during a period from time t1 to t2, the E-type FET 5
A positive signal voltage is applied to the fifth gate electrode G. The drain current ID supplied to the D-type FET 6 changes according to the voltage value of the control signal S3. Therefore, the amplification of the high frequency signal S1 is variably controlled by the voltage value of the control signal S3. For example, the voltage value (peak value) of the control signal S3 is set according to the reception sensitivity or the transmission sensitivity of the communication device.

In order to stop the high-frequency power amplifier circuit 4 during the amplification operation, the voltage value of the control signal S3 is reduced and the E-type FET 5
To cut off. That is, the drain current ID supplied to the D-type FET 6 is set to zero.

For example, during the period from time t2 to time t3, a control signal S3 of a positive voltage value or a zero volt voltage is supplied to the gate electrode G of the E-type FET 5 so that the voltage VGS becomes smaller than the pinch-off voltage Vp. Is done. Here, the E-type FET 5 is cut off, and the amplification operation of the amplifier circuit 4 is stopped.

Hereinafter, the same circuit operation is repeated.

[0028]

The high frequency power amplifier circuit of the present invention comprises a cascode-connected E-type FET and D-type FET. Therefore, when the E-type FET is turned off, the E-type F
A negative voltage value is not required as a control signal input to the gate electrode G of the ET, and only a positive voltage value or a zero volt voltage is required. Therefore, in a communication circuit using the high-frequency power amplifier circuit of the present invention, a circuit for generating positive and negative signal voltages is not required, so that the circuit configuration is extremely simplified. As a result, there are effects such as reduction of production cost and downsizing of communication equipment.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a high-frequency power amplifier circuit according to the present invention, an input signal input to the high-frequency power amplifier circuit, and an output signal extracted from the high-frequency power amplifier circuit.

FIG. 2A is a characteristic diagram showing a relationship between ID and VGS in a depletion type field effect transistor, and FIG. 2B is a characteristic diagram showing a relationship between ID and VGS in an enhancement type field effect transistor. is there.

FIG. 3 is a diagram illustrating a conventional high-frequency power amplifier, an input signal input to the high-frequency power amplifier, and an output signal extracted from the high-frequency power amplifier.

[Explanation of symbols]

4 High frequency power amplifier circuit 5 Enhancement type field effect transistor (E
Type FET) 6 Depletion type field effect transistor (D
Type FET) S1 High frequency signal S3 Control signal Vout Output signal

 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference) 5J067 AA01 AA13 AA24 AA26 AA41 AA66 CA81 CA92 FA01 FA10 HA14 HA15 HA16 KA12 KA47 KA48 KA53 MA17 MA21 MA22 SA14 TA01 TA06 5J092 AA01 AA13 AA24 AA26 CAA14 CA14 KA12 KA47 KA48 KA53 MA17 MA21 MA23 SA14 TA01 TA06 VL08

Claims (1)

[Claims] 1. An electronic device comprising: an enhancement type field effect transistor and a depletion type field effect transistor;
The drain electrode of the depletion type field effect transistor is cascade-connected to the source electrode of the enhancement type field effect transistor, and a high frequency signal is input to the gate electrode of the depletion type field effect transistor, and the enhancement type A high-frequency power amplifier circuit characterized in that a positive control signal is input to a gate electrode of a field effect transistor and a high-frequency signal amplified from a drain electrode is extracted as an output signal.