JP2000101036A - Row decoder of nonvolatile memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To weaken influence of the back bias effect to reduce the voltage in a row address decoder of a nonvolatile memory comprising NAND strings. SOLUTION: In this main row decoder in NMOS configuration of a NAND- type flash memory, transistors T2 to T4 constituting a charge-pump type level conversion circuit are formed in triple wells. The p-well and the n-well are connected with the source of the transistor T4 and the drain of the transistor T5 in short circuit. In operation of the main row decoder, the p-well and the n-well are charged via the transistor T4 with increase in voltage of the node BSEL and the potential differences between tfie sources of the transistors T2, T3, and the p-well are maintained generally the same. Consequently, back bias is alleviated and voltage not lower than Vpp+Vth (E) (threshold voltage) is output irrespective of the power supply potential so that constant voltage is achieved. At the end of operation of the main row decoder, the transistor T5 is activated to ground the p-well and the n-well for initialization.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a row decoder of a nonvolatile memory used for a flash memory having a NAND type configuration.

[0002]

2. Description of the Related Art There is known a flash memory including a NAND string in which a plurality of memory cell transistors are connected in series. In such a NAND flash memory, it is necessary to apply a voltage of about 20 V to a word line at the time of writing. Therefore, a power supply voltage of 20 V is applied to the main row decoder of such a flash memory.
A level conversion circuit for converting the level into a voltage of the order is provided.

As such a level conversion circuit, FIG.
As shown in (1), it is conceivable to use a CMOS flip-flop.

That is, in FIG. 6, a high power supply voltage Vpp
Between the PMOS transistor PT51 and the NMO
S transistor NT51 is connected in series. A PMOS transistor P is connected between the internal high power supply voltage Vpp and the ground.
T52 and NMOS transistor NT52 are connected in series. The gate of the PMOS transistor PT51 is
OS transistor PT52 and NMOS transistor NT
52 is connected to the connection point. PMOS transistor P
The gate of T52 is connected to the PMOS transistor PT51 and N
Connected to the connection point with MOS transistor NT51.
The gate of the NMOS transistor NT51 is connected to the input terminal of the voltage Vin. The gate of the NMOS transistor NT52 is connected to the input terminal of the voltage Vin via the inverter INV51. PMOS transistor PT52
A terminal of the output voltage Vout is derived from a connection point between the output voltage Vout and the NMOS transistor NT52.

In a level conversion circuit having a flip-flop configuration as shown in FIG. 6, an input voltage of a power supply voltage Vcc is supplied as an input voltage Vin. This input voltage Vin is N
The signal is supplied to the gate of the MOS transistor NT51, is inverted by the inverter INV51, and is supplied to the gate of the NMOS transistor NT52.

When the input voltage Vin of the power supply voltage Vcc is applied to the gate of the NMOS transistor NT51, NM
The OS transistor NT51 is turned on, and the NMOS transistor
The transistor NT52 is turned off. When the NMOS transistor NT51 is turned on, the node ND1 goes low. When the node ND1 goes low, the PMOS transistor PT52 turns on.
When the PMOS transistor PT52 is in the ON state,
Since the transistor NT52 is off, the PMOS
The transistor PT51 is turned off. As a result, the output node ND2 is pulled up to the high voltage Vpp. That is, the input voltage Vin at the Vcc level is converted to a high voltage of about 20 V and output as Vout.

On the other hand, when 0 V is input to the input voltage Vin, the NMOS transistor NT51 turns off and the NMOS transistor NT52 turns on. Thereby, output node ND2 is pulled to the ground level. That is, the output voltage Vout is output while the input voltage Vin of 0 V remains at the ground level.

By the way, in the above-mentioned level conversion circuit, C
It must be a MOS configuration. Since an output voltage of about 20 V is required, it is necessary to provide a high withstand voltage configuration. If a CMOS circuit having such a high withstand voltage configuration is realized, the number of process steps and the number of masks increase,
Increases costs. In addition, it is necessary to charge the N-well of the main row decoder to Vpp each time a write operation is performed, and thus there is a problem that the current consumption of the booster circuit increases and the write time increases due to the N-well charging.

For this reason, in a conventional main row decoder of a flash memory having a NAND type configuration, a charge pump type level conversion circuit which can be realized by an NMOS configuration is used.

FIG. 7 shows an example of a main row decoder of a conventional NAND type flash memory. In FIG. 7, a NAND gate G101 selects a desired block from a plurality of blocks arranged on a memory cell array. That is, NAN
The predecode signals X1, X2, and X3 of the row address are supplied to the D gate G101. A desired block on the memory cell array is selected by the predecode signals X1, X2, X3 of the row address. An output terminal of the NAND gate G101 is connected to an input terminal of the inverter INV101.

The transistors T101 to T103 and the capacitor C101 constitute a charge pump type level conversion circuit. The voltage applied to the word line is set by this level conversion circuit. At the time of writing, a voltage of about 20 V is formed.

The NMOS transistor T101 is a depletion-type transistor, and its source has a high breakdown voltage structure. NMOS transistor T10
One gate is connected to the supply line of the control signal SEP.

The NMOS transistor T102 is an intrinsic transistor, and its threshold voltage Vth (I) is generally about 0V. The NMOS transistor T103 is an enhancement type transistor, and its threshold voltage Vth (E) is usually set to 0.
6V. NMOS transistors T102, T103
Have a high withstand voltage structure.

The drain of the NMOS transistor T101 is connected to the output terminal of the inverter INV101.
The source of the NMOS transistor T101 is connected to an NMOS transistor TG101i forming a transfer gate.
And the NMOS transistor T
103 is connected to the gate.

The drain of the NMOS transistor T103 is connected to a supply line for the internal high voltage Vpp. The source of the transistor T103 is connected to the gate and the drain of the NMOS transistor T102. Transistor T1
02 is connected to the drain of the capacitor C
101 is connected to one end. The source of the transistor T102 is connected to the source of the transistor T101. The other end of the capacitor C101 is connected to the output terminal of the NAND gate G102. The clock CLK is supplied to one input terminal of the NAND gate G102. NAND
The other input terminal of the gate G102 is connected to the inverter INV
101 is connected to the output terminal.

The operation of the above-described conventional main row address decoder will be described. During standby, all of the predecode signals X1, X2, X3 are set to low level (ground level). The output of the NAND gate G101 becomes high level, and the output of the inverter INV101 becomes low level.
The node ASEL at the connection point with the transistor T101 is at a low level. Since node ASEL is low level,
The source of the NMOS transistor T101, the source of the NMOS transistor T102, and the NMOS transistor T
The node BSEL at the connection point with the gate of 103 is at a low level, and the NMOS transistor T103 is off.

Here, when writing is started, the predecode signals X1, X2, X3 of the selected block are activated.
Are all set to the high level, and the node ASEL becomes the power supply voltage Vcc. Further, the control signal SEP becomes low level.

When the control signal SEP becomes low level, the voltage of the node BSEL becomes the threshold voltage | V of the depletion type NMOS transistor T101.
th (D) |.

At this time, the threshold voltage of the transistor T103 is set to Vth (E), and the voltage of the node BSEL is set to Vth (E).
In the case of BSEL, the transistor T103 is turned on because VBSEL> Vth (E).

When the clock signal CLK performs a clock operation, a pumping operation is performed, and the voltage of the node BSEL gradually increases.

When the output of the NAND gate G102 is at the low level, the voltage Vcap of the node cap at one end of the capacitor C101 is changed from the node BSEL to the transistor T10.
3, the threshold voltage Vth (E) becomes lower, so that Vcap = VBSEL-Vth (E) (1), and electric charge is stored in the capacitor C101.

When the output of the NAND gate G102 becomes high level, the voltage Vcap of the node cap is raised by the voltage Vcc, and the voltage Vcap 'of the new node cap is changed.
Is as follows: Vcap ′ = Vcap + Vcc (2)

Since the NMOS transistor T102 is diode-connected, the charge at the node cap moves to the node BSEL, and raises the voltage at the node BSEL.
At this time, when the threshold voltage of the transistor T102 is Vth (I), the voltage VBSEL ′ of the node BSEL is as follows: VBSEL ′ = Vcap′−Vth (I) = Vcap + Vcc−Vth (I) (3)

As described above, the positive feedback is applied by the clock CLK to increase the voltage of the node BSEL, and the voltage of the node BSEL gradually increases. Thereby, a voltage of about 20 V can be formed at the time of writing.

The voltage of control signal VCGI for the selected word line is equal to internally generated voltage Vpp. This control signal VCGi is supplied to the drain of the NMOS transistor TG101i constituting the transfer gate. The gate of the NMOS transistor TG101i has
The voltage of node BSEL is applied. Since the voltage of the node BSEL is higher than the voltage Vpp of the control signal VCGi by the threshold voltage Vth (E) or more, the NMOS transistor TG1
01i turns on. Thereby, the word line WLi is
The voltage of VCGi is output as it is.

[0026]

As described above, in the conventional main row decoder of a NAND flash memory, the voltage is boosted by a charge pump type level conversion circuit to output a word line voltage at the time of writing. ing. By using a charge pump type level conversion circuit in this manner, an NMOS structure can be obtained. However, such a configuration has a problem that it is difficult to lower the power supply voltage because of the influence of the back bias effect.

That is, in the above-described level conversion circuit of the main row decoder, the voltage VBSEL ′ of the new node BSEL needs to be higher than the voltage VBSEL of the previous node BSEL in order to obtain a boosted gain. There is. That is, it is necessary to satisfy the relationship of VBSEL ′ ≧ VBSEL. As a result, it is necessary to satisfy VBSEL'≥VBSEL Vcap + Vcc-Vth (I) ≥Vcap + Vth (E) Vcc≥Vth (E) + Vth (I) (4)

In a MOS transistor, it is known that when a potential difference occurs between a source voltage and a substrate, electrons hardly flow from the source to the substrate surface, and the threshold voltage increases. Such a phenomenon is called a back bias effect.

In the above-described level conversion circuit of the main row decoder, when the node BSEL rises at the time of writing, the source voltages of the NMOS transistors T103 and T102 rise accordingly. That is, if the internally generated voltage Vpp is raised to a voltage of about 20 V at the time of writing, the source voltages of the NMOS transistors T103 and T102 are also raised to about the same as the internally generated voltage Vpp. Therefore, the NMOS transistor T
The threshold voltage Vth (E) of the transistor 103 and the threshold voltage Vth (I) of the NMOS transistor T102 increase. When the threshold voltage Vth (E) of the NMOS transistor T103 and the threshold voltage Vth (I) of the NMOS transistor T102 increase, the above-mentioned expression (4) cannot be satisfied unless the power supply voltage Vcc is increased.

In the current NAND type flash memory, 3.3 V is used as the power supply voltage Vcc, and thus satisfies the above equation (4). It is considered that there is a demand for lowering the power supply voltage in order to achieve the realization.
When the power supply voltage is set to 2.5 V or 1.8 V, it is very difficult to satisfy the above equation (4).

Although it is conceivable to increase the number of stages of the charge pump, increasing the number of stages of the charge pump causes a problem that the circuit scale increases.

Therefore, an object of the present invention is to provide an NMOS
An object of the present invention is to provide a row address decoder of a nonvolatile memory which can be configured and can be operated at a low voltage without being affected by a back bias effect.

[0033]

According to a first aspect of the present invention, there is provided a NAND string in which a plurality of memory cell transistors are connected in series, and a word line common to the gates of the memory cell transistors corresponding to each other in the plurality of NAND strings. A row address decoder of a nonvolatile memory in which a plurality of blocks are arranged on a memory cell array, and a desired block is selected from a plurality of blocks arranged on the memory cell array. Block selecting means, level converting means for converting the level of the output voltage of the block selecting means, and voltage generating means for generating a voltage to be applied to a desired word line from among a plurality of word lines in the selected block. Is provided between the voltage generating means and the word line, and the output of the level converting means is given to its gate. Level converting means, a capacitive element to which a boosting clock signal is applied, a first field effect transistor connected between an input terminal of the level converting means and its output terminal, A diode-connected second field-effect transistor connected between the element and the output terminal; and a third field-effect transistor connected between the internal high-voltage power supply and the capacitive element and having a gate connected to the output terminal. Wherein the first, second and third field effect transistors are of the first conductivity type and the second and third
At least the second field-effect transistor is located between the second well of the second conductivity type formed in the first well of the first conductivity type on the substrate of the second conductivity type. A row address decoder of a nonvolatile memory formed and having well potential adjusting means for increasing the potential of the second well by following the output voltage.

According to the second aspect of the present invention, the level conversion means includes:
Further, a means for initializing the potential of the second well is included.

When configuring a charge pump type level conversion circuit, an NMOS transistor is provided in a triple well in which an n-well and a p-well are formed on a p-type substrate. Then, when the source voltage rises due to the rise of the output voltage, the potential of the well rises following the rise of the source voltage. This eliminates the occurrence of the back bias effect due to the potential difference between the source and the substrate, and prevents an increase in the threshold voltage. Therefore, the power supply voltage can be reduced.

A transistor for setting the potential of the well in such a triple well to the ground level is provided. By turning on this transistor, the potential of the well can be initialized.

[0037]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows an example of a main row decoder of a NAND flash memory to which the present invention is applied.

In FIG. 1, a NAND gate G1 selects a desired block from a plurality of blocks arranged on a memory cell array.

The memory cell array of the NAND flash memory is configured as shown in FIG. In FIG. 2, transistors MT0A to MT15A, MT0B to M
T15B,... Are memory cell transistors having a floating gate. For example, 16 memory cell transistors MT0A to MT15A, MT0B to MT1
5B,... Are connected in series. Then, the memory cell transistors MT0A to MT15A, MT0B to MT1
5B,... Are connected in series to the drain side of the series connection of the selection gates SG1A, SG1B,.
Further, select gate transistors SG2A, SG2B,... Are respectively connected in series to the source side of this series connection. Thereby, for example, a NAND having 16 memory cells
Strings STA, STB,... Are configured.

The drain side select gate transistor S
The drains of G1A, SG1B,...
L0, BL1,... The sources of the select gate transistors SG2A, SG2B,... On the source side are respectively connected to the source line Vs.

The NAND strings STA, STB,
Are arranged side by side, and the gates of the corresponding select gate transistors and the gates of the memory cell transistors are commonly connected. In the example of FIG. 2, the NAND string ST
The gates of the selection gates SG1A, SG1B,... Of A, STB,... Are connected to a common selection signal supply line DSG.
Memory cell transistors MT0A to MT15A, MT0
The gates of B to MT15B,... Are respectively connected to common word lines WL0, WL12,. The gates of the selection gates SG2A, SG2B,... Are connected to a common selection signal supply line SSG. Thus, a block is formed by connecting the corresponding select gate transistor and memory cell transistor to each other.

As shown in FIG. 3, a plurality of such blocks B0, B1, B2,... Are arranged on a memory cell. The row address predecode signals X1, X2, X3 are supplied to the NAND gate G1 in FIG. The predecode signals X1, X2,
X3 selects a desired block on the memory cell array.

In FIG. 1, transistors T1 to T5,
The capacitor C1 forms a charge pump type level conversion circuit. This level conversion circuit outputs a voltage of about 20 V (16 to 17 V) at the time of writing.

Sub row decoder and SG decoder 10
Sets a selection gate in a NAND string and selects a desired word line. From the sub row decoder and the SG decoder 10, the word lines WL0 to WL0 are output.
A supply line of control signals VCG0 to VCG15 for WL15 and a control signal VSSG for selection signal supply line SSG
And the control signal V for the selection signal supply line DSG.
The supply lines for DSGH and VDSGL are derived.

TG1 to TG19 are NMOS transistors forming a transfer gate. The drains of the NMOS transistors TG1 to TG19 are connected to supply lines of control signals from the sub-row decoder and the SG decoder 10.

The drain of the NMOS transistor TG1 is connected to a control signal VSSG supply line for controlling the selection gate. NMOS transistors TG2 to TG
Drains 17 are connected to supply lines of control signals VCG0 to VCG15 for controlling the memory cell transistors, respectively. The drain of the NMOS transistor TG18 is connected to a supply line of a control signal VDSGH for controlling the selection gate. The drain of the NMOS transistor TG19 has a control signal VD for controlling the selection gate.
It is connected to the SGL supply line.

The source of the NMOS transistor TG1 is
Connected to selection signal supply line SSG. The sources of the NMOS transistors TG2 to TG17 are connected to the word lines WL0 to WL
L15. NMOS transistor TG1
8 and the source of the TG 19 are connected to the selection signal supply line D
Connected to SG.

As described above, the charge pump type level conversion circuit includes the transistors T1 to T5 and the capacitor C1.
It is composed of The NMOS transistor T1 is a depletion-type transistor, and has a source with a high breakdown voltage structure. NMOS transistor T
One gate is connected to the supply line of the control signal SEP.

The NMOS transistor T2 is an intrinsic type transistor and has a threshold voltage Vth
(I) is usually about 0V. NMOS transistor T
3, T4 is an enhancement type transistor,
The threshold voltage Vth (E) is normally 0.6V. The NMOS transistors T2, T3, T4 have a high breakdown voltage structure.

The NMOS transistor T5 is an enhancement type transistor. The transistor T5 has a structure with a high withstand voltage on the drain side.

In the level conversion circuit in the main row address decoder to which the present invention is applied, the NMOS transistors T2, T3 and T4 (transistors surrounded by broken lines) are, as shown in FIG. And p
It is formed in a triple well in which a well is formed.

In FIG. 4, reference numeral 11 denotes a p-type semiconductor substrate;
2 denotes an n-well, 13 denotes a p-well, 14 to 16 denote an n ⁺ diffusion layer, 17 denotes a p ⁺ diffusion layer, and 18 denotes a gate electrode. An n-well 12 is formed in a p-type semiconductor substrate 11, and a p-well 13 is formed in the n-well 12.
On the surface in the p-well 13, n ⁺ diffusion layers 15 and 16 as element-side diffusion layers and ap ⁺ diffusion layer 17 for an extraction electrode are formed. The n ⁺ diffusion layers 15 and 16 and the gate electrode 18 form an NMOS transistor. For example, the n ⁺ diffusion layer 15 functions as a source and n ^+
+ Diffusion layer 16 functions as a drain. Terminal Wp is p
The terminal Wn is derived from the well 13 and the terminal Wn is derived from the n-well 12.

In FIG. 1, the NMOS transistor T1
Is connected to the output terminal of the inverter IV1. The source of the NMOS transistor T1 is connected to the NMOS transistors TG1 to TG constituting the transfer gate.
18, and connected to the gate of the NMOS transistor T3 and the gate of the NMOS transistor T4.

The drain of the NMOS transistor T3 is connected to a supply line for the internally generated voltage Vpp. The source of the NMOS transistor T3 is connected to the gate and the drain of the NMOS transistor T2. NMOS transistor T
2 is connected to one end of the capacitor C1. The source of the NMOS transistor T2 is connected to the source of the NMOS transistor T1. The other end of the capacitor C1 is connected to the output terminal of the NAND gate G2. The drain of the NMOS transistor T4 is connected to the supply line of the internally generated voltage Vpp.

As described above, the transistor T2,
T3 and T4 are provided in a triple well, and the p-well 13 and n-well 12 of these transistors T2, T3 and T4 are connected to the drain of the transistor T5. Note that, as shown in FIG.
From the well 12, a terminal Wp and a terminal Wn are led out. Connecting the p-well 13 and the n-well 12
This means that the terminals Wp and Wn are connected.
The source of the transistor T5 is grounded. The gate of the transistor T5 is connected to the output terminal of the inverter INV2.

The NAND gate G1 is supplied with predecode signals X1, X2, X3. NAND gate G1
Is connected to the input terminal of the inverter INV1. The output terminal of the inverter INV1 is connected to the drain of the NMOS transistor T1 and to one input terminal of the NAND gate G2. The other input terminal of NAND gate G2 is connected to a clock CLK supply line. At the same time, the output terminal of the inverter INV1 is connected to the input terminal of the inverter INV2. The output terminal of the inverter INV2 is an NMOS transistor TG19
And the gate of the transistor T5.

The operation of the above embodiment will be described with reference to FIG. 5B to 5D during standby.
, All of the predecode signals X1, X2, X3 are set to low level (ground level). At this time,
Since the output of the NAND gate circuit G1 becomes high level and the output of the inverter INV1 becomes low level, FIG.
As shown in F, the node ASEL at the connection point between the inverter INV1 and the NMOS transistor T1 is at a low level. Since the node ASEL is at low level, the node BSEL at the connection point between the source of the NMOS transistor T1, the source of the NMOS transistor T2, and the gate of the NMOS transistor T3 is at low level, and the NMOS transistor T3 is off. Since the node BSEL is at a low level, the NMOS transistor T4 is off. At this time, the output of the inverter INV2 becomes high level (power supply voltage Vcc level), the NMOS transistor T5 turns on, and the p-well and n-well of the transistors T2, T3, T4 provided in the triple well (p-well in FIG. 4) Well 13 and n-well 12)
It reaches the ground level.

Here, when the writing is started, the predecode signals X1, X2, X3 of the selected block are set.
Are all set to the high level, and the node ASEL becomes the power supply voltage Vcc. Further, as shown in FIG. 5A, the control signal S
EP goes low.

When the control signal SEP goes low, as shown in FIG. 5G, the voltage at the node BSEL (indicated by E1 in FIG. 6) becomes the threshold voltage | Vth (D) | of the depletion type NMOS transistor T1. Becomes At the same time, when the node XASEL of the output terminal of the inverter INV2 goes low, the NMO
The S transistor T5 turns off.

Then, as shown in FIG. 5G, a pumping operation is performed, and the voltage of node BSEL gradually increases.

That is, the threshold voltage of the transistor T3 is set to Vth (E), and the voltage of the node BSEL is set to VBSEL
Then, since VBSEL> Vth (E), the transistor T3 is turned on.

When the transistor T3 is turned on, the voltage Vcap at the node cap at one end of the capacitor C1 changes to the node B
From SEL, threshold voltage Vth (E) of transistor T3
Vcap = VBSEL-Vth (E), and electric charge is stored in the capacitor C1.

When the clock CLK output from the NAND gate G2 goes high, the voltage V at the node cap
The cap is raised by the voltage Vcc of the clock at the time of the high level, and the voltage Vcap ′ of the new node cap becomes Vcap ′ = Vcap + Vcc.

Since the NMOS transistor T2 is diode-connected, the charge at the node cap is charged at the node BS.
Moving to EL, the voltage of the node BSEL is increased.

Incidentally, in order to operate such a charge pump type level conversion circuit, the sum of the threshold voltage Vth (E) of the NMOS transistor T3 and the threshold voltage Vth (I) of the NMOS transistor T2 is calculated by using the power supply voltage Vcc. It is necessary to:

Vcc ≧ Vth (E) + Vth (I) As the voltage of the node BSEL increases, the source voltages of the NMOS transistors T2 and T3 also increase. At this time, if a potential difference occurs between the substrate and the source voltage,
Since the inflow of electrons from the source to the substrate surface decreases and the threshold voltage increases due to the back bias effect, it becomes difficult to lower the power supply voltage Vcc.

Therefore, in the embodiment of the present invention, as described above, the transistors T2, T3 and T4 are provided in the triple well. Then, as the source voltage increases, the voltage of the p-well is increased to suppress an increase in the threshold voltage due to the back bias effect.

That is, when the pumping operation is started, the output of the inverter INV2 becomes low level,
The MOS transistor T5 turns off. At this time, NMO
The threshold voltage | Vth (D) | of the S transistor T1 is equal to the threshold voltage Vth (E) of the NMOS transistor T4.
By being larger, the NMOS transistor T4 turns on. When the NMOS transistor T4 turns on, the transistors T2 and T2 provided in the triple well
3. The p-well 13 and n-well 12 of T4 are charged to | Vth (D) | -Vth (E).

When the voltage of the node BSEL increases by the pumping operation, the gate voltage of the NMOS transistor T4 increases, and as shown by E3 in FIG.
The voltage Vpwel of the p-well of the NMOS transistors T2, T3, T4 also increases.

As described above, when the source voltage of the NMOS transistors T2 and T3 rises due to the rise of the voltage of the node BSEL, the NMOS transistor T2
2, the voltage Vpwel of the p-well 13 at T3 and T4 also increases. As a result, the back bias effect is considerably reduced, and the threshold voltage Vth of the NMOS transistor T3 is reduced.
(E) and the change in the threshold voltage Vth (I) of the NMOS transistor T2 are considerably suppressed.

Assuming that the potential difference between the source and the p-well 13 does not change, the threshold voltage Vth (E) of the NMOS transistor T3 is set to (Vth (E) = 0.6V), and the threshold voltage Vth (I) of the NMOS transistor T2 is set. To (Vth
(I) = 0.0V), Vth (E) + Vth (I) = 0.
The power supply voltage is 6 V, and the power supply voltage Vcc can be reduced to about (Vcc = 1 V) even if a margin is expected.

When the write operation is completed, verify is performed. Sub-row decoder and SG during verification
The upper limit of the voltage supplied from the decoder 10 to the word line is N
Memory cell transistor MT0A constituting an AND cell
ＭＴMT15A, MT0B〜MT15B,... Are about 5 V applied to the gates when they are pass transistors, but the NMOS transistors TG1 to Since it is sufficient that the TG 19 is turned on, there is no problem even if the node BSEL is at the word line voltage (about 20 V) at the time of writing. Therefore, once the writing is started, the internally generated voltage Vpp is kept at the selected word line voltage at the time of writing until the write / verify operation is completed and it is determined that the writing is sufficient.
It is not necessary to discharge the p-well 13 and n-well 12 of the MOS transistors T2, T3, T4.

In the verify reading, when it is determined that the cells in the page are sufficiently written, the internally generated voltage Vpp is set to the same potential as the power supply voltage Vcc, and the predecode signals X1, X2, and X3 of the row address are all low. Set to level. When all the predecode signals X1, X2, X3 are set to low level, the output of the inverter INV2 becomes high level, the NMOS transistor T5 turns on,
The charges in the p-well 13 and the n-well 12 of the transistors T2, T3, T4 are discharged, and the node Vpwel becomes the ground level.

As described above, in the embodiment of the present invention, the NM constituting the charge pump type level conversion circuit is described.
The OS transistors T2, T3, T4 are provided in a triple well. By increasing the voltage of the well together with the source voltage, the influence of the back bias effect is reduced. This makes it possible to reduce the power supply voltage to about 1 V with the configuration of the NMOS transistor decoder.

It should be noted that in the above example, 20 V
Although the description has been given of the case where a voltage of about the same level is applied to the word line, the same applies to the case where another voltage is applied.

In the above example, the NMOS transistors T2, T3 and T4 are provided in the triple well,
Although the S transistors T2 and T3 are both designed to reduce the influence of the back bias effect, the NMOS transistors T2 and T4 are provided in a triple well,
Even if the effect of the back bias effect is reduced only in the transistor T2, the effect is sufficiently effective.

[0077]

According to the first aspect of the present invention, when forming a charge pump type level conversion circuit, an n-type substrate is formed on a p-type substrate.
In a triple well in which a well and a p-well are formed, N constituting a charge pump type level conversion circuit is formed.
A MOS transistor is provided. When the source voltage rises due to the rise of the output voltage, the potential of the well rises accordingly. This alleviates the back bias effect due to the potential difference between the source and the substrate, and prevents an increase in the threshold voltage. Therefore, the power supply voltage can be reduced.

According to the second aspect of the present invention, the transistor for setting the potential of the well to the ground level is provided. By turning on this transistor, the potential of the well can be initialized.

[Brief description of the drawings]

FIG. 1 is a connection diagram of an example of a main row decoder to which the present invention is applied.

FIG. 2 is a connection diagram used for describing a NAND type string and a block.

FIG. 3 is a schematic diagram used to describe a block in a memory cell;

FIG. 4 is a cross-sectional view used for describing a triple well.

FIG. 5 is a waveform chart used for describing an example of a main row decoder to which the present invention is applied.

FIG. 6 is a connection diagram of an example of a conventional level conversion circuit.

FIG. 7 is a connection diagram of another example of a conventional level conversion circuit.

[Explanation of symbols]

T1, 2, T3, T4, T5... NMOS transistors, C1... Capacitors, WL0 to WL15.

[Procedure amendment]

[Submission date] December 3, 1998 (1998.12.
3)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0015

[Correction method] Change

[Correction contents]

The drain of the NMOS transistor T103
Are connected to the supply line of the high voltage Vpp. Transistor T1
03 is connected to the gate and the drain of the NMOS transistor T102. Transistor T102
The connection point between the gate and the drain of the capacitor is a capacitor C10.
1 is connected to one end. The source of the transistor T102 is connected to the source of the transistor T101. The other end of the capacitor C101 is connected to the output terminal of the NAND gate G102. The clock CLK is supplied to one input terminal of the NAND gate G102. The other input terminal of the NAND gate G102 is connected to the inverter INV10
1 output terminal.

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0016

[Correction method] Change

[Correction contents]

[0016] a description will be given of the operation of the conventional Meinro Ude coder described above. During standby, all of the predecode signals X1, X2, X3 are set to low level (ground level). As a result, the output of the NAND gate G101 becomes high level and the output of the inverter INV101 becomes low level.
Node ASEL at a connection point with OS transistor T101
Goes low. Since the node ASEL is low level, the source of the NMOS transistor T101 and the NMOS
The node BSEL at the connection point between the source of the transistor T102 and the gate of the NMOS transistor T103 is at a low level, and the NMOS transistor T103 is off.

[Procedure amendment 3]

[Document name to be amended] Statement

[Correction target item name] 0024

[Correction method] Change

[Correction contents]

As described above, the positive feedback is applied by the clock CLK to increase the voltage of the node BSEL, and the voltage of the node BSEL gradually increases. Thereby, at the time of writing, a voltage of about 20 V can be output .

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0033

[Correction method] Change

[Correction contents]

[0033]

According to a first aspect of the present invention, there is provided a NAND string in which a plurality of memory cell transistors are connected in series, and a word line common to the gates of the memory cell transistors corresponding to each other in the plurality of NAND strings. the connecting constitute a block, a non-volatile b Ude coder of memory so as to arranging a plurality of blocks on the memory cell array, select the desired block from among a plurality of blocks arranged in the memory cell array Block selecting means, level converting means for converting the level of the output voltage of the block selecting means, and voltage generating means for generating a voltage to be applied to a desired word line from among a plurality of word lines in the selected block. , Provided between the voltage generating means and the word line, and the output of the level converting means is provided to its gate. Transfer means, wherein the level converting means comprises a capacitive element to which a boosting clock signal is applied, a first field effect transistor connected between an input terminal of the level converting means and an output terminal thereof, and a capacitive element. A second field effect transistor connected between the internal high voltage power supply and the capacitor, and a third field effect transistor having a gate connected to the output terminal. The first, second, and third field-effect transistors are of the first conductivity type, and at least the second field-effect transistor of the second and third field-effect transistors is formed on a substrate of the second conductivity type. Potential adjustment formed on the second well of the second conductivity type formed in the first well of the first conductivity type and increasing the potential of the second well by following the output voltage. hand A nonvolatile b Ude coder of memory to have a.

[Procedure amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0041

[Correction method] Change

[Correction contents]

The NAND strings STA, STB,
Are arranged side by side, and the gates of the corresponding select gate transistors and the gates of the memory cell transistors are commonly connected. In the example of FIG. 2, the NAND string ST
The gates of the selection gates SG1A, SG1B,... Of A, STB,... Are connected to a common selection signal supply line DSG.
Memory cell transistors MT0A to MT15A, MT0
B~MT15B, ... gate of, respectively, a common word line WL0, WL12, is connected to the ... WL15. The gates of the selection gates SG2A, SG2B,... Are connected to a common selection signal supply line SSG. Thus, a block is formed by connecting the corresponding select gate transistor and memory cell transistor to each other.

[Procedure amendment 6]

[Document name to be amended] Statement

[Correction target item name] 0043

[Correction method] Change

[Correction contents]

In FIG. 1, transistors T1 to T5,
The capacitor C1 forms a charge pump type level conversion circuit. This level converting circuit, at the time of writing, a voltage of 20V extent is outputted.

[Procedure amendment 7]

[Document name to be amended] Statement

[Correction target item name] 0051

[Correction method] Change

[Correction contents]

[0051] In the level conversion circuit in this invention Meinro Ude coder is applied is, NMOS transistor T
2, T3 and T4 (transistors shown by dashed lines)
As shown in FIG. 4, it is formed in a triple well in which an n-well and a p-well are formed on a p-type substrate.

[Procedure amendment 8]

[Document name to be amended] Statement

[Correction target item name] 0064

[Correction method] Change

[Correction contents]

Since the NMOS transistor T2 is diode-connected, the charge at the node cap is charged at the node BS.
Moving to EL, the voltage of the node BSEL is increased. this
The voltage VBSEL 'of the node BSEL at the time
Assuming that the threshold voltage of T2 is Vth (I), VBSEL '= Vcap'-Vth (I) = Vcap + VccV-Vth (I) .

[Procedure amendment 9]

[Document name to be amended] Statement

[Correction target item name] 0065

[Correction method] Change

[Correction contents]

Incidentally, in order to operate such a charge pump type level conversion circuit, a charge pump
The gain of the circuit must satisfy Gain = VBSEL′−VBSEL ≧ 0. From this condition , the sum of the threshold voltage Vth (E) of the NMOS transistor T3 and the threshold voltage Vth (I) of the NMOS transistor T2 is determined by the power supply voltage. and Vcc less, it is necessary to Vcc ≧ Vth (E) + Vth (I).

[Procedure amendment 10]

[Document name to be amended] Statement

[Correction target item name] 0066

[Correction method] Change

[Correction contents]

[0066] When the voltage of the node BSEL rises,
The source voltages of the NMOS transistors T2 and T3 also increase. At this time, if a potential difference occurs between the substrate and the source voltage, the inflow of electrons from the source to the substrate surface decreases, and the threshold voltage increases due to the back bias effect, making it difficult to lower the power supply voltage Vcc. Come.

Claims (2)

[Claims] A plurality of memory cell transistors comprising a NAND string in which a plurality of memory cell transistors are connected in series;
A row decoder of a nonvolatile memory in which a common word line is connected to gates of memory cell transistors corresponding to each other in an ND string to form a block, and a plurality of the blocks are arranged on a memory cell array. Block selecting means for selecting a desired block from a plurality of blocks arranged on the memory cell array; level converting means for converting a level of an output voltage of the block selecting means; Voltage generating means for generating a voltage to be applied to a desired word line from a word line; transfer means provided between the voltage generating means and the word line, wherein an output of the level converting means is supplied to a gate thereof The level conversion means comprises: a capacitive element to which a boosting clock signal is applied; A first field-effect transistor connected between an input terminal of the level conversion means and an output terminal thereof, a diode-connected second field-effect transistor connected between the capacitive element and the output terminal, A third field-effect transistor connected between a power supply and the capacitive element, the gate of which is connected to the output terminal; and the first, second, and third field-effect transistors are a first field-effect transistor.
At least a second field-effect transistor of the second and third field-effect transistors is formed in a first well of a first conductivity type on a substrate of a second conductivity type. Second
A row decoder of a non-volatile memory having a well potential adjusting means formed for a conductive second well and for increasing the potential of the second well by following an output voltage. 2. The apparatus according to claim 1, wherein said level conversion means further comprises:
2. The row decoder according to claim 1, further comprising means for initializing the potential of the well.