JP2000100940A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor device that is equipped with wiring film layers, contact holes that connect wiring film layers together, and other contact holes connected to a semiconductor substrate and capable of restraining the semiconductor substrate located at the base of the contact holes from being overetched when the contact holes are formed at the same time. SOLUTION: A semiconductor device is equipped with a first wiring film 17 formed on a semiconductor board 15, a first interlayer insulating film 18 provided covering the first wiring film 17, a second wiring film 19 formed on the first interlayer insulating film 18, a second interlayer insulating film 20 provided covering the second wiring film 19, a first contact hole 22 that reaches down to the first wiring film 17 penetrating through the second interlayer insulating film 20, the second wiring film 19, and the first interlayer insulating film 18, and a second contact hole 23 that reaches down to the semiconductor substrate 15 penetrating through the second interlayer insulating film 20 and the first interlayer insulating film 18, where the top surface of the first interlayer insulating film 18 is made even by flattening the level difference caused by the first wiring film 17.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention comprises a plurality of wiring films in the middle of an interlayer insulating film, a contact hole for connecting each wiring film, and a contact hole for connecting to a semiconductor substrate. In this case, the present invention relates to a semiconductor device and a method of manufacturing a semiconductor device that can reduce overetching of a semiconductor substrate located at the bottom of one contact hole when each contact hole is formed simultaneously.

[0002]

2. Description of the Related Art FIG. 15 is a sectional view showing a structure of a conventional semiconductor device, and FIGS. 16 to 18 are sectional views showing a method of manufacturing the semiconductor device shown in FIG. In FIG. 15, 1
Is a semiconductor substrate, and 2 is an element isolation layer for isolating elements on the semiconductor substrate 1 and is formed by being buried in a groove 1a formed in the semiconductor substrate 1, and is made of, for example, a silicon oxide film. Reference numeral 3 denotes a first wiring film formed on the element isolation layer 2 and formed of, for example, a polysilicon film, and reference numeral 4 denotes a first wiring film formed so as to cover the first wiring film 3 and formed of, for example, TEOS. The upper surface is formed in a stepped shape by the first wiring film 3.

[0005] 5 is formed on the first interlayer insulating film 4.
For example, a second wiring film 6 made of a polysilicon film is formed so as to cover the second wiring film 5, for example, TEO.
S is a second interlayer insulating film made of S, 7 is a third wiring film made of, for example, a polysilicon film formed on the second interlayer insulating film 6, 8 is the first wiring film 3, A first contact hole 9 formed for connecting the second wiring film 5 and the third wiring film 7 is a second contact hole formed for connecting to the semiconductor substrate 1.

Next, a description will be given of a method of manufacturing the conventional semiconductor device configured as described above. First, a silicon oxide film 10 is formed on a semiconductor substrate 1 by using, for example, a thermal oxidation technique.
Is formed on the silicon oxide film 10, for example, under reduced pressure CV.
The silicon nitride film 11 is formed using the D method. next,
A resist is applied on the silicon nitride film 11 and patterned for element isolation by photolithography to form a resist mask 12 (FIG. 16A).

Next, using the resist mask 12 as a mask, the silicon nitride film 11 and the silicon oxide film 10 are etched and patterned to remove the resist mask 12 (FIG. 16B). Next, using the silicon nitride film 11 and the silicon oxide film 10 as a mask, the semiconductor substrate 1
Is etched to form a groove 1a (FIG. 16C).
Next, a silicon oxide film 2a is formed so as to be buried in the groove 1a, and is etched by a chemical mechanical polishing method.
Inside, silicon nitride film 11 and silicon oxide film 10
(FIG. 16 (d)).

Next, the silicon oxide film 2a is
The silicon oxide film 2 is projected from the upper surface by a desired thickness.
Etchback of a is performed to form the element isolation layer 2 (FIG. 17A). Next, the silicon nitride film 11 and the silicon oxide film 10 are removed by wet processing. Next, a polysilicon film 3a is formed on the semiconductor substrate 1 to a thickness of, for example, about 1000 angstroms. This polysilicon film 3
A resist is applied on the substrate a and patterned by photolithography to form a resist mask 13 (FIG. 17).
(B)).

Next, the polysilicon film 3a is patterned using the resist mask 13 as a mask, the first wiring film 3 is formed on the element isolation layer 2, and the resist mask 13 is removed (FIG. 17C). Next, a first interlayer insulating film 4 is formed to cover the first wiring film 3 with a thickness of, for example, 5000 angstroms. (FIG. 17D). At this time, the upper surface of the first interlayer insulating film 4 has a stepped shape due to the first wiring film 3. Next, on the first interlayer insulating film 4, for example, 50
A polysilicon film is formed with a thickness of 0 Å and is patterned using a resist mask to form a second wiring film 5.

Next, so as to cover the second wiring film 5,
A second interlayer insulating film 6 is formed (FIG. 18A). Next, a third wiring film 7 is formed on the second interlayer insulating film 6 (FIG. 18B). Next, a resist is applied on the third wiring film 7, and a resist mask 14 is formed by photolithography (FIG. 18C). Next, the resist mask 14
Is used as a mask for etching.

The etching conditions at this time are, for example, using an ECR type dry etching apparatus, and using CHF ₃ /
When the etching is performed with O ₂ gas at a pressure of 2 mTorr, there is a condition that an etching rate ratio between each of the interlayer insulating films 4 and 5 and the second wiring film 5 is 1: 0.1.

As another etching condition at this time, for example, a parallel plate type dry etching apparatus is used, and a gas of CHF ₃ / CF ₄ / Ar / O ₂ is used for 250 m
When performed at a pressure of Torr, there is a condition that the etching rate ratio between each of the interlayer insulating films 4 and 5 and the second wiring film 5 is 1: 0.2.

Then, under any of the etching conditions,
Third wiring film 7, second interlayer insulating film 6, second wiring film 5
Then, the first interlayer insulating film 4 is etched to
A first contact hole 8 reaching the wiring film 3 of FIG.
The wiring film 7, the first interlayer insulating film 4 and the second interlayer insulating film 6 are etched to simultaneously form the second contact holes 9 reaching the semiconductor substrate 1, respectively.

At this time, it is necessary to etch the second wiring film 5 in order to form the first contact hole 8, and this etching takes a very long time as compared with the interlayer insulating films 4 and 6. It takes. Therefore, it is faster for the second contact hole 9 to reach on the semiconductor substrate 1 than for the first contact hole 8 to reach on the first wiring film 3. The bottom semiconductor substrate 1 is shaved. Next, the resist mask 14
Is removed (FIG. 15).

[0013]

According to the conventional semiconductor device, it takes a very long time to etch the second wiring film 5 in the formation of the first contact hole 8. There is a problem that the semiconductor substrate 1 at the bottom of the contact hole 9 is shaved and the reliability of the semiconductor device is reduced.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a highly reliable semiconductor device and a method of manufacturing a semiconductor device without cutting a semiconductor substrate more than necessary. Aim.

[0015]

Means for Solving the Problems Claim 1 according to the present invention.
Is formed on a semiconductor substrate having a first wiring film formed thereon, a first interlayer insulating film formed so as to cover the first wiring film, and a first interlayer insulating film formed on the first interlayer insulating film. A second wiring film, a second wiring film, and a second interlayer insulating film formed so as to cover the second wiring film, the second interlayer insulating film, the second wiring film, and the first wiring film. A first contact hole penetrating through the interlayer insulating film and reaching the first wiring film; a second contact hole reaching the semiconductor substrate through the second interlayer insulating film and the first interlayer insulating film; And the first
The upper surface of the interlayer insulating film is formed by flattening a step formed by the first wiring film.

According to a second aspect of the present invention, in the semiconductor device of the first aspect, the first wiring film has a thickness of the first wiring film.
And the time required for etching the second contact hole is set to be equal.

According to a third aspect of the present invention, in the semiconductor device according to the first or second aspect, the first wiring film is formed on an element isolation layer buried in the semiconductor substrate. The thickness of the separation layer protruding from the upper surface of the semiconductor substrate is set so that each time required for etching the first and second contact holes becomes equal.

According to a fourth aspect of the present invention, in the semiconductor device according to any one of the first to third aspects, the first interlayer insulating film includes a lower insulating film and an upper insulating film. The upper surface of the insulating film is formed in a step shape by the first wiring film, the upper surface of the upper insulating film is formed by flattening the step by the first wiring film, and the etching rate of the upper insulating film is reduced by the lower insulating film. It is slower than the etching rate.

According to a fifth aspect of the present invention, in the semiconductor device according to the fourth aspect, the upper insulating film is formed of a nitride film, and the lower insulating film is formed of an oxide film.

According to a sixth aspect of the present invention, there is provided a semiconductor device comprising: a first semiconductor substrate having a first wiring film formed thereon;
A first interlayer insulating film formed so as to cover the wiring film;
A second wiring film formed on the first interlayer insulating film;
A second interlayer insulating film formed so as to cover the first wiring film, the second interlayer insulating film, the second wiring film, and the first interlayer insulating film. A first contact hole reaching the wiring film; a second interlayer insulating film; and a second contact hole penetrating the first interlayer insulating film and reaching the semiconductor substrate. Are larger than the diameter of the second contact hole.

According to a seventh aspect of the present invention, in the semiconductor device according to the sixth aspect, the diameter of the opening penetrated by the first contact hole of the second wiring film decreases toward the bottom. The diameter of the lower end of the opening of the second wiring film formed in a tapered shape is equivalent to the diameter of the second contact hole.

According to a eighth aspect of the present invention, in a method of manufacturing a semiconductor device, a first wiring film is formed on a semiconductor substrate, and a first interlayer insulating film is formed so as to cover the first wiring film. Forming, flattening a step due to the first wiring film on the upper surface of the first interlayer insulating film, forming a second wiring film on the first interlayer insulating film, and forming a second wiring film so as to cover the second wiring film. A first contact hole penetrating through the second interlayer insulating film, the second wiring film, and the first interlayer insulating film to reach the first wiring film; A second contact hole penetrating the interlayer insulating film and the first interlayer insulating film and reaching the semiconductor substrate is simultaneously formed.

According to a ninth aspect of the present invention, in a method of manufacturing a semiconductor device, a first wiring film is formed on a semiconductor substrate, and a first interlayer insulating film is formed so as to cover the first wiring film. Forming, forming a second wiring film on the first interlayer insulating film, forming a second interlayer insulating film so as to cover the second wiring film, forming a second interlayer insulating film, a second wiring A first contact hole penetrating through the film and the first interlayer insulating film and reaching the first wiring film; and a first contact hole reaching the semiconductor substrate through the second interlayer insulating film and the first interlayer insulating film. Forming a first contact hole, wherein the diameter of the upper portion of the first contact hole is set to be larger than the diameter of the upper portion of the second contact hole. At the time of penetration of the second wiring film at the time, By changing the etching condition to increase the amount, the opening penetrated by the first contact hole of the second wiring film is formed in a tapered shape in which the diameter becomes smaller toward the lower portion, and the second wiring film is formed. Is adjusted so that the diameter of the lower end is equal to the diameter of the second contact hole.

According to a tenth aspect of the present invention, in the method for manufacturing a semiconductor device according to the ninth aspect, the condition for etching the second wiring film is defined as follows: a gas system of CHF ₃ / CF ₄ / Ar / O ₂ And etching by reducing the proportion of O ₂ to increase the amount of deposition on the second wiring film,
A desired tapered shape is obtained.

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 Hereinafter, embodiments of the present invention will be described. FIG. 1 is a sectional view showing a configuration of a semiconductor device according to a first embodiment of the present invention, and FIGS. 2 to 5 are sectional views showing a method for manufacturing the semiconductor device shown in FIG. In FIG. 1, reference numeral 15 denotes a semiconductor substrate, and 16 denotes an element isolation layer for isolating an element on the semiconductor substrate 15, for example, a silicon oxide film buried in a groove 15 a formed in the semiconductor substrate 15. Consists of

Reference numeral 17 denotes a first wiring film formed of, for example, a polysilicon film formed on the element isolation layer 16;
Is a first interlayer insulating film made of, for example, TEOS, which is formed so as to cover the first wiring film 17. The upper surface of the first interlayer insulating film is formed by flattening a step formed by the first wiring film 17.
Reference numeral 19 denotes a second wiring film formed on the first interlayer insulating film 18 and made of, for example, a polysilicon film. Reference numeral 20 denotes a second wiring film formed so as to cover the second wiring film 19, for example, BPTEO.
This is a second interlayer insulating film made of S.

Reference numeral 21 denotes a third wiring film made of, for example, a polysilicon film formed on the second interlayer insulating film 20;
22 denotes a first wiring film 17, a second wiring film 19, and a third
In order to connect the first wiring film 21, the third wiring film 21, the second interlayer insulating film 20, the second wiring film 19, and the first
A first contact hole 23 formed through the first interlayer insulating film 18 is connected to the semiconductor substrate 15 to form a third wiring film 21, a second interlayer insulating film 20, and a first interlayer insulating film. 18 is a second contact hole formed penetrating through the second contact hole 18.

Next, a method of manufacturing the semiconductor device of the first embodiment configured as described above will be described. First, a silicon oxide film 24 is formed on the semiconductor substrate 15 using, for example, a thermal oxidation technique, and a silicon nitride film 25 is formed on the silicon oxide film 24 by using, for example, a low pressure CVD method. Next, a resist is coated on the silicon nitride film 25, and patterning for element isolation is performed by photolithography to form a resist mask 26 (FIG. 2).
(A)).

Next, using the resist mask 26 as a mask, the silicon nitride film 25 and the silicon oxide film 24 are etched and patterned, and the resist mask 26 is removed (FIG. 2B). Next, using the silicon nitride film 25 and the silicon oxide film 24 as a mask, the semiconductor substrate 15
Is etched to form a groove 15a (FIG. 2C).
Next, a silicon oxide film 16a is formed so as to fill the groove 15a, and is etched by a chemical mechanical polishing method to form the inside of the groove 15a and the region patterned by the silicon nitride film 25 and the silicon oxide film 24. (FIG. 2 (d)).

Next, the silicon oxide film 16a is etched back so that the silicon oxide film 16a protrudes from the upper surface of the semiconductor substrate 1 by a desired thickness to form the element isolation layer 16 (FIG. 3A). . Next, the silicon nitride film 25 and the silicon oxide film 24 are removed by wet processing. Next, a polysilicon film 17a is formed on the semiconductor substrate 15 to a thickness of, for example, 1000 angstroms. Next, a resist is applied on the polysilicon film 17a and is patterned by photolithography to form a resist mask 27 (FIG. 3B).

Next, using the resist mask 27 as a mask, the polysilicon film 17a is patterned to
6, a first wiring film 17 is formed, and a resist mask 27 is formed.
Is removed (FIG. 3 (c)). Next, a TEOS 18a is formed so as to cover the first wiring film 17 (FIG. 4A).
At this time, the first wiring film 17 is formed on the upper surface of the TEOS 18a.
There is a step due to

Next, a step on the upper surface of the silicon oxide film 18a due to the first wiring film 17 is flattened by etching by a chemical mechanical polishing method to form a first interlayer insulating film 18. (FIG. 4B). FIG.
As is clear from FIG. 2B, the film thickness t ₁ of the first interlayer insulating film 18 at the portion where the first wiring film 17 is not formed on the semiconductor substrate 15 at this time is First
The first wiring film 17 is formed thicker by the thickness t _{3 of} the first wiring film 17 than the film thickness t ₂ of the first interlayer insulating film 18 where the wiring film 17 is formed.

Next, a polysilicon film, for example, is formed on the first interlayer insulating film 18 and is patterned using a resist mask to form a second wiring film 19. Next, a second interlayer insulating film 20 made of, for example, BPTEOS is formed so as to cover the second wiring film 19 (FIG. 4C).
Since the thickness of the second wiring film 19 is small, the upper surface of the second interlayer insulating film 20 hardly has a step.

Next, a third wiring film 21 made of, for example, a polysilicon film is formed on the second interlayer insulating film 20 (FIG. 5A). Next, a resist is applied on the third wiring film 21 and patterned by photolithography to form a resist mask 28 (FIG. 5B). Next, etching is performed using the resist mask 28 as a mask.

As the etching conditions at this time, for example, an ECR type dry etching apparatus is used, and CHF ₃ /
When the etching is performed with O ₂ gas at a pressure of 2 mTorr, there is a condition that the etching rate ratio between each of the interlayer insulating films 18 and 20 and the second wiring film 19 is 1: 0.1.

As another etching condition, for example, a parallel plate type dry etching device is used, and CHF is used.
_{When the} etching is performed with a gas of ₃ / CF ₄ / Ar / O ₂ at a pressure of 250 mTorr, the etching rate ratio between each of the interlayer insulating films 18 and 20 and the second wiring film 19 becomes 1: 0.2. is there.

Then, under any of the etching conditions,
The third wiring film 21, the second interlayer insulating film 20, the second wiring film 19, and the first interlayer insulating film 18 are etched to form a first contact hole 22 reaching the first wiring film 17. Then, the third wiring film 21, the second interlayer insulating film 20, and the first interlayer insulating film 18 are etched, and the second contact holes 23 reaching the semiconductor substrate 15 are simultaneously formed.

At this time, since the formation of the first contact holes 22 requires etching of the second wiring film 19, this etching requires a very long time. The amount of etching of the first interlayer insulating film 18 in the formation of the second contact hole 23 is the same as that of the first contact hole 2.
Since it is necessary to etch the first interlayer insulating film 18 more by the thickness of t ₃ than the etching amount of the first interlayer insulating film 18 in the formation of 2,
It takes a lot of time.

Accordingly, the time difference between the etching time for reaching the semiconductor substrate 15 in forming the second contact hole 23 and the etching time for reaching the first wiring film 17 in forming the first contact hole 22 is different. ,
The second contact hole 2 is smaller than the conventional case.
The scraping of the semiconductor substrate 15 at the bottom of 3 can be suppressed. Next, the resist mask 28 is removed (FIG. 1).

In the semiconductor device according to the first embodiment configured as described above, the upper surface of the first interlayer insulating film 18 is formed by flattening a step formed by the first wiring film 17.
Since the film thickness of the first interlayer insulating film 18 can be larger at the portion where the first wiring film 17 does not exist than at the portion where the first wiring film 17 exists, the first contact hole Since the etching time difference caused by the etching of the second wiring film 19 in the simultaneous formation of the second contact hole 23 and the second contact hole 23 can be made smaller than in the conventional case, the shaving of the semiconductor substrate 15 can be reduced. Thus, a semiconductor device having excellent reliability can be obtained.

In the first embodiment, the example in which the second interlayer insulating film 20 is formed by BPTEOS has been described. However, this may be formed by TEOS. , BPTEOS having an etching rate higher than that of TEOS is used. In addition, an example using PTEOS having an etching rate higher than the etching rate of TEOS can be considered. In addition, since the first interlayer insulating film 18 is in contact with the semiconductor substrate 15 here, BPTEOS and PTEOS containing many impurities are not used.

Embodiment 2 FIG. 6 is a cross-sectional view showing a configuration of a semiconductor device according to a second embodiment of the present invention, and FIG. 7 is a cross-sectional view showing a method for manufacturing the semiconductor device shown in FIG. In FIG. 6, the same parts as those in the first embodiment are denoted by the same reference numerals, and description thereof will be omitted. Reference numeral 29 denotes a first wiring film formed on the element isolation layer 16 and made of, for example, a polysilicon film. The first wiring film 29 has first and second film thicknesses to be described later.
Each time required for etching the contact hole is set to be equal.

Reference numeral 30 denotes a first interlayer insulating film made of, for example, TEOS, which is formed so as to cover the first wiring film 29. The upper surface is formed by flattening a step formed by the first wiring film 29. ing. Reference numeral 31 denotes a third wiring for connecting the first wiring film 29, the second wiring film 19, and the third wiring film 21.
Wiring film 21, second interlayer insulating film 20, second wiring film 1
9 and a first contact hole 32 formed through the first interlayer insulating film 30 to form a third wiring film 21 and a second interlayer insulating film 2 for connecting to the semiconductor substrate 15.
0 and a second contact hole formed through the first interlayer insulating film 30.

Next, a method of manufacturing the semiconductor device according to the second embodiment configured as described above will be described. First, the element isolation layer 16 is formed on the semiconductor substrate 1 through the same steps as in the first embodiment. Next, a polysilicon film is formed on the semiconductor substrate 15 to a thickness of, for example, 2000 angstroms, and is patterned to form a first wiring film 29 (FIG. 7A).

The thickness of the first wiring film 29 set at this time is, as is apparent from comparison with the case of the first embodiment, a thickness larger than a generally required thickness. Is formed. This is achieved by forming first and second
This is because the etching times of the contact holes 31 and 32 are set to be equal.

Next, TE is so formed as to cover the first wiring film 29.
The OS 30a is formed. (FIG. 7 (b)). At this time, TE
A step due to the first wiring film 29 exists on the upper surface of the OS 30a. Next, a step on the upper surface of the TEOS 30a due to the first wiring film 29 is etched and flattened by a chemical mechanical polishing method to form a first interlayer insulating film 30 (FIG. 7C).

As is clear from FIG. 7C, the thickness t ₄ of the first interlayer insulating film 30 at the portion where the first wiring film 29 is not formed on the semiconductor substrate 15 at this time is From the thickness t ₅ of the first interlayer insulating film 30 at the position where the first wiring film 29 is formed on the semiconductor substrate 15, the first wiring film 2 is formed.
9 is formed thicker by the thickness t ₆ .

Next, as in the first embodiment, a second wiring film 19, a second interlayer insulating film 20, and a third wiring film 21 are formed. Next, a resist mask is formed on the third wiring film 21, and the third wiring film 21, the second interlayer insulating film 20, the second wiring film 19, and the first interlayer insulating film 30 are etched. Then, the first contact hole 31 reaching over the first wiring film 29 and the third wiring film 21,
The second interlayer insulating film 20 and the first interlayer insulating film 30 are etched to simultaneously form the second contact holes 32 reaching the semiconductor substrate 15 (FIG. 6).

At this time, as in the first embodiment, the first
Of the second wiring film 19
This etching requires a very long time. By setting the thickness of the first wiring film 29 to t ₆ so as to be equal in consideration of the etching time, the etching amount of the first interlayer insulating film 30 in the formation of the second contact hole 32 is set. Is set to be greater than the etching amount of the first interlayer insulating film 30 in the formation of the first contact hole 31 by the thickness of t ₆ .

Therefore, the time difference between the etching time for reaching the semiconductor substrate 15 in forming the second contact hole 32 and the etching time for reaching the first wiring film 29 in forming the first contact hole 31 is as follows. Almost eliminated, and the abrasion of the semiconductor substrate 15 at the bottom of the second contact hole 32 can be further suppressed.

In the semiconductor device of the second embodiment configured as described above, the thickness of the first wiring film 29 is made equal to each time required for etching the first and second contact holes 31 and 32. The first contact hole 31 and the second contact hole 32 are formed on the upper surface of the first interlayer insulating film 30 because the step formed by the first wiring film 29 is flattened. , The etching time difference caused by the etching of the second wiring film 19 can be almost eliminated.
5 can be further reduced, and a more reliable semiconductor device can be obtained.

Embodiment 3 FIG. FIG. 8 is a cross-sectional view showing a configuration of a semiconductor device according to a third embodiment of the present invention, and FIG. 9 is a cross-sectional view showing a method for manufacturing the semiconductor device shown in FIG. In FIG. 8, the same parts as those in the above embodiments are denoted by the same reference numerals, and description thereof will be omitted. Reference numeral 33 denotes an element isolation layer for isolating an element on the semiconductor substrate 15, which is formed by being embedded in a groove 15 a formed in the semiconductor substrate 15 and made of, for example, a silicon oxide film. Film thickness t
_{Numeral 10} is set so that the times required for etching the first and second contact holes described later are equal.

Reference numeral 34 denotes a first wiring film formed on the element isolation layer 33, for example, a polysilicon film. Reference numeral 35 denotes a first wiring film formed to cover the first wiring film 34, for example, TEO.
In the first interlayer insulating film made of S, a step formed by the first wiring film formed on the element isolation layer 33 is flattened.

Reference numeral 36 denotes the first wiring film 34 and the second wiring film 1
9 and the third wiring film 21, the third wiring film 21, the second interlayer insulating film 20, the second wiring film 19,
A first contact hole 37 formed through the first interlayer insulating film 35 is connected to the semiconductor substrate 15 so that the third wiring film 21, the second interlayer insulating film 20 and the first A second contact hole formed through the interlayer insulating film 35 of FIG.

Next, a description will be given of a method of manufacturing the semiconductor device of the third embodiment configured as described above. First, the silicon oxide film is left only in the groove 15a of the semiconductor substrate 15 and in the region patterned by the silicon nitride film 25 and the silicon oxide film 24 through the same steps as the above embodiments. . Next, the first and second contact holes 3 to be formed by a desired thickness from the upper surface of the semiconductor substrate 15, here,
As each time is equal according to the etching of 6,37 is etched back so as to leave only projecting the film thickness of the t ₁₀ (FIG. 9 (a)).

Next, the silicon nitride film 25 and the silicon oxide film 24 are removed by a wet process (FIG. 9).
(B)). Next, a first wiring film 34 is formed on the semiconductor substrate 15 by forming a polysilicon film with a thickness of, for example, 1000 angstroms and patterning the same. Next, a TEOS 35a is formed so as to cover the first wiring film 34.
(FIG. 9 (c)). At this time, on the upper surface of the TEOS 35a,
There is a step due to the first wiring film 34 formed on the element isolation layer 33.

Next, the step on the upper surface of the TEOS 35a due to the first wiring film 34 formed on the element isolation layer 33 is etched by a chemical mechanical polishing method to be flattened to form a first interlayer insulating film. Formed as a film 35 (FIG. 9)
(D)). As is clear from FIG. 9D, the film thickness t ₇ of the first interlayer insulating film 35 at the portion where the first wiring film 34 is not formed on the semiconductor substrate 15 at this time is From the film thickness t ₈ of the first interlayer insulating film 35 at the position where the first wiring film 34 is formed on the element isolation layer 33 of FIG.
The first is thicker by projecting thickness min t ₁₀ protruding from the semiconductor substrate 15 upper surface of thickness t ₉ and the isolation layer 33 of the wiring layer 34.

Next, a second wiring film 19, a second interlayer insulating film 20, and a third wiring film 21 are formed as in the above embodiments. Next, a resist mask is formed on the third wiring film 21, and the third wiring film 21, the second interlayer insulating film 20, the second wiring film 19, and the first interlayer insulating film 35 are etched. Then, the first contact hole 36 reaching the first wiring film 34 and the third wiring film 21,
The second interlayer insulating film 20 and the first interlayer insulating film 35 are etched to simultaneously form the second contact holes 37 reaching the semiconductor substrate 15 (FIG. 8).

At this time, as in the above embodiments, the first
The second wiring film 19 is formed in the formation of the contact hole 36 of FIG.
This etching requires a very long time. Then, considering the etching time, the semiconductor substrate 1 of the element isolation layer 33 is made equal.
By setting the protruding thickness t ₁₀ from the upper surface of 5, the etching amount of the first interlayer insulating film 35 in the formation of the second contact hole 37, the first contact hole 3
6 is set to be larger than the etching amount of the first interlayer insulating film 35 by the thickness of t ₉ and t ₁₀ .

Therefore, the time difference between the etching time for reaching the semiconductor substrate 15 in forming the second contact hole 37 and the etching time for reaching the first wiring film 34 in forming the first contact hole 36 is as follows. Almost eliminated, and the abrasion of the semiconductor substrate 15 at the bottom of the second contact hole 37 can be further suppressed.

In the semiconductor device of the third embodiment configured as described above, the thickness t ₁₀ of the element isolation layer 33 protruding from the upper surface of the semiconductor substrate 15 is determined by changing the thickness t ₁₀ of the first and second contact holes 36 and 37. Since the respective times required for the etching are set to be equal, the upper surface of the first interlayer insulating film 35 is flattened by the step caused by the first wiring film 34 formed on the element isolation layer 33. Since the etching time difference caused by the etching of the second wiring film 19 in the formation of the first contact hole 36 and the second contact hole 37 can be substantially eliminated, the shaving of the semiconductor substrate 15 is further reduced. Thus, a semiconductor device with higher reliability can be obtained.

Incidentally, the first wiring film 34 of the third embodiment is described.
Although the film thickness of the first embodiment is the same as that of the first embodiment, it is not limited to this, and it goes without saying that the thickness of the second embodiment may be set in combination.

Embodiment 4 FIG. 10 is a sectional view showing a configuration of a semiconductor device according to a fourth embodiment of the present invention, and FIG.
FIG. 11 is a cross-sectional view showing the method for manufacturing the semiconductor device shown in FIG.
In FIG. 10, the same parts as those in each of the above embodiments are denoted by the same reference numerals, and description thereof will be omitted. 38 denotes the first wiring film 17
Is a first interlayer insulating film formed so as to cover the lower insulating film 39 and the upper insulating film 40.

The upper surface of the lower insulating film 39 is formed in a step shape by the first wiring film 17, and the upper insulating film 40
Is formed such that the steps due to the first wiring film 17 are flattened. The etching rate of the upper insulating film 40 is lower than the etching rate of the lower insulating film 39. For example, a nitride film is formed as the upper insulating film 40, and an oxide film is formed as the lower insulating film 39. I think. In this case, the etching rate ratio of the oxide film to the nitride film is about 2.0 to 3.0 to 1.0.

Reference numeral 41 denotes the first wiring film 17 and the second wiring film 1
9 and the third wiring film 21, the third wiring film 21, the second interlayer insulating film 20, the second wiring film 19,
The first contact hole 42 formed through the first interlayer insulating film 38 is connected to the semiconductor substrate 15 so that the third wiring film 21, the second interlayer insulating film 20 and the first Is a second contact hole formed through the interlayer insulating film 38 of FIG.

Next, a method of manufacturing the semiconductor device of the fourth embodiment configured as described above will be described. First, the first wiring film 17 is formed on the semiconductor substrate 15 through the same steps as in the above embodiments. Next, the first wiring film 1
A silicon oxide film 39a and a silicon nitride film 40a are sequentially formed so as to cover 7 (FIG. 11A). On this occasion,
Each of the upper surfaces of the silicon oxide film 39a and the silicon nitride film 40a has a step due to the first wiring film 17.

Next, the step on the upper surface of the silicon nitride film 40a due to the first wiring film 17 is etched and flattened by a chemical mechanical polishing method, and is formed of a lower insulating film 39 and an upper insulating film 40. It is formed as one interlayer insulating film 38 (FIG. 11B). As is clear from FIG. 11B, the semiconductor substrate 1 in this case is similar to the first embodiment.
The thickness t ₁ of the first interlayer insulating film 38 on the portion of the semiconductor substrate 15 where the first wiring film 17 is formed on the portion of the semiconductor substrate 15 where the first wiring film 17 is not formed is than the thickness t ₂ of the interlayer insulating film 38 is formed thicker by the thickness t ₃ minutes of the first wiring layer 17.

Since the lower insulating film 39 has not been subjected to a flattening step, the film thickness is t
Same as ₁₁ . The thickness of the upper insulating film 40 is the first
A portion where the wiring film 17 is not present in the lower thickness and t _12, also places the first wiring layer 17 is present it can be seen that made by a thin film thickness and t _13. Therefore, the difference in the thickness of the upper insulating film 40 corresponds to the thickness t ₃ of the first wiring film 17.

Next, as in the above embodiments, a second wiring film 19, a second interlayer insulating film 20, and a third wiring film 21 are formed. Next, a resist mask is formed on the third wiring film 21, and the third wiring film 21, the second interlayer insulating film 20, the second wiring film 19, and the first interlayer insulating film 38 are etched. Then, the first contact hole 41 reaching the first wiring film 17, the third wiring film 21,
The second interlayer insulating film 20 and the first interlayer insulating film 38 are etched to simultaneously form the second contact holes 42 reaching the semiconductor substrate 15 (FIG. 1).
0).

At this time, as in the above embodiments, the first
The second wiring film 19 is formed in the formation of the contact hole 41 of FIG.
This etching requires a very long time. Then, the second contact hole 4
The etching amount of the first interlayer insulating film 38 2, the first setting the thickness of the t ₃ greater than the amount of etching of the interlayer insulating film 38 of the first contact hole 41, the difference between the thickness t ₃ is the The upper insulating film 40 has an etching rate lower than that of the lower insulating film 39 in the one interlayer insulating film 38.

Therefore, the time difference between the etching time to reach the semiconductor substrate 15 in the formation of the second contact hole 42 and the etching time to reach the first wiring film 17 in the formation of the first contact hole 41 is As a result, the size of the semiconductor substrate 15 at the bottom of the second contact hole 42 can be suppressed.

In the semiconductor device of the fourth embodiment configured as described above, the first interlayer insulating film 38 is formed of the lower insulating film 39 and the upper insulating film 40, and the etching rate of the lower insulating film 39 is increased. Since the upper surface of the upper insulating film 40 having a lower etching rate is flattened by the step formed by the first wiring film 17, the second contact hole 41 and the second contact hole 42 are formed. Since the difference in etching time caused by the etching of the wiring film 19 is compensated for by the thickness of the upper insulating film 40 having a low etching rate, it can be further reduced. Therefore, the abrasion of the semiconductor substrate 15 can be reduced, and a highly reliable semiconductor device can be obtained.

In the fourth embodiment, the same example as in the first embodiment has been described with respect to the thickness of the first wiring film 17 and the protrusion thickness of the element isolation layer 16, but the present invention is not limited to this. Needless to say, it is needless to say that combining the examples of the above-described second and third embodiments further enhances the effect.

Embodiment 5 FIG. 12 is a sectional view showing a configuration of a semiconductor device according to a fifth embodiment of the present invention, and FIG.
Size) and the etching rate of TEOS (TEOS
FIG. 7 is a diagram illustrating a relationship with the “Etch Rate”. In FIG. 12, the same parts as those in the above-described embodiments are denoted by the same reference numerals, and description thereof will be omitted. Reference numeral 43 denotes a first interlayer insulating film formed so as to cover the first wiring film 17, and the upper surface thereof is the first interlayer insulating film.
The wiring film 17 is formed in a stepped shape.

Reference numeral 44 denotes the first wiring film 17 and the second wiring film 1
9 and the third wiring film 21, the third wiring film 21, the second interlayer insulating film 20, the second wiring film 19,
The first contact hole 45 formed through the first interlayer insulating film 43 is connected to the semiconductor substrate 15 so that the third wiring film 21, the second interlayer insulating film 20, and the first The diameter D ₂ of the second contact hole 45 is smaller than the diameter D _{1 of} the first contact hole 4 in the second contact hole formed through the interlayer insulating film 43.

Next, a method of manufacturing the semiconductor device of the fifth embodiment configured as described above will be described. First, the first wiring film 17 is formed on the semiconductor substrate 15 through the same steps as in the above embodiments. Next, the first wiring film 1
7, a first interlayer insulating film 43 made of, for example, TEOS is formed. At this time, a step due to the first wiring film 17 exists on the upper surface of the first interlayer insulating film 43.

Next, as in the above embodiments, a second wiring film 19, a second interlayer insulating film 20, and a third wiring film 21 are formed. Next, a resist mask is formed on the third wiring film 21, and the third wiring film 21, the second interlayer insulating film 20, the second wiring film 19, and the first interlayer insulating film 43 are etched. Then, the first contact hole 44 reaching the first wiring film 17 and the third wiring film 21,
The second interlayer insulating film 20 and the first interlayer insulating film 43 are etched to simultaneously form second contact holes 45 reaching the semiconductor substrate 15 (FIG. 1).
2).

At this time, since the diameter D ₁ of the _first contact hole 44 is formed to be larger than the diameter D ₂ of the second contact hole 45, the etching rate in forming the first contact hole 44 is the second contact hole 45. Contact hole 4
5 is faster than the etching rate in the formation of No. 5. This is clear from the relationship in FIG. Therefore, the second wiring film 19 in the formation of the first contact hole 44
Each of the contact holes 44,
The difference in etching time between the first and second contact holes 45 can be eliminated by making the etching speed of the first contact hole 44 faster than the etching speed of the second contact hole 45.

[0079] Further, as the etching time in the formation of the contact holes 44 and 45 is equal, the diameter D ₁ of the first contact hole 44 and the diameter D ₂ of the second contact holes 45, 13 It can be set from the relationship as shown. As an example, D ₁ is about 0.30 μm.
m and D ₂ may be set to about 0.25 μm.

The time difference between the etching time for reaching the semiconductor substrate 15 in forming the second contact hole 45 and the etching time for reaching the first wiring film 34 in forming the first contact hole 44 is as follows. Almost eliminated, and the shaving of the semiconductor substrate 15 at the bottom of the second contact hole 45 can be further reduced.

In the semiconductor device of the fifth embodiment configured as described above, the diameter D ₁ of the first contact hole 44 is
Since the diameter of the second contact hole 45 is made larger than the diameter D ₂ and the times required for etching the first and second contact holes 44 and 45 are made equal, the scraping of the semiconductor substrate 15 is further reduced. Accordingly, a semiconductor device having higher reliability can be obtained.

Although the fifth embodiment has described the example in which the upper surface of the first interlayer insulating film 43 is formed in a shape having a step due to the first wiring film 17, the present invention is not limited to this. As described in Embodiment Modes 1 to 4, if the combination of flattening the upper surface of the first interlayer insulating film is used, the scraping of the semiconductor substrate can be more easily solved. It goes without saying that you can do it.

Embodiment 6 FIG. FIG. 14 is a sectional view showing a configuration of a semiconductor device according to a sixth embodiment of the present invention. FIG.
In the following description, the same parts as those in the above-described embodiments are denoted by the same reference numerals, and description thereof is omitted. 46 is the first wiring film 17, the second
In order to connect the third wiring film 19 and the third wiring film 21, the third wiring film 21, the second interlayer insulating film 20, the second wiring film 19, and the first interlayer insulating film 43 are penetrated. The first contact hole 47 is formed through the third wiring film 21, the second interlayer insulating film 20, and the first interlayer insulating film 43 to connect to the semiconductor substrate 15. A second contact hole.

The diameter D4 of the upper end of the second contact hole 47 is smaller than the diameter D3 of the upper end of the first contact hole 46. Then, the opening 1 of the second wiring film 19 penetrated by the first contact hole 46 is formed.
9a is formed in a tapered shape whose diameter becomes smaller toward the lower part, and the diameter D4 of the lower end of the opening 19a of the second wiring film 19 is equal to the diameter D4 of the second contact hole 47. Is formed.

Next, a method of manufacturing the semiconductor device of the sixth embodiment configured as described above will be described. First, the first wiring film 17 is formed on the semiconductor substrate 15 through the same steps as in the above embodiments. Next, the first wiring film 1
7, a first interlayer insulating film 43 made of, for example, TEOS is formed. At this time, a step due to the first wiring film 17 exists on the upper surface of the first interlayer insulating film 43.

Next, a second wiring film 19, a second interlayer insulating film 20, and a third wiring film 21 are formed as in the above embodiments. Next, a resist mask is formed on the third wiring film 21, and the third wiring film 21, the second interlayer insulating film 20, the second wiring film 19, and the first interlayer insulating film 43 are etched. Then, the first contact hole 46 reaching the first wiring film 17 and the third wiring film 21,
The second interlayer insulating film 20 and the first interlayer insulating film 43 are etched to simultaneously form the second contact holes 47 reaching the semiconductor substrate 15 (FIG. 1).
4).

Then, when the first contact hole 46 is formed, the etching of the second wiring film 19 is performed so that the diameter of the second wiring film 19 becomes smaller as the opening 19a reaches the lower portion. The etching condition is changed so that the amount of deposition with respect to 19 becomes large. As an actual example of etching, the conditions for etching the second wiring film 19 are as follows: a gas system of CHF ₃ / CF ₄ / Ar / O ₂ is used, and etching is performed by reducing the ratio of O ₂ . The amount of deposition on the second wiring film 19 increases, and a desired tapered shape can be obtained.

At this time, in the formation of the second contact hole 47, the second interlayer insulating film 20 etched at the same time has almost no change in the deposition amount even if the gas is changed as described above. , Second wiring film 1
9 is not formed in the same tapered shape.

At this time, the first contact hole 4
Diameter D ₃ of the upper end of 6 is larger formed than the diameter D ₄ of the upper end of the second contact hole 47, the etch rate in the formation of the first contact hole 46, the etching rate in the formation of the second contact hole 47 Since it is faster, the time required for the first contact hole 46 to penetrate the second wiring film 19 to be etched and the time required for the second contact hole 47 to penetrate the second interlayer insulating film 20 are reduced. Are equivalent.

[0090] Then, the first diameter D ₄ of the lower end of the opening 19a which is penetrated by the contact hole 46 of the second wiring layer 19, so that the diameter D ₄ of the second contact hole 47 is equal to Has been adjusted. Therefore, the remaining portions of the etching of the contact holes 46 and 47 at this stage are to etch the same amount of the first interlayer insulating film 43 with the same diameter.
The etching times of the first and second contact holes 46 and 47 become equal, and the etching time of the first contact hole 46 until reaching the first wiring film 17 and the etching time until the second contact hole 47 reaches the semiconductor substrate 15. Is equivalent to

In the semiconductor device of the sixth embodiment configured as described above, the diameter D of the upper end of the first contact hole 46 is
₃ is made larger than the diameter D ₄ of the upper end of the second contact hole 47, and the second wiring film 1 of the first contact hole 46 is made larger.
9 and the time until the second contact hole 47 penetrates the second interlayer insulating film 20 is equalized, and the first contact hole 4
Diameter in the formation of 6 as extending the opening 19a of the second wiring layer 19 to the lower end is reduced, and the diameter D ₄ so as to be equal to the diameter D ₄ of the second contact hole 47.

Therefore, in the etching of the remaining first interlayer insulating film 43 of each of the contact holes 46 and 47,
It is possible to perform the etching at equal weight and equal diameter D _4, since each etching time of the contact holes 46 and 47 is equal, it is possible to prevent abrasion of the control well semiconductor substrate 15, reliability Thus, a more excellent semiconductor device can be obtained.

[0093]

As described above, according to the first aspect of the present invention, there is provided a semiconductor substrate having a first wiring film formed thereon.
A first interlayer insulating film formed so as to cover the first wiring film, a second wiring film formed on the first interlayer insulating film,
In a semiconductor device having a second interlayer insulating film formed so as to cover a second wiring film, a second interlayer insulating film, a second wiring film, and a first interlayer insulating film may be penetrated. A first contact hole reaching the first wiring film; a second contact hole penetrating the second interlayer insulating film and the first interlayer insulating film to reach the semiconductor substrate; Since the upper surface of the film is formed by flattening a step formed by the first wiring film, if the first and second contact holes are to be formed at the same time, the first interlayer insulating film for etching the first contact hole is used. Since the thickness of the film is larger than the thickness of the first interlayer insulating film used for etching the second contact hole, each contact hole is formed during the etching time of the second wiring film in forming the first contact hole. of It is possible to reduce the differences among the second
It is possible to provide a semiconductor device capable of reducing abrasion of the semiconductor substrate at the bottom of the contact hole.

According to a second aspect of the present invention, in the first aspect, the thickness of the first wiring film is equal to the first and second wiring films.
Since the respective times required for etching the contact holes are set to be equal, the thickness of the first interlayer insulating film required for etching the second contact holes increases, and the time required for etching the respective contact holes increases. Since the times are made equal, it is possible to provide a semiconductor device capable of further reducing the abrasion of the semiconductor substrate at the bottom of the second contact hole.

According to a third aspect of the present invention, in the first or second aspect, the first wiring film is formed on the element isolation layer embedded in the semiconductor substrate. The thickness of the protrusion from the top surface of the semiconductor substrate is
And the time required for etching the second contact hole is set to be equal, so that the film thickness of the first interlayer insulating film required for etching the second contact hole becomes large, Since the etching time is made equal, it is possible to provide a semiconductor device that can further reduce the shaving of the semiconductor substrate at the bottom of the second contact hole.

According to a fourth aspect of the present invention, in any one of the first to third aspects, the first interlayer insulating film includes a lower insulating film and an upper insulating film. Is formed in a step shape by the first wiring film,
The upper surface of the upper insulating film is formed by flattening a step formed by the first wiring film, and the etching speed of the upper insulating film is lower than the etching speed of the lower insulating film. In the interlayer insulating film, the thickness of the upper insulating film having a low etching rate is increased, and the time difference required for etching each contact hole is reduced. Therefore, the scraping of the semiconductor substrate at the bottom of the second contact hole is further reduced. It is possible to provide a semiconductor device that can perform the above.

According to a fifth aspect of the present invention, in the fourth aspect, the upper insulating film is formed of a nitride film and the lower insulating film is formed of an oxide film. It is possible to provide a semiconductor device in which the etching rate of an insulating film can be reliably reduced.

According to claim 6 of the present invention, the first interlayer insulating film formed so as to cover the first wiring film of the semiconductor substrate having the first wiring film formed thereon, In a semiconductor device having a second wiring film formed on one interlayer insulating film and a second interlayer insulating film formed so as to cover the second wiring film, a second interlayer insulating film, A first contact hole penetrating through the second wiring film and the first interlayer insulating film and reaching the first wiring film; and a semiconductor substrate penetrating through the second interlayer insulating film and the first interlayer insulating film. And a second contact hole extending upward. Since the diameter of the first contact hole is larger than the diameter of the second contact hole, when the first and second contact holes are to be simultaneously formed, each contact hole is formed. To reduce the time difference for etching Can, it is possible to provide a semiconductor device capable of reducing the abrasion of the semiconductor substrate at the bottom of the second contact hole.

According to a seventh aspect of the present invention, in the sixth aspect, the opening portion penetrated by the first contact hole of the second wiring film is tapered such that the diameter decreases toward the lower portion. The diameter of the lower end of the opening of the second wiring film formed by the method described above is equal to the diameter of the second contact hole, so that the etching of each contact hole can be easily controlled. Becomes possible.

According to an eighth aspect of the present invention, a first wiring film is formed on a semiconductor substrate, and a first interlayer insulating film is formed so as to cover the first wiring film. A level difference caused by the first wiring film on the upper surface of the first interlayer insulating film, a second wiring film is formed on the first interlayer insulating film, and a second interlayer insulating film is formed so as to cover the second wiring film. Forming a first contact hole penetrating through the second interlayer insulating film, the second wiring film and the first interlayer insulating film and reaching the first wiring film; Since the second contact hole penetrating through the first interlayer insulating film and reaching the semiconductor substrate is formed at the same time, the time difference required for etching each contact hole can be reduced, and the semiconductor at the bottom of the second contact hole can be reduced. Method of manufacturing semiconductor device that can reduce substrate scraping It is possible to provide a.

According to a ninth aspect of the present invention, a first wiring film is formed on a semiconductor substrate, and a first interlayer insulating film is formed so as to cover the first wiring film. Forming a second wiring film on the interlayer insulating film, and forming a second interlayer insulating film so as to cover the second wiring film;
A first contact hole penetrating through the second wiring film and the first interlayer insulating film and reaching the first wiring film; and a first contact hole passing through the second interlayer insulating film and the first interlayer insulating film and on the semiconductor substrate. In a method of manufacturing a semiconductor device in which a second contact hole is formed at the same time, a diameter of an upper portion of the first contact hole is set to be larger than a diameter of an upper portion of the second contact hole. When the second wiring film is penetrated during the formation of the second wiring film, the etching condition is changed to increase the amount of deposition on the second wiring film, and the opening portion penetrated by the first contact hole of the second wiring film is changed. Is formed in a tapered shape whose diameter becomes smaller toward the lower part,
Since the opening of the second wiring film is adjusted so that the diameter of the lower end is equal to the diameter of the second contact hole, the time difference required for etching each contact hole can be reduced, and each contact hole can be reduced. Since the etching control can be easily performed, it is possible to provide a method of manufacturing a semiconductor device capable of further reducing the shaving of the semiconductor substrate at the bottom of the second contact hole.

According to a tenth aspect of the present invention, in the ninth aspect, the condition for etching the second wiring film is determined by using a CHF ₃ / CF ₄ / Ar / O ₂ gas system. By reducing the ratio of ₂ and etching, the amount of deposition on the second wiring film is increased and a desired tapered shape is obtained, so that the desired tapered shape of the opening of the second wiring film is reliably formed. It is possible to provide a method of manufacturing a semiconductor device that can perform the above.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a configuration of a semiconductor device according to a first embodiment of the present invention;

FIG. 2 is a cross-sectional view showing a method for manufacturing the semiconductor device shown in FIG.

FIG. 3 is a sectional view illustrating the method of manufacturing the semiconductor device illustrated in FIG. 1;

FIG. 4 is a sectional view illustrating the method of manufacturing the semiconductor device illustrated in FIG. 1;

FIG. 5 is a sectional view illustrating the method of manufacturing the semiconductor device illustrated in FIG. 1;

FIG. 6 is a sectional view showing a configuration of a semiconductor device according to a second embodiment of the present invention;

FIG. 7 is a sectional view illustrating the method of manufacturing the semiconductor device illustrated in FIG. 6;

FIG. 8 is a sectional view showing a configuration of a semiconductor device according to a third embodiment of the present invention;

FIG. 9 is a sectional view illustrating the method of manufacturing the semiconductor device illustrated in FIG. 8;

FIG. 10 is a sectional view showing a configuration of a semiconductor device according to a fourth embodiment of the present invention.

11 is a sectional view illustrating the method of manufacturing the semiconductor device illustrated in FIG. 10;

FIG. 12 is a sectional view showing a configuration of a semiconductor device according to a fifth embodiment of the present invention.

FIG. 13 is a diagram showing a relationship between a diameter of a contact hole and an etching rate.

FIG. 14 is a cross-sectional view illustrating a configuration of a conventional semiconductor device.

FIG. 15 is a sectional view illustrating the method of manufacturing the semiconductor device illustrated in FIG. 14;

16 is a sectional view illustrating the method of manufacturing the semiconductor device illustrated in FIG. 14;

FIG. 17 is a sectional view illustrating the method of manufacturing the semiconductor device illustrated in FIG. 14;

FIG. 18 is a sectional view illustrating the method of manufacturing the semiconductor device illustrated in FIG. 14;

[Explanation of symbols]

15 semiconductor substrate, 15a groove, 16, 33 element isolation layer, 17, 29, 34 first wiring film, 18, 30, 3
5, 38, 43 First interlayer insulating film, 19 Second wiring film, 19a Opening, 20 Second interlayer insulating film, 21
Third wiring film, 22, 31, 36, 41, 44, 46
First contact holes, 23, 32, 37, 42, 4
5, 47 Second contact hole, 39 Lower insulating film, 40 Upper insulating film.

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Takahiro Yokoi 2-3-2 Marunouchi, Chiyoda-ku, Tokyo F-term (reference) 4M104 BB01 DD08 DD16 DD17 DD19 EE08 EE14 FF08 FF09 HH12 5F004 AA11 BA04 BA14 DA01 DA16 DA23 DA26 DB01 DB02 DB03 DB07 EA10 EA27 EA32 EB01 EB02 EB03 EB04 5F033 HH04 KK04 NN39 QQ08 QQ09 QQ10 QQ11 QQ39 QQ48 QQ73 QQ76 RR04 RR06 RR15 SS04 SS13 SS25 SS27 TT02 WW01

Claims (10)

[Claims] A semiconductor substrate having a first wiring film formed thereon; and a first substrate formed to cover the first wiring film.
Semiconductor device, comprising: a first interlayer insulating film, a second wiring film formed on the first interlayer insulating film, and a second interlayer insulating film formed to cover the second wiring film At
A first contact hole penetrating through the second interlayer insulating film, the second wiring film, and the first interlayer insulating film and reaching the first wiring film; A second contact hole penetrating through the first interlayer insulating film and reaching the semiconductor substrate; and an upper surface of the first interlayer insulating film is flattened by a step formed by the first wiring film. A semiconductor device, comprising: 2. The method according to claim 1, wherein the first wiring film has first and second film thicknesses.
2. The time required for etching the contact hole is set to be equal.
3. The semiconductor device according to claim 1. 3. The semiconductor device according to claim 1, wherein the first wiring film is formed on an element isolation layer buried in the semiconductor substrate, and the thickness of the element isolation layer protruding from the upper surface of the semiconductor substrate is first and second. 3. The semiconductor device according to claim 1, wherein each time required for etching the second contact hole is set to be equal. 4. 4. The first interlayer insulating film includes a lower insulating film and an upper insulating film, and an upper surface of the lower insulating film is formed in a stepped shape by the first wiring film. 2. An upper surface of the semiconductor device according to claim 1, wherein a step formed by the first wiring film is flattened, and an etching speed of the upper insulating film is lower than an etching speed of the lower insulating film.
The semiconductor device according to claim 3. 5. The semiconductor device according to claim 4, wherein the upper insulating film is formed of a nitride film, and the lower insulating film is formed of an oxide film.
3. The semiconductor device according to claim 1. 6. A semiconductor substrate having a first wiring film formed thereon and a first substrate formed so as to cover the first wiring film.
Semiconductor device, comprising: a first interlayer insulating film, a second wiring film formed on the first interlayer insulating film, and a second interlayer insulating film formed to cover the second wiring film At
A first contact hole penetrating through the second interlayer insulating film, the second wiring film, and the first interlayer insulating film and reaching the first wiring film; A second contact hole penetrating the first interlayer insulating film and reaching the semiconductor substrate, wherein a diameter of the first contact hole is larger than a diameter of the second contact hole. Semiconductor device. 7. An opening portion penetrated by the first contact hole of the second wiring film is formed in a tapered shape whose diameter becomes smaller toward a lower portion, and the opening portion of the second wiring film is formed in a tapered shape. 7. The semiconductor device according to claim 6, wherein the diameter of the lower end is equal to the diameter of the second contact hole. 8. A step of forming a first wiring film on the semiconductor substrate, forming a first interlayer insulating film so as to cover the first wiring film, and forming an upper surface of the first interlayer insulating film. Flattening a step due to the first wiring film, forming a second wiring film on the first interlayer insulating film, and forming a second interlayer film so as to cover the second wiring film. Forming an insulating film, a first contact hole penetrating through the second interlayer insulating film, the second wiring film, and the first interlayer insulating film and reaching the first wiring film; Forming a second contact hole penetrating through the second interlayer insulating film and the first interlayer insulating film and reaching the semiconductor substrate at the same time. . 9. A step of forming a first wiring film over a semiconductor substrate, a step of forming a first interlayer insulating film so as to cover the first wiring film, and a step of forming the first interlayer insulating film Forming a second wiring film thereon, forming a second interlayer insulating film so as to cover the second wiring film, forming a second interlayer insulating film, covering the second wiring film, A first contact hole that penetrates through the first interlayer insulating film and reaches the first wiring film; and a second contact hole that penetrates through the second interlayer insulating film and the first interlayer insulating film. Forming a second contact hole and a second contact hole at the same time, so that the diameter of the upper part of the first contact hole is larger than the diameter of the upper part of the second contact hole. To be set, and forming the first contact hole. When penetrating the second wiring film, the etching condition is changed to increase the amount of deposition on the second wiring film, and the opening penetrated by the first contact hole in the second wiring film is changed. And forming the opening of the second wiring film so that the diameter of the lower end is equal to the diameter of the second contact hole. Manufacturing method of a semiconductor device. 10. The second wiring film is etched by using a gas system of CHF ₃ / CF ₄ / Ar / O ₂ with a small ratio of O ₂ to perform etching.
10. The method of manufacturing a semiconductor device according to claim 9, wherein a desired tapered shape is obtained by increasing the amount of deposition on the wiring film.