JP2000100512A - Electrical connector - Google Patents

Electrical connector

Info

Publication number
JP2000100512A
JP2000100512A JP11286706A JP28670699A JP2000100512A JP 2000100512 A JP2000100512 A JP 2000100512A JP 11286706 A JP11286706 A JP 11286706A JP 28670699 A JP28670699 A JP 28670699A JP 2000100512 A JP2000100512 A JP 2000100512A
Authority
JP
Japan
Prior art keywords
contacts
connector
contact
electrical connector
conductive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11286706A
Other languages
Japanese (ja)
Inventor
Gunsang Lim
リム グンサン
Richard D Marowsky
ディー.マロウスキイ リチャード
Ben Khoshnood
コーシュヌード ベン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ABB Installation Products Inc
Original Assignee
Thomas and Betts Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=22452046&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=JP2000100512(A) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Thomas and Betts Corp filed Critical Thomas and Betts Corp
Publication of JP2000100512A publication Critical patent/JP2000100512A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01RELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
    • H01R13/00Details of coupling devices of the kinds covered by groups H01R12/70 or H01R24/00 - H01R33/00
    • H01R13/646Details of coupling devices of the kinds covered by groups H01R12/70 or H01R24/00 - H01R33/00 specially adapted for high-frequency, e.g. structures providing an impedance match or phase match
    • H01R13/6461Means for preventing cross-talk
    • H01R13/6464Means for preventing cross-talk by adding capacitive elements
    • H01R13/6466Means for preventing cross-talk by adding capacitive elements on substrates, e.g. printed circuit boards [PCB]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01RELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
    • H01R13/00Details of coupling devices of the kinds covered by groups H01R12/70 or H01R24/00 - H01R33/00
    • H01R13/646Details of coupling devices of the kinds covered by groups H01R12/70 or H01R24/00 - H01R33/00 specially adapted for high-frequency, e.g. structures providing an impedance match or phase match
    • H01R13/6461Means for preventing cross-talk
    • H01R13/6467Means for preventing cross-talk by cross-over of signal conductors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01RELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
    • H01R13/00Details of coupling devices of the kinds covered by groups H01R12/70 or H01R24/00 - H01R33/00
    • H01R13/646Details of coupling devices of the kinds covered by groups H01R12/70 or H01R24/00 - H01R33/00 specially adapted for high-frequency, e.g. structures providing an impedance match or phase match
    • H01R13/6473Impedance matching
    • H01R13/6474Impedance matching by variation of conductive properties, e.g. by dimension variations
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0213Electrical arrangements not otherwise provided for
    • H05K1/0216Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/0228Compensation of cross-talk by a mutually correlated lay-out of printed circuit traces, e.g. for compensation of cross-talk in mounted connectors
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/0393Flexible materials
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits
    • H05K1/118Printed elements for providing electric connections to or between printed circuits specially for flexible printed circuits, e.g. using folded portions
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/16Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
    • H05K1/162Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed capacitors
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/09218Conductive traces
    • H05K2201/09245Crossing layout
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/403Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4092Integral conductive tabs, i.e. conductive parts partly detached from the substrate
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S439/00Electrical connectors
    • Y10S439/941Crosstalk suppression
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49718Repairing
    • Y10T29/49721Repairing with disassembling
    • Y10T29/4973Replacing of defective part

Landscapes

  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Details Of Connecting Devices For Male And Female Coupling (AREA)
  • Coupling Device And Connection With Printed Circuit (AREA)
  • Telephone Set Structure (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide an electrical connector allowing reduction of cross talk coupling between a pair of selected electrical contacts. SOLUTION: This electrical connector, in which cross talk between a pair of selected electrical contacts 12 can be reduced, includes a printed circuit board 14 having a pair of circuit elements connected to the selected contacts 12 within the connector. Routes of signal of the selected contacts 12 are newly decided by pattern means of the circuit elements of a printed circuit board 14. The circuit elements respectively balance a mutual inductance of the new- decided routes of the signal so as to reduce the cross talk.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、電気コネクタに関し、
より詳しくは、低減された漏話干渉を具備した電気コネ
クタに関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrical connector,
More particularly, it relates to an electrical connector with reduced crosstalk interference.

【0002】[0002]

【従来の技術】従来型の電話のRJ45ジャックとプラ
グとのコネクタを用いて、音声伝送において要求される
よりも高い伝送周波数でのデータ伝送を行うための努力
が近年されている。このようなジャックとプラグのコネ
クタの性能基準は、EUA/TIA標準TSB−40
(ハードウエア接続仕様)、部類5によって管理されて
いる。この標準における部類5のレベルの1つに、電気
コネクタにおいて隣接する接点との間の漏話結合をより
低いレベルとすることがある。参考として、本出願の譲
受人による商用の標準のOMNI RJ45ジャックコ
ネクタは、TSB−40性能要求についての漏話要求の
第3部類を満足している。
2. Description of the Related Art Efforts have been made in recent years to transmit data at higher transmission frequencies than required for voice transmission using the RJ45 jack and plug connectors of conventional telephones. The performance standard of such a jack and plug connector is EUA / TIA standard TSB-40.
(Hardware connection specification), and is managed by category 5. One of the levels of class 5 in this standard is the lower level of crosstalk coupling between adjacent contacts in electrical connectors. For reference, the commercial standard OMNI RJ45 jack connector by the assignee of the present application satisfies the third class of crosstalk requirements for TSB-40 performance requirements.

【0003】漏話の低減あるいは中和は、電気コネクタ
においては、標準のOMNIジャック内において特定の
導体対あるいは接点対の間におけるキャパシタンスを付
加することにより達成できることが知られている。この
ことは、1993年1月29日に出願された、「漏話低
減のための装置と方法」と称された、米国特許出願第0
8/011,020号に詳しく記載されている。この出
願に記載され図示されたように、選択されたコネクタ接
点間のキャパシタンスを増大するための技術は、それら
に個別のコンデンサを付加することである。この出願で
は更に、このような増大されたキャパシタンスは、配置
された及び/又はそこに述べられたコネクタ内において
選択された接点対を連結するために使用されるプリント
回路板上の適当なトレースの配列により派生する漂遊キ
ャパシタンスにより得られることが認識されている。
[0003] It is known that crosstalk reduction or neutralization can be achieved in electrical connectors by adding capacitance between specific conductor or contact pairs within a standard OMNI jack. This is disclosed in U.S. Patent Application No. 0, filed January 29, 1993, entitled "Apparatus and Method for Crosstalk Reduction".
No. 08 / 011,020. As described and illustrated in this application, a technique for increasing the capacitance between selected connector contacts is to add individual capacitors to them. Further, in this application, such increased capacitance may result in the appropriate traces on the printed circuit board being used to connect the selected contact pairs in the connectors located and / or described therein. It is recognized that the stray capacitance derived from the arrangement results in a stray capacitance.

【0004】[0004]

【発明が解決しようとする課題】このため、部類5の漏
話要求を有するだけでなく、そのコネクタのコストを削
減し且つその製造能力を改良することができる、電気コ
ネクタが望まれている。更に、標準のOMNIプラグに
改良されたジャックを使用して部類5の性能レベルを申
し分なく満足するように、標準の装置を出来るだけ利用
し続けることが望まれている。
Therefore, there is a need for an electrical connector that not only has the crosstalk requirements of class 5, but also can reduce the cost of the connector and improve its manufacturing capabilities. In addition, it is desirable to continue to utilize the standard equipment as much as possible so as to satisfy the performance levels of Class 5 using improved jacks on standard OMNI plugs.

【0005】[0005]

【発明の目的】従って、本発明の目的は、選択された電
気接点対の間の漏話結合を低減することができる電気コ
ネクタを提供することを目的とする。
Accordingly, it is an object of the present invention to provide an electrical connector which can reduce crosstalk coupling between selected pairs of electrical contacts.

【0006】[0006]

【課題を解決するための手段】本発明の好ましい構成に
おいて、電気コネクタは、絶縁性のハウジングと、この
ハウジング上に支持された複数の電気接点とを含んで構
成される。接点は、各接点対の間に空間をあけて並んだ
配列で配置されている。誘電基板が接点の上に位置して
おり、導電性のトレースが誘電基板により支持されてい
る。導電性のトレースは、コネクタ内の1つの接点と空
間的に揃えて配置されている。導電性のトレースは、誘
電基板の誘電率および透磁率を所定の相互インダクタン
ス及びキャパシタンスに規定するための形状である。ま
た、導電性のトレースを電気コネクタ内の他の接点の1
つに接続するための導電性要素が設けられている。
In a preferred embodiment of the present invention, an electrical connector includes an insulative housing and a plurality of electrical contacts supported on the housing. The contacts are arranged in a side-by-side arrangement with a space between each pair of contacts. A dielectric substrate is located over the contacts and conductive traces are supported by the dielectric substrate. The conductive trace is spatially aligned with one of the contacts in the connector. The conductive traces are shaped to define the permittivity and permeability of the dielectric substrate to a predetermined mutual inductance and capacitance. Also, conductive traces may be placed on one of the other contacts in the electrical connector.
A conductive element is provided for connecting the two.

【0007】[0007]

【実施例】以下に本発明の実施例を説明する。図1に
は、多接点の電気コネクタ内においてキャパシタンスを
増大する場合に使用される本発明の一態様が図式的に示
されている。図式的には、例示した電気コネクタは、並
んだ配列で配置された8つの接点12を有している。好
ましい形状においては接点のそれぞれは、断面が略長四
角形状の断面と実質的に平らな上面を有し、またそれぞ
れの接点12の上面は略共通面内に位置している。これ
らの接点12は、標準のOMNI RJ45ジャックコ
ネクタを表すように形成されている。
Embodiments of the present invention will be described below. FIG. 1 schematically illustrates one embodiment of the present invention for use in increasing capacitance in a multi-contact electrical connector. Schematically, the illustrated electrical connector has eight contacts 12 arranged in a side-by-side arrangement. In a preferred configuration, each of the contacts has a substantially rectangular cross-section and a substantially flat top surface, and the top surface of each contact 12 lies in a substantially common plane. These contacts 12 are formed to represent a standard OMNI RJ45 jack connector.

【0008】接点12上に位置するのは、誘電基板16
を含んでなるプリント回路板14である。銅のような導
電性材料でできたトレース18が、選択された接点1
2、例えば図示した接点No.1、No.4、並びにN
o.8と空間的に揃えて、誘電基板16上に支持されて
いる。誘電材料とその透磁率をそれらの間に備えた状態
で接点12上にトレース18を配列することで、平行板
と考えられる導電性のトレースと接点との間の容量性の
関係が生成され、またインダクタンスとコンダクタンス
が同様に生じる。理論上は、平行板間のキャパシタンス
は、基本的には(1)板の面積A、(2)板の間の距離
D、並びに(3)板の間の誘電材料の誘電率Kの関数で
ある。このようなキャパシタンス、ピコファラド(p
F)は、式:C=(0.2249A/D)K、を用いて
計算される。接点対の間のキャパシタンスを増大するた
め、導電性のトレース18を他のコネクタ接点12と接
続しても良い。例えば、電線20のような接続要素を用
いて導電性のトレース18を接点8を越えて接点6に接
続し、また他の電線22を用いて導電性のトレース18
を接点4を越えて接点6に接続することもできる。また
この代わりに、導電性のトレース18から接続トレース
18aを形成し、この接続トレース18aを、例えば、
接点3に接続する構成としても良い。そして、このよう
に構成することで、接点対1−3の間のキャパシタンス
24を増大し、接点対4−6の間のキャパシタンス26
を増大し、並びに接点対6−8の間のキャパシタンス2
8を増大することができる。一例として、MICA基板
は0.002インチ厚のものが選定され、また銅の導電
性のトレースは0.002インチ厚のものが選定され
る。
[0008] Located on the contact 12 is a dielectric substrate 16.
Is a printed circuit board 14. Traces 18 made of a conductive material such as copper are used to select selected contacts 1
2, for example, the illustrated contact No. 1, No. 4, and N
o. 8 and supported on a dielectric substrate 16. Arranging the traces 18 on the contacts 12 with the dielectric material and its permeability between them creates a capacitive relationship between the conductive traces and the contacts, which are considered parallel plates, In addition, inductance and conductance similarly occur. In theory, the capacitance between the parallel plates is basically a function of (1) the area A of the plates, (2) the distance D between the plates, and (3) the dielectric constant K of the dielectric material between the plates. Such a capacitance, picofarad (p
F) is calculated using the formula: C = (0.2249A / D) K. Conductive traces 18 may be connected to other connector contacts 12 to increase the capacitance between the contact pairs. For example, the conductive trace 18 may be connected to the contact 6 beyond the contact 8 using a connecting element such as a wire 20, and the conductive trace 18 may be connected using another wire 22.
Can be connected to the contact 6 beyond the contact 4. Alternatively, a connection trace 18a is formed from the conductive trace 18, and this connection trace 18a is
It may be configured to connect to the contact 3. With this configuration, the capacitance 24 between the contact pair 1-3 is increased, and the capacitance 26 between the contact pair 4-6 is increased.
And the capacitance 2 between the contact pair 6-8
8 can be increased. As an example, the MICA substrate is selected to be 0.002 inches thick, and the copper conductive traces are selected to be 0.002 inches thick.

【0009】次に、図2から図4を参照する。図2、4
には、図1を参照して説明した本発明の原理が実際に漏
話低減を図るためにどのように実施化されるのかが示さ
れている。これらの図において、本発明に従って変更さ
れた、OMNI RJ45コネクタとして知られている
形式の電気コネクタが示されている。ここに示された実
施例では、工業的使用に従って4つの接点対を規定する
8つの接点が示されている。
Next, reference will be made to FIGS. Figures 2 and 4
Shows how the principles of the invention described with reference to FIG. 1 are actually implemented to reduce crosstalk. In these figures, an electrical connector of the type known as an OMNI RJ45 connector, modified in accordance with the present invention, is shown. In the embodiment shown here, eight contacts are shown defining four contact pairs according to industrial use.

【0010】コネクタ30は、その上に複数の電気接点
34を並んだ配置で支持した絶縁性のハウジング32を
有している。各接点34は、OMNIプラグコネクタ
(図示せず)内の補完的な接点と電気接続をする片持ち
梁形式で作られた前方端子部34aを有している。各接
点34は更に、好ましくは、絶縁された電線の導体と電
気接続するための絶縁変位接点(IDC)の形状であ
る、後方端子を有している。各前方端子34aと後方端
子34bとの間に、各接点は、断面が略長四角形状であ
り前方と方向の端子の間に実質的に平らな面領域を有す
る境界部34cを含んでいる。この平らな境界部34c
は、IDC後方端子34bと片持ち梁式の前方端子34
aのピッチ間のピッチ境界を作るために形成され、横に
離間された配列でコネクタハウジング32上に支持され
て、境界部34cの平らな面が実質的に共通面内に位置
するようになる。
The connector 30 has an insulating housing 32 on which a plurality of electrical contacts 34 are supported in a side-by-side arrangement. Each contact 34 has a cantilevered front terminal portion 34a for electrical connection with a complementary contact in an OMNI plug connector (not shown). Each contact 34 further has a rear terminal, preferably in the form of an insulation displacement contact (IDC) for electrical connection with the conductor of the insulated wire. Between each front terminal 34a and rear terminal 34b, each contact includes a boundary 34c that is generally rectangular in cross section and has a substantially flat surface area between the front and direction terminals. This flat border 34c
Are the IDC rear terminal 34b and the cantilever type front terminal 34
a, formed on the connector housing 32 in a laterally spaced arrangement to create a pitch boundary between the pitches of a, such that the flat surface of the boundary portion 34c lies substantially in a common plane. .

【0011】本発明によれば、コネクタ30内の2つの
接点の信号路は、コネクタの漏話低減特性を助力するべ
く後述する目的のために再ルート決めされる。このよう
にして、コネクタの後方部においては、接点3の信号路
は接点5と7の間に位置される一方、図2に示したよう
に、信号路6は接点2と4の間に位置される。図2にお
いて、後方端子部34aは、接点1−8を正しい連続順
に維持される
In accordance with the present invention, the signal paths of the two contacts within connector 30 are rerouted for the purposes described below to assist in the crosstalk reduction characteristics of the connector. Thus, at the rear of the connector, the signal path of contact 3 is located between contacts 5 and 7, while signal path 6 is located between contacts 2 and 4, as shown in FIG. Is done. In FIG. 2, the rear terminal portion 34a maintains the contacts 1-8 in the correct sequence.

【0012】信号路の再ルート決めするため、接点3と
6が分割され、接点3のために前方部34dと不連続の
後方部34fが規定される。同様に、接点6のために、
前方部34fが後方部34gから不連続に規定される。
For rerouting the signal path, the contacts 3 and 6 are split and a front portion 34d and a discontinuous rear portion 34f are defined for the contact 3. Similarly, for contact 6,
The front portion 34f is discontinuously defined from the rear portion 34g.

【0013】絶縁された回路を含んだプリント回路板
(PCB)36が電気コネクタ30に、好ましくはその
底部に取付けられる。このPCB36は、その上に一対
の回路要素40と42を支持した誘電基板38を有して
いる。回路要素40は、導電性のトレース40a、接続
トレース40b並びに再ルート決めトレース40cを有
している。導電性のトレース40aは、接点7の上部に
空間的に揃えて位置して、これとともに容量性の関係を
形成する。接続トレース40bは、導電性のトレース4
0aから再ルート決めトレース40cに向かって横方向
に延在し、それが適切に接続される場所において分割さ
れた接点6の後方部34gに橋渡しされる。再ルート決
めトレース40cは、与えられた長さに渡って接点5と
空間的に揃えて位置する範囲を有し、その前方部34d
に接続される場所において接点4の上部において接点3
に橋渡しされる。
A printed circuit board (PCB) 36 containing insulated circuits is attached to the electrical connector 30, preferably at the bottom. The PCB 36 has a dielectric substrate 38 on which a pair of circuit elements 40 and 42 are supported. Circuit element 40 has conductive traces 40a, connection traces 40b, and reroute traces 40c. The conductive traces 40a are spatially aligned over the contacts 7 and form a capacitive relationship therewith. The connection trace 40b is a conductive trace 4
Oa extends laterally towards rerouting trace 40c and is bridged to rear portion 34g of split contact 6 where it is properly connected. The rerouting trace 40c has a range that is spatially aligned with the contact 5 over a given length and its forward portion 34d
Contact 3 on top of contact 4 where it is connected to
Is bridged to.

【0014】回路要素42は、導電性のトレース42
a、接続トレース42b並びに再編成トレース42cを
有している。導電性のトレース42aは、接点2に空間
的に揃えて位置して、これとともに容量性の関係を形成
する。接続トレース42bは、導電性のトレース42a
から再ルート決めトレース42cに向かって横方向に延
在し、それが接続される接点3の後方部34eに橋渡し
される。再ルート決めトレース42cは、与えられた長
さに渡って接点4と空間的に揃えて位置する範囲を有
し、接点5を橋渡しするように形成され、また接点6の
前方部34fに接続される。回路要素40と42は、以
下に指摘するように、このような再ルート決めされた信
号路にキャパシタンスを付加する。
Circuit element 42 includes conductive traces 42
a, a connection trace 42b and a reorganization trace 42c. The conductive traces 42a are spatially aligned with the contacts 2 and form a capacitive relationship therewith. The connection trace 42b is connected to the conductive trace 42a.
Extending laterally to the rerouting trace 42c and bridging to the rear portion 34e of the contact 3 to which it is connected. The rerouting trace 42c has an area that is spatially aligned with the contact 4 over a given length, is formed to bridge the contact 5, and is connected to the front 34f of the contact 6. You. Circuit elements 40 and 42 add capacitance to such a rerouted signal path, as noted below.

【0015】図5に、プリント回路板36をより詳細に
示した。図示した配列では、回路要素40と42は、各
回路要素を規定する導電性のトレース間にクロスオーバ
ー点がないように形成されている。このため、PCB3
6は、回路要素40と42をそれらの間に挟持する一対
の誘電フィルム44で形成される。好ましい構成では、
各導電フィルムは0.001インチ厚のポリイミドで作
られ、このような材料はKAPTONの商標で市販され
入手できるものである。回路要素は、好ましくは、それ
ぞれの厚さが約0.004インチである銅の導電性のト
レースにより規定される。接続トレース40bと42
b、並びに再ルート決め部40cと42cの回路幅は、
典型的には全て、約0.018インチの寸法である。接
続トレース40bと42bは、これら接続トレースが対
応する接点6と3に接続された位置において、それぞれ
拡張された溶接用パッド40dと42dを有している。
同様に、再ルート決めトレース40cと42cの、それ
ぞれ接点6と3に接続されるそれぞれの端子には、同様
に形成された拡張された溶接用パッド40eと42eが
ある。それぞれの溶接用パッド40d,40e並びに4
2d,42eに整列された誘電フィルム44の部分は、
これらの溶接用パッドを露出させてそこに接点3と6の
対応する分割部分を溶接できるように、PCB36の上
面および下面において取り除かれる。
FIG. 5 shows the printed circuit board 36 in more detail. In the illustrated arrangement, circuit elements 40 and 42 are formed such that there are no crossover points between the conductive traces defining each circuit element. Therefore, PCB3
6 is formed of a pair of dielectric films 44 sandwiching the circuit elements 40 and 42 therebetween. In a preferred configuration,
Each conductive film is made of 0.001 inch thick polyimide, such a material being commercially available under the KAPTON trademark. The circuit elements are preferably defined by conductive traces of copper each having a thickness of about 0.004 inches. Connection traces 40b and 42
b, and the circuit width of the rerouting units 40c and 42c
Typically all are about 0.018 inches in size. The connection traces 40b and 42b have expanded welding pads 40d and 42d, respectively, at the locations where they are connected to the corresponding contacts 6 and 3.
Similarly, each terminal of rerouting traces 40c and 42c connected to contacts 6 and 3, respectively, has similarly formed expanded welding pads 40e and 42e. The respective welding pads 40d, 40e and 4
The portions of the dielectric film 44 aligned in 2d, 42e are:
These welding pads are removed on the upper and lower surfaces of the PCB 36 so that the corresponding splits of the contacts 3 and 6 can be welded thereto to expose them.

【0016】更に、図5において、導電性のトレース4
0aと42aは、接点7と2にそれぞれ予め定められた
キャパシタンスを提供するための長さと幅を有するよう
に形成される。例えば、各導電性のトレース40aと4
2aは、約0.050インチの幅46と約0.100イ
ンチの長さを有するように形成されて、接点7とトレー
ス40との間に約2pFの大きさのキャパシタンスを提
供するものである。なお、所望のキャパシタンスに応じ
て他の寸法が選定されることは勿論である。
Further, referring to FIG.
Oa and 42a are formed to have a length and width to provide a predetermined capacitance to contacts 7 and 2, respectively. For example, each conductive trace 40a and 4
2a is formed to have a width 46 of about 0.050 inches and a length of about 0.100 inches to provide a capacitance of about 2 pF between contact 7 and trace 40. . Of course, other dimensions are selected according to the desired capacitance.

【0017】誘電性フィルム44を完全に通って延びる
透孔50と52が、PCBがコネクタ30に取付けられ
た時にこれら透孔50、52が接点6と3の分割部分に
整列して位置するように、配置されている。
Through holes 50 and 52 extending completely through the dielectric film 44 are such that when the PCB is attached to the connector 30, the holes 50 and 52 are aligned with the splits of the contacts 6 and 3. Is located.

【0018】次に、図6と7に、プリント回路板36′
の他の構成例を示した。この配置において、回路要素4
0′と42′は、導電性のトレースの相互に重なり合う
部分があるように、形成される。このようなプリント回
路板36′を構成するため、回路要素40′が第1の誘
電フィルム44′上に形成され、また他の回路要素4
2′は第2の誘電フィルム44′上に形成される。ま
た、回路要素40′と42′を一緒に挟み込んでPCB
36′を組み立てる前に、0.001インチ厚のKAP
TONフィルムのような適当な絶縁物からなる中間層5
4が挿入されて、各回路要素が絶縁される。このように
して、回路パターンが相互に交差するように配列された
PCB36′の構成は、2つの回路要素40と42が1
枚のフィルム上に形成され次いで第2のフィルムにより
被覆される図5のPCB36よりもやや厚く、また製造
するためには僅かに高価となる。
Next, FIGS. 6 and 7 show a printed circuit board 36 '.
Another configuration example was shown. In this arrangement, circuit element 4
0 'and 42' are formed such that there are overlapping portions of the conductive traces. To construct such a printed circuit board 36 ', a circuit element 40' is formed on the first dielectric film 44 'and the other circuit elements 4' are formed.
2 'is formed on the second dielectric film 44'. In addition, the circuit elements 40 'and 42' are
Before assembling 36 ', 0.001 inch thick KAP
Intermediate layer 5 made of a suitable insulating material such as TON film
4 are inserted to insulate each circuit element. In this way, the configuration of the PCB 36 'in which the circuit patterns are arranged so as to intersect each other is such that the two circuit elements 40 and 42 have one circuit element.
5 is slightly thicker than the PCB 36 of FIG. 5 formed on a sheet of film and then covered by a second film, and is slightly more expensive to manufacture.

【0019】図8に、本発明に従って構成された変更さ
れたOMNIジャックの接点と、標準の従来の構成であ
るOMNIプラグを図式的に示した。これらOMNIジ
ャックとOMNIプラグは、典型的には、比較的に長く
また近接した平行多芯回路を構成する。特に、対1(接
点4と5)並びに対3(接点3と6)は漏話問題のため
の最悪の状態を典型的に規定する。
FIG. 8 schematically illustrates a modified OMNI jack contact constructed in accordance with the present invention and a standard conventional OMNI plug. These OMNI jacks and OMNI plugs typically form a relatively long and close parallel multi-core circuit. In particular, pair 1 (contacts 4 and 5) as well as pair 3 (contacts 3 and 6) typically define the worst case for crosstalk problems.

【0020】漏話を減じるために、OMNIジャックの
広い導体領域により規定される領域「a」が、絶縁性の
回路をその上に備えたPCB36を付加することにより
変更される。上記した2つの回路要素が分割された接点
3と6に適切に溶接される。第1の回路要素40の導電
性のトレース40aは、接点7と容量性の関係を有して
いる。同様に、第2の回路要素42の導電性のトレース
42aは、導体2と容量性の関係を有する。回路要素4
0と42を分割された接点3と6に溶接することで、そ
の信号路を再ルート決めするだけでなく、この信号路に
導電性のトレース40aと42aにより生成されたキャ
パシタンスを付加することができる。
To reduce crosstalk, the area "a" defined by the large conductor area of the OMNI jack is modified by adding a PCB 36 with insulating circuitry thereon. The two circuit elements described above are appropriately welded to the divided contacts 3 and 6. The conductive trace 40 a of the first circuit element 40 has a capacitive relationship with the contact 7. Similarly, the conductive trace 42 a of the second circuit element 42 has a capacitive relationship with the conductor 2. Circuit element 4
Welding 0 and 42 to the split contacts 3 and 6 not only reroutes the signal path, but also adds to this path the capacitance created by the conductive traces 40a and 42a. it can.

【0021】更に、OMNIプラグの回路「b」はOM
NIジャックの回路「a」よりもずっと長く、従って電
磁力(EMF)はより大きい。この効果を相殺するた
め、上記した接点3と6の、領域「a」内の信号路は、
PCB36上の回路要素40と42により再ルート決め
される。この領域「a」においては接点3と5が極めて
接近しており、また接点4と6も同様に極めて接近して
いるので、長さ当たりの誘導EMFは領域「b」内の対
向部よりもずっと高い。こうして、領域「a」内のより
短い経路では、十分な量の誘導EMFが、領域「b」の
誘導EMFを相殺するために発生される。本発明の改良
がされていない現用のOMNIコネクタでは、対1と対
3の間の漏話は、典型的には、100MHzにおいて2
6.4dBから26.8dBの間である。ここで、対1
は接点4と5により規定され、また対3は接点3と6に
より規定される。対1と対3との間の漏話は通常は非常
に高く、また主要因は相互インダクタンスである。そし
て、2つの回路要素40と42を用いることで、相互イ
ンダクタンスが釣り合い、対1と対3との間の漏話低減
が達成される。再ルート決めされた信号路と選択された
キャパシタンスによって変更されたOMNIコネクタで
は、測定された漏話は、100MHZにおいて、一方向
において約43.0dBであり、逆方向において約4
2.3dBであった。このように、上記のようにOMN
Iジャックコネクタを変更することで、所望の漏話低減
が図れ、このため、標準の、変更していないOMNIプ
ラグコネクタをそれとの接続のために用いることができ
る。
Further, the circuit "b" of the OMNI plug is an OMNI plug.
It is much longer than the NI jack circuit "a", and therefore has a higher electromagnetic force (EMF). To offset this effect, the signal path of the contacts 3 and 6 in the region "a" is
Rerouted by circuit elements 40 and 42 on PCB 36. In this region "a", the contacts 3 and 5 are very close, and the contacts 4 and 6 are also very close, so that the inductive EMF per length is greater than the opposing portion in the region "b". Much higher. Thus, for a shorter path in region "a", a sufficient amount of induced EMF is generated to offset the induced EMF in region "b". In a working OMNI connector without the improvement of the present invention, the crosstalk between pair 1 and pair 3 is typically 2 at 100 MHz.
It is between 6.4 dB and 26.8 dB. Where
Is defined by contacts 4 and 5, and pair 3 is defined by contacts 3 and 6. Crosstalk between pair 1 and pair 3 is usually very high, and the main factor is mutual inductance. Then, by using the two circuit elements 40 and 42, mutual inductances are balanced and crosstalk reduction between pair 1 and pair 3 is achieved. With the OMNI connector modified by the rerouted signal path and the selected capacitance, the measured crosstalk at 100 MHZ is about 43.0 dB in one direction and about 43.0 dB in the reverse direction.
2.3 dB. Thus, as described above, OMN
By changing the I jack connector, desired crosstalk reduction can be achieved, so that a standard, unmodified OMNI plug connector can be used for connection therewith.

【0022】以上、本発明の好ましい実施例を説明した
が、本発明の技術思想の範囲内において種々の変形が行
えることは勿論である。従って、この好ましい実施例は
例示を意図したものでこれに限定されるものではない。
Although the preferred embodiment of the present invention has been described above, it goes without saying that various modifications can be made within the scope of the technical idea of the present invention. Accordingly, this preferred embodiment is intended to be illustrative and not limiting.

【0023】[0023]

【発明の効果】以上の通り、本発明によれば、選択され
た電気接点対の間の漏話結合を低減することができる電
気コネクタを提供することができる。
As described above, according to the present invention, it is possible to provide an electric connector capable of reducing crosstalk coupling between selected pairs of electric contacts.

【図面の簡単な説明】[Brief description of the drawings]

【図1】多接点コネクタの漏話低減に使用される本発明
の一実施例の形態を図式的に示した説明図である。
FIG. 1 is an explanatory diagram schematically showing an embodiment of an embodiment of the present invention used for reducing crosstalk of a multi-contact connector.

【図2】コネクタ内の選択された接点対の間の漏話低減
を提供のに特に適合したプリント回路板を含むOMNI
ジャックコネクタの上部平面図である。
FIG. 2 shows an OMNI including a printed circuit board specifically adapted to provide crosstalk reduction between selected pairs of contacts in a connector.
FIG. 3 is a top plan view of the jack connector.

【図3】図2のコネクタの前部正面図である。FIG. 3 is a front elevational view of the connector of FIG. 2;

【図4】図2のコネクタのII−II線に沿った断面図であ
る。
FIG. 4 is a cross-sectional view of the connector of FIG. 2 taken along the line II-II.

【図5】図2のコネクタと共に使用される回路板の上部
平面図である。
FIG. 5 is a top plan view of a circuit board used with the connector of FIG. 2;

【図6】図2のコネクタと共に使用されるプリント回路
板の他の実施例を示した説明図である。
FIG. 6 is an explanatory view showing another embodiment of a printed circuit board used with the connector of FIG. 2;

【図7】図6の他のプリント回路板の構成要素の分解図
である。
FIG. 7 is an exploded view of the components of another printed circuit board of FIG. 6;

【図8】(a)と(b)は、標準のOMNIプラグと関
連した、本発明の図示された改良されたOMNIジャッ
クの接点を図式的に示した説明図である。
FIGS. 8 (a) and (b) are schematic illustrations of the contacts of the illustrated and improved OMNI jack of the present invention in connection with a standard OMNI plug.

【符号の説明】[Explanation of symbols]

12 接点 14 プリント回路板 16、36 誘電基板 18 トレース 40、42 回路要素 12 contact 14 printed circuit board 16, 36 dielectric substrate 18 trace 40, 42 circuit element

───────────────────────────────────────────────────── フロントページの続き (72)発明者 リチャード ディー.マロウスキイ アメリカ合衆国.テネシー,コリエルヴィ ル,クリークヴァレイ ドライヴ 1301 (72)発明者 ベン コーシュヌード アメリカ合衆国.フロリダ,パークラン ド,ヒアリーレーン 7121 ──────────────────────────────────────────────────続 き Continued on the front page (72) Richard Dee. Marlowski United States. Tennessee, Coryerville, Creek Valley Drive 1301 (72) Inventor Ben Koshnud USA. Florida, Parkland, Hiale Lane 7121

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 絶縁性のハウジング、 前記ハウジング上に支持された複数の電気接点であっ
て、前記電気接点は各接点対の間に間隔をあけて並んだ
配列で配置された電気接点、 前記接点上に位置する誘電基板、 前記誘電基板に支持された導電性のトレースであって、
前記トレースは前記接点の1つと空間的に揃えて配置さ
れるとともに前記誘電基板の透磁率および誘電率により
予め定められた相互インダクタンスとキャパシタンスを
規定するトレース、並びに前記導電性のトレースを前記
接点の他の1つに接続するための導電性要素を含んでな
ることを特徴とする電気コネクタ。
An insulating housing; a plurality of electrical contacts supported on the housing, wherein the electrical contacts are arranged in a spaced-apart array between each pair of contacts; A dielectric substrate located on the contact, a conductive trace supported on the dielectric substrate,
The trace is spatially aligned with one of the contacts and defines a mutual inductance and capacitance predetermined by the magnetic permeability and permittivity of the dielectric substrate, and the conductive trace is An electrical connector comprising a conductive element for connecting to another one.
【請求項2】 前記導電性要素が、前記導電性のトレー
スに接続された導電性のトレース部分から構成されるこ
とを特徴とする請求項1記載の電気コネクタ。
2. The electrical connector according to claim 1, wherein said conductive element comprises a conductive trace portion connected to said conductive trace.
【請求項3】 前記誘電基板上には複数の導電性のトレ
ースがあり、それぞれ前記コネクタの選択された接点と
空間的に揃えて配置された部分を有することを特徴とす
る請求項1記載の電気コネクタ。
3. The method of claim 1, wherein a plurality of conductive traces are on the dielectric substrate, each having a portion spatially aligned with a selected contact of the connector. Electrical connector.
【請求項4】 前記接点が断面略長四角形状であり、前
記導電性のトレースが上に位置する実質的に平らな面を
それぞれ有することを特徴とする請求項3記載の電気コ
ネクタ。
4. The electrical connector of claim 3 wherein said contacts have a generally rectangular shape in cross section and said conductive traces each have a substantially flat surface located thereon.
JP11286706A 1993-10-05 1999-10-07 Electrical connector Pending JP2000100512A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US132015 1993-10-05
US08/132,015 US5470244A (en) 1993-10-05 1993-10-05 Electrical connector having reduced cross-talk

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP6241655A Division JP3024050B2 (en) 1993-10-05 1994-10-05 Electrical connector and method for reducing crosstalk between electrical contacts of electrical connector

Publications (1)

Publication Number Publication Date
JP2000100512A true JP2000100512A (en) 2000-04-07

Family

ID=22452046

Family Applications (2)

Application Number Title Priority Date Filing Date
JP6241655A Expired - Lifetime JP3024050B2 (en) 1993-10-05 1994-10-05 Electrical connector and method for reducing crosstalk between electrical contacts of electrical connector
JP11286706A Pending JP2000100512A (en) 1993-10-05 1999-10-07 Electrical connector

Family Applications Before (1)

Application Number Title Priority Date Filing Date
JP6241655A Expired - Lifetime JP3024050B2 (en) 1993-10-05 1994-10-05 Electrical connector and method for reducing crosstalk between electrical contacts of electrical connector

Country Status (8)

Country Link
US (2) US5470244A (en)
EP (2) EP0649194B1 (en)
JP (2) JP3024050B2 (en)
CA (1) CA2133635A1 (en)
DE (1) DE69418966T2 (en)
ES (1) ES2136170T3 (en)
SG (2) SG83732A1 (en)
TW (1) TW257894B (en)

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EP0649194A1 (en) 1995-04-19
DE69418966T2 (en) 1999-10-21
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EP0649194B1 (en) 1999-06-09
SG48308A1 (en) 1998-04-17
DE69418966D1 (en) 1999-07-15
CA2133635A1 (en) 1995-04-06
JP3024050B2 (en) 2000-03-21
TW257894B (en) 1995-09-21
US5454738A (en) 1995-10-03
US5470244A (en) 1995-11-28
EP0898340A1 (en) 1999-02-24
JPH07201394A (en) 1995-08-04
ES2136170T3 (en) 1999-11-16

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