JP2000092141A - Level control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a level control circuit capable of miniaturizing a decimation filter and the signal processing part of the poststage and reducing power consumption. SOLUTION: This level control circuit changes the response time of a decimation filter 103 for attenuating unwanted wave components included in a digital code for which signals frequency converted into a quadrature demodulation part 100 and band-limited to a desired band in an LPF part 101 are analog-to- digital converted in a Δmodulation (or ΔΣ modulation) part 102, based on the output information of a level detection/discrimation circuit 105 for detecting and discriminating, the reception level. For instance, the stage number of the decimation filter 103 is changed corresponding to the reception level. Thus, the decimation filter 103 and the signal processing part 106 are miniaturized, and the power consumption is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a level control circuit in a mobile communication receiving circuit, and more particularly to a level control circuit in a receiving circuit employing a decimation filter required for an analog-to-digital converter.

[0002]

2. Description of the Related Art Analog-to-digital converters employing (1) modulation or (2) modulation (hereinafter referred to as AD converters).
Is an effective technique in a mobile communication receiving circuit or the like that requires a wider band and higher accuracy. When this AD converter is employed, it is necessary to employ a decimation filter for thinning out the sampling rate. Conventionally, a decimation filter has a role of suppressing a harmonic noise component generated by △ modulation or △ Σ modulation and securing a required SN ratio from a folded component due to thinning.

However, when the present invention is applied to a mobile communication receiving circuit or the like, a signal receiving level fluctuates, which leads to an increase in the size of a decimation filter and a subsequent signal processing unit.

[0004]

As described above, when a signal whose reception level fluctuates is subjected to A / D conversion, there is a problem in that the subsequent decimation filter and the subsequent signal processing unit become large.

SUMMARY OF THE INVENTION The present invention has been made in view of such problems, and can reduce the size and power consumption of a decimation filter and a subsequent signal processing unit, and can be realized with a simple configuration. It is an object to provide a simple level control circuit.

[0006]

A level control circuit according to the present invention converts a signal in a radio frequency band to a predetermined frequency, and restricts a band of an output signal of the frequency converter to a desired band. Band-limiting means, analog-to-digital conversion means for sampling an output signal of the band-limiting means using a clock signal having a frequency component higher than the desired band, and converting the output signal into a digital code; and inputting the output signal of the analog-to-digital conversion means A decimation filter means for attenuating unnecessary wave components contained in the digital code as a signal, and a clock signal having a frequency component lower than the clock frequency used in the analog-to-digital conversion means, having an output signal of the decimation filter means as an input signal. Sampling means for sampling an input signal by means of And level detecting means for receiving the level detection of the predetermined signal, based on the output information of the level detection means, characterized in that a means for changing the response time of the decimation filter means.

Here, the analog-to-digital conversion means is:
A modulation method or a modulation method may be employed. As described above, by adopting the configuration having the means for changing the response time of the decimation filter means, it is possible to reduce the size and power consumption of the decimation filter means and the subsequent signal processing unit under certain input conditions.

That is, an AD converter employing 採用 modulation or △ Σ modulation applied to mobile communication oversamples a signal with a clock having a rate higher than the signal bandwidth and converts the signal into a digital code. The digital code output as the Δ modulation or the Δ modulation contains a noise component having a large level in addition to the desired signal, and thus is not suitable for demodulation processing as it is. Further, since the sampling rate required for such an AD converter is as high as several tens to several hundred times or more as compared with the desired band, it is difficult to reduce the power consumption of the subsequent signal processing unit as it is. Therefore, thinning is performed to a sampling rate lower than usual.
For this purpose, a decimation filter is generally employed to suppress aliasing noise caused by thinning.

Therefore, when the reception level is low, it is necessary to sufficiently attenuate the aliasing noise, but when the reception level is high, it is sufficient to attenuate only the amount necessary to secure the SN ratio of the decimated signal. .

Therefore, the effect is realized by controlling the response time of the decimation filter means based on the reception level of a predetermined signal. The decimation filter means increases the response time by increasing the number of stages, for example, so that the attenuation characteristic of out-of-band noise becomes steep. Utilizing this characteristic, when the reception level is small, for example, the number of stages of the decimation filter means is increased to lengthen the response time, and when the reception level is high, for example, the number of stages of the decimation filter means is shortened to shorten the response time. Thus, the size of the decimation filter unit can be reduced under the condition that the reception level is high.

In the case of realizing a filter having a sufficient length in advance in preparation for an input near the reception sensitivity, it is possible to stop the clock supply to a part in accordance with the reception level. This makes it possible to reduce the power consumption of the digital section under the condition that the reception level is high.

Instead of changing the number of stages, the decimation filter means may use a coefficient multiplier, and may change the coefficient to change the impulse response characteristic to change the response time. Even in such a case, the size of the decimation filter unit can be reduced.

Further, with these configurations, it is possible to control so that the number of bits of the output signal of the decimation filter means is always constant regardless of the level. Thus, the signal processing unit downstream of the decimation filter unit can be simplified.

[0014]

Embodiments of the present invention will be described below in detail with reference to the drawings. In the following drawings, the same symbols indicate the same or corresponding parts. FIG. 1 shows the configuration of an embodiment of a level control circuit according to the present invention.

In FIG. 1, a quadrature demodulation section 100 quadrature demodulates a received signal into a base band. LPF unit 1
In step 01, the in-phase component (I) and the quadrature component (Q) of the baseband signal subjected to quadrature demodulation are each limited to an appropriate bandwidth. The 変 調 modulation (or △ Σ modulation) unit 102 converts an analog signal to be an input signal into a digital code using a clock having a higher rate than the signal bandwidth. △
The digital code serving as the output signal of the modulation (or △ Σ modulation) section 102 contains many noise components in addition to the desired signal, and is not suitable for demodulation as it is. When △ modulation (or △ Σ modulation) is adopted, the sampling rate is usually several tens to several hundred times or more higher than the desired band, so that the latch 104 for thinning out data and the aliasing noise suppression are used. Is provided.

As the decimation filter 103,
Usually, it is realized by an FIR filter or an IIR filter. For example, the FIR filter and the IIR filter are connected in series with the same configuration, so that the attenuation characteristic of out-of-band noise becomes steep.

The number of stages of the decimation filter 103 is variable, and the number of stages is controlled based on the output signal of the level detection / judgment circuit 105. That is, when the level detection / determination circuit 105 determines that the average reception level is low, the decimation filter 1
03, the number of stages of the decimation filter 103 is reduced when it is determined that the average reception level is large.

Next, the decimation filter 103 is set to F
FIG. 2 shows a specific configuration example in the case of using an IR filter. As shown in the figure, for example, a configuration is used in which one or more stages of serial-in-parallel-out registers are used as units, and one stage to a maximum of N stages are connected in series. In this configuration example, N = 3. The number of stages to be connected is determined and used based on the average reception level.

For example, when it is determined that the average reception level is large and the decimation filter 103 is configured in one stage, the output signal of the first stage register 201 is changed by the register output switching means (selector) 204 to the output signal of the decimation filter 103. And switch connection.
In this case, stopping the supply of the clock to the registers 202 and 203 in the second and third stages is effective for reducing power consumption.

Conversely, when the average reception level is determined to be low and the decimation filter 103 is configured in three stages, the output signal of the third stage register 203 is used as it is by using the register output switching means (selector) 204. 103 is an output signal. At this time, in the frequency characteristics of the decimation filter 103, a large amount of attenuation in a high frequency region can be obtained. Therefore, it is effective for securing SN from aliasing noise.

When these configurations are realized by a digital signal processor, the control of the number of stages can be realized by the control of the number of instructions, so that a simpler configuration can be realized.

Next, a method of controlling the number of stages of the decimation filter 103 will be further described. As described above, the decimation filter 103 has a maximum number of N stages connected in series. At this time, the detection range of the average reception level is divided into N steps by (N-1) thresholds, and as a result of comparing the detection level and the threshold, the level detection circuit 301 determines which step belongs. And the number of stages is determined.

FIG. 3 shows a level detection / judgment circuit 105.
The following shows a specific configuration example. In the figure, the level detection circuit 301 is provided with a band-limited latch 10 shown in FIG.
The signal at the output stage of No. 4 is input, and the average power level of this signal is detected. When the desired signal is input in the base band, the average power level is obtained by calculating I ² + Q ² from the in-phase component (I) and the quadrature component (Q) and averaging for a certain section. . The desired signal for detecting the average power level is the LPF shown in FIG.
The signal between the output stage of the unit 101 and the output stage of the latch 104 can be used (more generally,
There is also a method of finding an average amplitude level for a desired wave whose band has been limited in the intermediate frequency band).

The reception levels detected in this way are divided into a plurality of (N-1) threshold groups Th1, Th2,.
h (N−1) is input to the level comparison circuit 302. The level comparison circuit 302 compares a preset threshold level with the value of the power level detected by the level detection circuit 301, and outputs (N-1) comparison results. The determination circuit 303 includes a level comparison circuit 302
The number of filter stages is determined from the output information of FIG.
And outputs a control signal to the register output switching means (selector) 204.

Next, an example of the operation of the determination circuit 303 will be described with reference to FIG. In the graph of FIG. 4, the horizontal axis indicates the detection level, and the vertical axis indicates the number of filter stages (area). For explanation,
The relationship between the detection level and the number of filter stages (regions) is shown by a straight line. .., Th (N−1) are assumed to be in a relationship of Th1 <Th2 <... <Th (N−1). In the area a, the filter is used in N stages, and in the area b, the filter is used in (N-1) stages. The same applies hereinafter, and the filter is used in one stage in the area c.
When the detected level r satisfies Th1 <r <Th2, the number of filter stages belongs to the region b. From this, the determination circuit 303 determines that (N-1) stages are necessary, and outputs a control signal indicating the result to the register output switching means (selector) 204 in FIG.

As described above, in the above embodiment, when it is determined that the average reception level is low, the number of stages of the decimation filter 103 is increased, and when it is determined that the average reception level is high, the decimation filter 103 is increased.
Are controlled so as to shorten the number of stages. Therefore, the size of the decimation filter 103 can be reduced under the condition that the average reception level is large. Also, by controlling in this way, the decimation filter 10
3 can be controlled so that the number of bits of the output signal is always constant regardless of the level. Thus, simplification of the signal processing unit 106 at the subsequent stage of the decimation filter 103 can be expected.

Further, instead of using a configuration in which the number of stages of the decimation filter 103 can be varied as in the above-described embodiment, a coefficient multiplier is used to change the impulse response characteristic of the decimation filter 103 by changing the coefficient. , The response time can be changed.

FIG. 5 shows a specific configuration example of the decimation filter 103 having such a configuration. As shown in the figure, delay circuits 501, 502, 503, 504
Multiplier 511 provided between the adder 520 and the
Each coefficient k1, k2, k3, k of 512, 513, 514
4 is stored in the coefficient table 530. The coefficient table 530 stores coefficients k1, k
2, k3 and k4 are stored. Then, it is assumed that the determination circuit 303 in FIG. 3 determines the stage of the average reception level,
According to a control signal indicating a result of the determination by the determination circuit 303,
The coefficients k1, k2, k3, and k4 are read from the coefficient table 530 according to the average reception level, and the coefficient multipliers 511,
Each coefficient k1, k2, k3, k of 512, 513, 514
Set 4. When the average reception level is high, each coefficient k is set so that the decimation filter 103 has a steep impulse response characteristic as shown in FIG.
1, k2, k3, and k4 are set, and when the average reception level is low, the decimation filter 103
Each of the coefficients k1, k2, k3,
Control is performed to set k4. Thus, the response time of the decimation filter 103 can be changed according to the reception level. With such a configuration, the decimation filter 103 and the signal processing unit 106 at the subsequent stage can be reduced in size and simplified.

In the above description, the case where the decimation filter 103 is an FIR filter has been described. However, even when the decimation filter 103 is an IIR filter, a configuration in which the number of stages is variable or another type in which the impulse response characteristic is variable is used. It can be configured.

[0030]

As described above, according to the present invention, the response time of the decimation filter is controlled by the reception level. Therefore, even when the present invention is applied to a mobile communication in which the level fluctuates, the decimation filter and the subsequent signal processing are performed. It is possible to reduce the size of the unit and reduce power consumption.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing a specific configuration example of a decimation filter in the embodiment shown in FIG.

FIG. 3 is a block diagram showing a specific configuration example of a level detection / judgment circuit in the embodiment shown in FIG. 1;

FIG. 4 is a diagram for explaining the operation of the level detection / judgment circuit shown in FIG. 3;

FIG. 5 is a block diagram showing another specific configuration example of the decimation filter in the embodiment shown in FIG. 1;

FIG. 6 is a diagram showing an impulse response characteristic for explaining the operation of the decimation filter shown in FIG. 5;

[Explanation of symbols]

 Reference Signs List 100 quadrature demodulation unit 101 LPF unit 102 △ modulation (or △ Σ modulation) unit 103 decimation filter 104 latch 105 level detection / judgment circuit 106 signal processing unit 201 first stage register 202 2nd stage Third register 203: Third stage register 204: Register output switching means (selector) 301: Level detection circuit 302 ... Level comparison circuit 303: Judgment circuit 501, 502, 503, 504 ... Delay circuit 511, 512, 513, 514 ... coefficient multiplier 520 ... adder 530 ... coefficient table

 ──────────────────────────────────────────────────続 き Continued on front page F term (reference) 5J022 BA06 CA07 CA10 CB06 CC03 CE08 CF08 CG01 5J064 AA04 BA03 BB06 BC04 BC06 BC08 BC09 BC12 BC15 BC25 BD02 5K004 AA05 FA05 FG02 FH01 FH06 FJ06

Claims (2)

[Claims] 1. A frequency conversion means for converting a signal in a radio frequency band to a predetermined frequency, a band limiting means for limiting a band of an output signal of the frequency conversion means to a desired band, and a frequency component higher than the desired band. Analog-to-digital conversion means for sampling an output signal of the band-limiting means using a clock signal having the signal, and converting the output signal to a digital code; and an output signal of the analog-to-digital conversion means as an input signal. Decimation filter means for attenuating, sampling means for taking an output signal of the decimation filter means as an input signal, and sampling the input signal with a clock signal having a frequency component lower than the clock frequency used in the analog-to-digital conversion means, A level for detecting the reception level of a predetermined signal And Le detecting means, based on the output information of the level detection means, level control circuit, characterized in that it includes a means for changing the response time of the decimation filter means. 2. The level control circuit according to claim 1, wherein said analog-to-digital conversion means employs △ modulation or △ Σ modulation.