JP2000091951A - Digital matched filter, receiver and communication system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a digital matched filter whose circuit scale is reduced while maintaining its detection accuracy. SOLUTION: A signal is fetched from odd number order storage stages 32-1, 32-3, 32-5, 32-7 of a reception register 20 and a switch 36 is used to extract a signal selectively from an odd number order of storage stages 34-1, 34-3, 34-5, 34-7 or an even number order of storage stages 34-2, 34-4, 34-6, 34-8 of a spread code register 22 and the signals are multiplied by multipliers 30-1-30-4. Then adder 28 sums the results of multiplication to calculate a partial correlation value. In this case, the switch 36 is switched for each 1/2-chip clock by a switching control signal outputted from a control section 38. Then an adder 26 outputs a correlation value for each one-chip clock, based on the storage contents of a partial correlation register 24.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital matched filter, a receiver, and a communication system, and more particularly, to a digital matched filter capable of reducing the circuit scale while maintaining detection accuracy, and a receiver and communication using the same. About the system.

[0002]

2. Description of the Related Art In a communication system employing a direct spread spectrum communication system, an original signal is spread by a pseudo random code sequence (spreading code) on a transmitter side, and the signal (received code sequence) is spread on a receiver side. The original signal is extracted by despreading. In the process on the receiver side, a digital matched filter is used to improve the detection speed and accuracy,
Thereby, the correlation value between the received code string and the spread code is sequentially calculated for each one-chip clock.

FIG. 7 is a diagram showing the configuration of a digital matched filter according to the prior art. The digital matched filter 100 shown in FIG. 1 is provided with a reception register 102 to which a reception code string is input, and a storage stage for storing the spreading code and the same number of chips (here, the spreading factor is 8). It is included. In this reception register 102,
The received code string in which each chip is 1 or -1 is sequentially input, and the contents of each storage stage are shifted to the right front stage side in the figure every one chip clock. It should be noted that the numbers written in the frames indicating the respective storage stages of the reception register shown in FIG. 3 are for identifying the codes currently stored in the respective storage stages, and in FIG. This shows that the code of the eye is stored, and the code of the eighth chip is stored in the final stage. And 1
After the chip clock, the code of the second chip is stored in the first storage stage, and the code of the ninth chip (not shown) is stored in the last storage stage.

The digital matched filter 100 shown in FIG. 1 is provided with a spreading code register 104 to which a spreading code composed of a combination of eight chips having a value of 1 or -1 is input. This spreading code register 104
Contains eight registers, and each chip of the spread code is stored in order. Further, the digital matched filter 100 includes eight multipliers 106-1.
The contents of each register included in the spread code register 104 are input to each multiplier 106, and the contents of each storage stage of the reception register 102 are also input to each multiplier 106. It has become.

[0005] The result of the multiplication in each multiplier 106 is input to the adder 108, and the 8
A correlation value between a code for a chip (hereinafter, referred to as a “received code”) and a spread code is determined. For example, when the received code and the spread code completely match, adder 108 outputs 8 as the correlation value. When the received code is a code obtained by inverting the spread code, −8 is output from the adder 108 as a correlation value.

[0006] The correlation value output from the adder 108 is output as it is to the outside and used for subsequent processing, and is also input to an absolute value calculation circuit 110, where the absolute value of the correlation value, that is, An absolute correlation value is calculated. This correlation absolute value is also output to the outside in the same format and used for subsequent processing, and is also input to the comparator 112. On the other hand, the threshold value TH is input to the comparator 112, and the absolute value of the correlation is compared with the threshold value. Then, when the correlation absolute value exceeds the threshold value TH, the detection pulse DET is output.

Thus, in the conventional digital matched filter 100 shown in FIG. 1, a correlation value is calculated for each one-chip clock, and it is checked whether or not the absolute value of the correlation exceeds a threshold value. Then, when the correlation absolute value exceeds the threshold, a detection pulse is output. For this reason, in the subsequent processing, by monitoring the output timing of the detection pulse, it is possible to obtain the timing required when decoding the received code string or the like.

[0008]

However, in the conventional digital matched filter 100 described above, the multiplier 10
6 is required to be equal to the number of chips of the spreading code, and if the number of chips of the spreading code is increased, there is a problem that the circuit scale increases. That is, although the multiplier 106 is generally a large-scale circuit, if the multiplier 106 is included in a large number of circuits, the circuit scale increases. Therefore, the multiplier 1
06 to reduce the number of digital matched filters 100
It is desirable to reduce the circuit scale.

In this regard, in the digital matched filter according to Japanese Patent Application Laid-Open No. 7-58669, a spread code is divided into a plurality of partial spread codes, and a correlation value between each partial code and a received code sequence is calculated. I have. For this reason, according to the digital matched filter disclosed in the publication, the number of codes to be calculated in one correlation value calculation process can be reduced, and as a result, the number of multipliers in the circuit can be reduced. .

However, in the digital matched filter according to the above publication, if a correlation can be obtained with the received code for the leading portion of the partial spread codes, then the correlation value of the remaining partial spread codes with the received code is delayed by several chip clocks. Is calculated. For this reason, until the correlation value is calculated for the remaining partial spread codes, the correlation value cannot be calculated for the partial spread code corresponding to the leading portion, and the correlation value cannot be calculated for each one-chip clock timing. For this reason, the digital matched filter according to the above publication cannot always detect the timing at which the correlation between the spread code and the received code string becomes high, and the detection accuracy decreases.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to provide a digital matched filter capable of reducing the circuit scale while maintaining detection accuracy, and a receiver and a communication system using the same. To provide.

[0012]

(1) In order to solve the above problems, a digital matched filter according to the present invention comprises:
In a digital matched filter that sequentially calculates a correlation value between a reception code updated every one-chip clock and a spreading code for each one-chip clock, one or a plurality of the correlation values calculated from the present time onward are respectively calculated. A partial correlation value calculating means for calculating a total of N partial correlation values divided into N partial sums per one chip clock (N ≧ 2); and a partial correlation value calculated by the partial correlation value calculating means. And a correlation value calculating means for sequentially calculating a correlation value between the received code and the spread code for each one-chip clock. Further, the receiver and the communication system according to the present invention include such a digital matched filter.

According to the present invention, the correlation value between the received code and the spread code is obtained as the sum of the partial sums. That is, the correlation value is the sum of the correlation values between the received code and the spread code for each chip. In the present invention, focusing on this fact, the correlation value between the received code and the spread code is set to N pieces. It is calculated as a partial sum, that is, a sum of partial correlation values. Then, a total of N partial correlation values are calculated during one chip clock, the partial correlation values already calculated by the correlation value calculating means are combined, and the correlation value between the received code and the spread code is 1 It is calculated sequentially for each chip clock.

Here, the partial correlation value in the present invention is:
Not only the partial correlation value for a continuous part of the received code,
This is meant to include all the partial sums of correlation values, such as partial correlation values relating to discrete portions in the received code. In this specification, “chip” means a processing unit of a reception code or a spreading code, and usually means each bit. Further, “chip clock timing” means the update timing of the received code.

(2) A digital matched filter according to the present invention is a digital matched filter which sequentially calculates a correlation value between a reception code updated every one chip clock and a spread code every one chip clock. , A partial correlation value calculation in which all correlation values between a part of the received code and each of a plurality of partial spread codes obtained by dividing the spread code are calculated as a partial correlation value during one chip clock. Means, a partial correlation value storage means for storing a partial correlation value calculated by the partial correlation value calculation means, based on the partial correlation value stored by the partial correlation value storage means, the received code and the spread code And a correlation value calculating means for sequentially calculating a correlation value between 1 and 1 for each one-chip clock. Further, the receiver and the communication system according to the present invention include such a digital matched filter.

According to the present invention, the spreading code is divided into a plurality of parts to form partial spreading codes. Then, the correlation values between a part of the received code and each of the partial spreading codes are all calculated as a partial correlation value during one chip clock. The calculated partial correlation value is temporarily stored, and a correlation value between the received code and the spread code is calculated for each one-chip clock based on the stored content.

Here, the part of the received code in the present invention is not limited to a continuous part of the received code, but also includes a discrete part in the received code.

In one aspect of the present invention, the partial correlation value calculation means includes a first storage means for storing a part of the received code, and a plurality of second storage means for storing each of a plurality of partial spread codes. Means, multiplying means for multiplying the storage content of one of the second storage means and the storage content of the first storage means, and the second storage means to be operated on by the multiplication means is provided with one chip clock. Switching means for sequentially switching between them. According to this aspect, the partial correlation value can be calculated with a relatively simple configuration.

(3) A digital matched filter according to the present invention is a digital matched filter which sequentially calculates a correlation value between a reception code updated every one chip clock and a spreading code every one chip clock. , Each of a plurality of partial reception codes obtained by dividing the reception code,
A partial correlation value calculating means for calculating each correlation value between the partial spreading codes obtained by dividing the spreading code and a corresponding partial spreading code as a partial correlation value during one chip clock; A partial correlation value storage means for storing a partial correlation value calculated by the means, and a correlation value between the received code and the spread code based on the partial correlation value stored by the partial correlation value storage means for one chip. And a correlation value calculating means for sequentially calculating for each clock. Further, the receiver and the communication system according to the present invention include such a digital matched filter.

According to the present invention, the received code is divided into a plurality of codes to form partial received codes. Further, the spreading code is also divided into a plurality of pieces and used as partial spreading codes. And all the partial received codes,
Correlation values between the corresponding partial spreading codes are calculated as partial correlation values during one chip clock. Then, a correlation value between the received code and the spread code is calculated for each one-chip clock based on the partial correlation values.

Here, in the present invention, the partial reception code is not limited to a continuous part of the reception code. Similarly, the partial spreading code is not limited to a continuous part of the spreading code.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a diagram showing an overall configuration of a communication system according to an embodiment of the present invention. As shown in the figure,
This communication system adopts a spread spectrum communication system, and includes a spread spectrum unit 10 and a modulation unit 12 on the transmitter side. On the other hand, the receiver includes a demodulation unit 14, a digital matched filter 16, and a determination unit 18. Hereinafter, a case where spread spectrum communication with a spreading factor of 8 is performed between the transmitter and the receiver will be described.

In such a configuration, the transmission data is first input to the spread spectrum unit 10, where the transmission data is multiplied by a spreading code at a higher bit rate than the transmission data to generate a transmission code sequence. The transmission code string generated by the spread spectrum unit 10 is then input to the modulation unit 12, where the PS
After a predetermined modulation such as K (phase shift keying) is performed, the signal is transmitted to a receiver via an antenna. On the other hand, the receiver receives such a signal, demodulates it in the demodulation unit 14, and extracts a received code string subjected to spread spectrum. The received code sequence is input to the digital matched filter 16, where the spread code used in the spread spectrum unit 10 and the received code are sequentially compared for each one-chip clock, and the correlation value between the two is output. Then, using the timing at which the spread code and the received code match, the determination unit 18 extracts the original signal from the received code sequence. Among the above communication systems, the present invention particularly has a digital matched filter 16 which is one of the configurations on the receiver side.

FIG. 2 is a diagram showing a configuration of the digital matched filter 16 according to the embodiment of the present invention. In the figure, the digital matched filter 16 has a reception register 20 having storage stages 32-1 to 32-8, and a spread code register 22 having storage stages 34-1 to 34-8. Then, in the reception register 20, the storage stages 32-1, 32-3, 32-5, 32-
7 are taken out of the memory 30 and the respective multipliers 30-1
To 30-4. Note that, in the figure, the storage stage 32-8 of the reception register 20 can be omitted, and the reception register 20 may be constituted by a total of seven storage stages.

On the other hand, the storage contents of the storage stages 34-1 and 34-2 of the spreading code register 22 are taken out and inputted to the switch 36-1, and the storage stage 34
-1 or 34-2 is stored in switch 3
6-1 and output to the multiplier 30-1. Similarly, the storage stages 34-n, 34-
The stored content of (n + 1) is determined by the switch 36-((n + 1) /
2), and one of the contents is input to the multiplier 30
− ((N + 1) / 2) (n = 1, 3, 5, 7). Here, the switches 36-1 to 36-1
A switching control signal is input to the control unit 38-4 from the control unit 38, and the switches 36-1 are received by the switching control signal.
To 36-4 are selected as one of two input signals. For example, when a high-level switching control signal is transmitted from the control unit 38, the switch 36
-1 to 36-4 select the inputs from the storage stages 34-1, 34-3, 34-5, and 34-7 of the spreading code register 22, respectively. If it is output, the switch 36-1
36-4 are the storage stages 3 of the spreading code register 22.
4-2, 34-4, 34-6, and 34-8 are selected, respectively. When any one of the inputs is selected based on the switching control signal from the control unit 38 in this way, the input is selected from the contents of the reception register 20 and the multiplier 30-.
1 to 30-4, and the result of the multiplication is added to the adder 28.
Is input to That is, in the adder 28, the reception code stored in the reception register 20 and the spreading code
Is calculated as the partial correlation value corresponding to the partial sum of the correlation value with the spreading code stored in.

For example, a first chip (first code: first bit) is stored in storage stage 32-1 of reception register 20, and an eighth chip (eighth code: eighth bit) is stored in storage stage 32-8. ) Is stored in the control unit 3
If a high-level switching control signal is transmitted from 8,
The adder 28 calculates “1A + 3C + 5E + 7G”.

Here, the code of the n-th chip in the received code sequence is simply referred to as “n”. The eight chips constituting the spreading code are described as “A” to “H” in order from the top. The above-mentioned “1A + 3C + 5E + 7G” is one of partial sums of correlation values when the first chip is stored in the storage stage 32-1 of the reception register 20.
"1" x "A" + "3" x "C" + "5" x "E" +
“7” × “G” is abbreviated. In the following, simply P
_{Recorded as 1A} . Similarly, “n” × “A” + “n + 2” ×
“C” + “N + 4” × “E” + “n + 6” × “G” is simply written as P _nA, and “n” × “B” + “n + 2” × “D” +
“N + 4” × “F” + “n + 6” × “H” is simply referred to as P _nB .

The signal input to the reception register 20 is not limited to one bit. That is, the reception register 20
May store not only one bit of information but also a plurality of bits of information. Similarly, the spreading code register 22 may hold not only 1-bit information but also a plurality of bits of information.

The partial correlation value calculated by the adder 28 is then input to the partial correlation value register 24. The partial correlation value register 24 has a total of four storage stages 44-1 to 44-4.
Here, the storage contents of each storage stage 44 are sequentially shifted by the FIFO method. Then, in the partial correlation value register 24, the storage content of the storage stage 44-1 and the storage content of the storage stage 44-4 are taken out, and the output is input to the adder 26. The adder 26 adds the outputs from the storage stages 44-1 and 44-4, and outputs the addition result as a correlation value C _n 'for each one-chip clock. Note that the subscript n 'indicates the chip clock timing.

Further, the output of the adder 26 is also inputted to the absolute value calculating section 40, where the correlation value C
The absolute value of _n 'can be obtained. This absolute value is output to the outside as a correlation absolute value, and is also input to the comparator 42. Comparator 4
2 is also input with a threshold value TH. The comparator 42 compares the absolute value of the correlation with the threshold value TH, and when the absolute value of the correlation value is larger than the threshold value TH, the detection pulse DE is output.
T is output.

In the above configuration, the reception register 20 updates the reception code stored in each stage for each one-chip clock.
8, a switch control signal is sent out every 1/2 chip clock, and the switches 36-1 to 36-4 switch their input every 1/2 chip clock. Further, the adder 28 calculates a partial correlation value P _X every half chip clock, and these are input to the partial correlation value register 24. The subscript X represents “nA” or “nB” added to the above P _nA or P _nB (n = 1, 2,...).
・). In the partial correlation value register 24, the content of each storage stage 44 is sequentially updated every 1/2 chip clock. Then, the adder 26 adds the contents of the storage stages 44-1 and 44-4 of the partial correlation value register 24 for each one-chip clock, and outputs the result as a correlation value C _n '.

FIG. 3 shows this digital matched filter 1.
6 is a diagram illustrating the operation of FIG. In FIG.
, The reception register 20 and the spread code register 22
Are stored, and the stored contents of each register for each half chip clock are shown in order from the top. That is, the spreading code register 2 shown in each frame of the column 21a
2 are A to H in order from the top, while the reception register 20 stores the first to eighth chips in the time up to the first one-chip clock.
Thereafter, a state in which the second to ninth chips are stored and a state in which the third to tenth chips are stored continue. Thereafter, similarly, the contents stored in the reception register 20 are shifted every chip clock. Column 21a
, The arrow between the receiving register 20 and the spreading code register 22 indicates the switching direction of the switch 36, and the contents of the storage stages indicated by both ends of the arrow are multiplied by the multiplier 30. Is shown. For example, in the uppermost frame of the same field 21a, the reception register 20
Storage stages 32-1, 32-3, 32-5, 32-
7 is stored in the storage stage 34- of the spread code register 22.
It is shown that they are multiplied by the storage contents of 1, 34-3, 34-5, and 34-7, respectively. In the second frame from the top, the storage stage 32 of the reception register 20
-1, 32-3, 32-5, 32-7 are stored in the storage stages 34-2, 34-4,
34-6, 34-8, respectively.

Next, a column 21b shows the contents of the switching control signal output from the control section 38 in order from the top for every 1/2 chip clock. That is, when the character indicated in this column 21b is "H", the switching control signal is at the high level, and the switches 36-1 to 36-4 store the storage stages 34-1 and 34- of the spreading code register 22.
3, 34-5 and 34-7 are respectively selected. On the other hand, when it is "L", the switching control signal is at a low level, and the switches 36-1 to 36-4 are switched.
In the storage stage 34- of the spread code register 22,
2, 4-4, 34-6, and 34-8 are respectively selected.

A column 21c shows the latest code (bit: chip) input to the reception register 20, and in the figure, the eighth chip, the ninth chip, and the tenth chip are the reception registers in order from the top. 20, the contents of each storage stage of the reception register 20 are sequentially updated.

Further, an adder 28 adds 1/2 to the column 21d.
The content of the partial correlation value calculated for each chip clock is shown, and each partial correlation value calculated by the register storage content shown in each frame of the column 21a is shown for each 1/2 chip clock. .

The column 21e in the figure shows the contents of the correlation value calculated for each one-chip clock. For example, in the fourth frame from the top of the figure, the partial correlation value P _1A calculated first and the partial correlation value P _2B calculated one chip clock after that are added, and the correlation value C1 is output. Has been shown to be.

That is, according to the digital matched filter 16 according to the present embodiment, the switch 36 is switched at a clock speed twice as fast as the timing of the chip clock at which the reception register 20 is shifted, and a part of the reception code is changed. The partial correlation value between each part of the spread code and each part is sequentially calculated, and the partial correlation value is temporarily stored in the partial correlation value register 24. Then, the adder 26 calculates the necessary correlation value for each one-chip clock by adding the contents stored in the partial correlation value register 24. According to such a configuration, the correlation value is calculated for each of the two partial sums, so that the multiplier 3
The number of zeros can be reduced by half, and the circuit size of the digital matched filter 16 can be significantly reduced. Further, since a plurality of partial correlation values between a part of the received code and a part of the spread code are calculated for each one-chip clock, a blank period of detection occurs as in the digital matched filter according to the related art. And the detection accuracy can be maintained.

The digital matched filter 16 according to the embodiment described above can be variously modified. For example, in the above description, the discrete storage stage 32 of the reception register 20 is used as the input of the multiplier 30.
-1,32-3,32-5,32-7 were adopted,
The multiplier 30 may multiply the storage contents of successive storage stages such as the first four stages or the second four stages. Further, in the above description, two of the storage stages 34 of the spreading code register 22 are sequentially switched by the switch 36, but the spreading code is further divided into a large number,
A partial correlation value may be calculated for each of the divided spreading codes.

FIG. 4 is a diagram showing a configuration of a digital matched filter according to such a modification. The digital matched filter 16a shown in the figure functions as a substitute for the digital matched filter 16 in the communication system shown in FIG. 1, and is characterized in that a multiplexer 54 is provided instead of the switch 36. In this configuration, the storage stage 48-
The contents stored in the storage stages 48-1 and 48-5 among the data stored in the storage stages 48-1 and 48-5 are input to the multipliers 56-1 and 56-2, respectively, while the multiplexer 54-1 connected to the spreading code register 52 is provided. , 54-2 are also output to multipliers 56-1,
56-2. The multiplexer 54-1 has a spread code register 52 as its input.
The contents of the storage stages 50-1 to 50-8 of the spreading code register 52 are input to the multiplexer 54-2. A switching control signal is output from the control unit 47 to the multiplexers 54-1 and 54-2, and the input of the multiplexer 54 is switched every quarter chip clock by the switching control signal. . That is, the switching control signal is a 2-bit signal, whereby the input of the multiplexer 54-1 is applied to the storage stages 50-1 to 50- of the spreading code register 52.
4 and are sequentially switched every quarter chip clock,
On the other hand, the input of the multiplexer 54-2 is １ ／ between the storage stages 50-5 to 50-8 of the spreading code register 52.
It can be switched sequentially for each chip clock.

Then, the multiplier 56-1 multiplies the storage content of the storage stage 48-1 of the reception register 46 by the output of the multiplexer 54-1 and inputs the result of the multiplication to the adder 58. In the multiplier 56-2, the storage content of the storage stage 48-5 of the reception register 46 is multiplied by the output from the multiplexer 54-2, and the result of the multiplication is input to the adder 58. The adder 58 adds the output from the multiplier 56 every １ ／ chip clock, and sequentially inputs the addition result to the partial correlation value register 60. The partial correlation value register 60 has a total of 16 storage stages, and the contents stored in the first, sixth, eleventh, and sixteenth storage stages are taken out by the adder 62. The adder 62 can add up the partial correlation values stored in these storage stages, and as a result, the correlation value between the received code and the spread code is output every one chip clock. ing. The correlation value output from the adder 62 in this manner is similar to the digital matched filter 16 already shown in FIG.
The absolute value of the correlation value, that is, the absolute value of the correlation value is calculated. The correlation absolute value is output to the outside and the comparator 6
6, and is compared with the threshold value TH similarly input to the comparator 66. When the correlation absolute value is larger than the threshold value TH, the detection pulse DET is output.

According to the digital matched filter 16a having such a configuration, by employing the multiplexer 54, the correlation value can be further divided into a large number of partial sums, and the number of the multipliers 56 can be further reduced. Thus, according to this modification, it is possible to further reduce the circuit scale of a digital-matched filter, and furthermore, a communication-type receiver employing a spread-spectrum method. In FIG. 4, the storage stages 48-6 to 48-8 of the reception register 46 are used.
May be omitted, and the reception register 46 may be constituted by a total of five storage stages.

Embodiment 2 Next, a digital matched filter according to Embodiment 2 of the present invention will be described.
The digital matched filter described below can be used in place of the digital matched filter 16 in FIG.

FIG. 5 is a diagram showing a configuration of a digital matched filter according to Embodiment 2 of the present invention. The digital matched filter 16b shown in FIG.
The receiving register 70 includes storage stages 68-1 to 68-8 equal to the storage stages 76-1 to 76-8 equal to the spreading factor.
And a spread code register 78 including a spread code 76-8. In the former, a received code sequence for eight chips is stored as a received code for which a correlation value with the spread code is calculated. Further, the reception register 70 is provided with a switch 72-1 for inputting the contents of the storage stages 68-1 and 68-2, and one of the storage contents selected by the switch 72-1 is multiplied. Container 74
-1 is input. On the other hand, the multiplier 74-1 has a storage stage 76-1 of the spreading code register 78.
The multiplier 74-1 stores the content stored in the storage stage 76-1 of the spreading code register 78 and the content stored in one of the storage stages 68-1 or 68-2 of the reception register 70. , And the result is input to the adder 82. Similarly, the storage stage 7 of the spreading code register 78 is provided in the multiplier 74-i.
6- (2i-1) is stored ("-" in parentheses means subtraction, and so on). The storage stage 68- (2i-
1) and 68-2i are selected by the switch 72-i, and the contents of the selected storage stage 68 are input to the multiplier 74-i. Then, the multiplier 74-i multiplies them, and inputs the result to an adder 82 (i = 2, 3,
4). Here, inputs of the eight storage stages 68 of the reception register 70 are sequentially enabled by a control device (not shown). That is, the reception code string is input to the storage stage 68 of the reception register 70 in parallel, and the chip of the latest reception code is stored in any one of the storage stages 68 whose writing is enabled by a control device (not shown). Is stored. Specifically, storage stages 68-1 to 68
The writing is enabled in this order for every one chip clock in the order of -8, and then the writing of the storage stage 68-1 is enabled again. Further, a switch control signal is input to the switch 72 from the control unit 80. When the switch control signal is at a high level, the reception register 70
Of the storage stages 68-1, 68-3, 68-5, 6
The memory contents of 8-7 are selected by the switch 72, while
When the switching control signal sent from the control unit 80 is at a low level, the storage stage 68-
The stored contents of 2, 68-4, 68-6, 68-8 are selected by the switch 72. This control unit 8
The level of the switching control signal transmitted from 0 is switched every half chip clock.

On the other hand, the spreading code register 78 is a shift register having eight storage stages 76 equal to the spreading factor, and is connected to the first storage stage 76-1 and the last storage stage 76-8, and is connected every one chip clock. The stored contents are sequentially circulated. That is, at first, the chip “A” of the spreading code is input to the storage stage 76-1, but after one chip clock, the chip “A” is stored in the storage stage 76-2, and
6-1 stores a chip "H". Thereafter, the storage position of the chip “A” circulates similarly.

The result of the multiplication by the multiplier 74 is input to an adder 82, which adds them to each other and inputs the result to a partial correlation value register 84 as a partial correlation value. The partial correlation value register 84 has two storage stages 86-1 and 86-8.
6-2, and both the stored contents are output to the adder 88. The adder 88 adds the stored contents of the two storage stages 86-1 and 86-2 and outputs the sum as a correlation value, and inputs the correlation value to the absolute value calculation unit 90. The absolute value calculation unit 90 calculates the absolute value of the correlation value and outputs it to the outside,
It is input to the comparator 92. On the other hand, the threshold value TH is input to the comparator 92, and when the correlation absolute value becomes larger than the threshold value TH, the detection pulse DET is externally output.

FIG. 6 is a diagram for explaining the operation of the digital matched filter 16b according to the second embodiment of the present invention. In the figure, the contents of the reception register 70 and the spreading code register 78 are schematically represented in the respective frames of the column 71a in order from the top. In each frame, an arrow between the reception register 70 and the spreading code register 78 indicates the switching direction of the switch 72. That is,
For example, in the register storage contents shown in the uppermost frame of the same column 71a, the storage stages 68-1 and 68 of the reception register are stored.
8-3, 68-5, and 68-7 are selected by the switch 72, respectively, and are multiplied by the storage stages 76-1, 76-3, 76-5, and 76-7 of the spreading code register 78. It is shown. That is, at this time, the control unit 8
The switching control signal output from 0 is at a high level as shown in a column 71b. On the other hand, in the register storage contents shown in the second frame from the top of the column 71a, the storage stages 68-2, 68-4, 68 of the reception register 70
-6 and 68-8 are selected by the switch 72, respectively, and the storage stages 76-1 and 76-7 of the spread code register 78 are selected.
6-3, 76-5, and 76-7 are shown to be multiplied. At this time, the switching control signal output from the control unit 80 is at the low level as shown in the corresponding frame of the column 71b.

The column 71c contains the spreading code register 7
8 shows how the stored contents are circulated for each one-chip clock. The number described in each box of this column 71c indicates the position of "A" which is the first chip of the spread code. For example, when 2 is written in the frame in the column 71c, the spreading code chip “A” is stored in the storage stage 76-2 in the spreading code register 78. Further, a column 71d indicates the latest reception code stored in the reception register 70. This column 71d shows how a chip of a new reception code is input for each one-chip clock.

The column 71e shows the partial correlation value calculated for each half chip clock. For example, the partial correlation value P _1A (= 1A + 3C + 5E) in the uppermost frame in FIG.
+ 7G) is output at that timing. The contents of the partial correlation value correspond to the contents stored in the register shown in the column 71a. Further, column 71f
Represents a correlation value output from the adder 62 for each one-chip clock. For example, in FIG.
At 1e, it is output by adding the partial correlation values P _2A and P _3B . Similarly, the correlation value C3 is the partial correlation value P _4B
And the partial correlation value _P3A .

In the figure, the switching control signal output from the control unit 80 is switched in the order of H and L every 1/2 chip clock, while the storage content of the spreading code register 78 is shifted by This cycle is performed for each one-chip clock used at the time.
It is shifted from the write timing of 0 by チ ッ プ chip clock. For example, the reception register 70 and the spreading code register 78 are driven by using a common clock, and the writing of the reception register 70 is performed at the rising of the clock, while the circulation of the spreading code register 78 is performed at the rising of the same clock. It is performed at the fall.

In this way, every other chip (storage stages 68-1, 68-3, 68-5, 68) from the beginning of the received code until the received code is updated.
-7) and the spreading code chips A, C, E, and G are multiplied to calculate a partial correlation value.
Every other chip from the second chip from the top of the received code (storage stages 68-2, 68-4, 68-6,
68-8) is multiplied by the spreading code chips B, D, F, and H to calculate a partial correlation value. Therefore, by adding these partial correlation values in the adder 88, it is possible to calculate a necessary correlation value for each one-chip clock.

Further, in the digital matched filter 16b according to the present embodiment, the switch 72 is provided so that the contents stored in the storage stage of the reception register 70 are taken out one by one, so that the number of the multipliers 74 is halved. Thus, the circuit size of the digital matched filter 16b, and thus the receiver, can be greatly reduced.

[0053]

As described above, according to the present invention,
By using a relatively small number of multipliers for calculating a partial correlation value, correlation values can be sequentially calculated for each one-chip clock, thereby reducing the circuit size of a digital matched filter and a receiver using the same. Can be.

Further, since a plurality of partial correlation values are always obtained for each one-chip clock, it is possible to avoid a blank period of detection from occurring as in the digital matched filter according to the prior art. , Detection accuracy can be maintained.

[Brief description of the drawings]

FIG. 1 is a diagram showing an overall configuration of a communication system according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a configuration of a digital matched filter according to the first embodiment of the present invention.

FIG. 3 is a diagram illustrating an operation of the digital matched filter according to the first embodiment of the present invention.

FIG. 4 is a diagram showing a configuration of a modified example of the digital matched filter according to the first embodiment of the present invention.

FIG. 5 is a diagram illustrating a configuration of a digital matched filter according to a second embodiment of the present invention.

FIG. 6 is a diagram illustrating an operation of a digital matched filter according to a second embodiment of the present invention.

FIG. 7 is a diagram illustrating a configuration of a digital matched filter according to the related art.

[Explanation of symbols]

10 spread spectrum section, 12 modulation section, 14 demodulation section, 16 digital matched filter, 18 decision section,
20 reception register, 22 spreading code register, 24
Partial correlation value register, 26, 28 adder, 30 multiplier, 36 switch, 38 control unit, 40 absolute value calculation unit, 42 comparator, 54 multiplexer.

Claims (6)

[Claims] 1. A digital matched filter for sequentially calculating a correlation value between a received code updated every one-chip clock and a spread code for each one-chip clock, wherein one or more calculated values are calculated after the present time. A partial correlation value calculating means for calculating a total of N partial correlation values for each chip clock by dividing the correlation value into N partial sums, (N ≧
2) The correlation value between the received code and the spread code is set to 1 based on the partial correlation value calculated by the partial correlation value calculation means.
A digital matched filter comprising: a correlation value calculating means for sequentially calculating for each chip clock. 2. A digital matched filter for sequentially calculating a correlation value between a reception code updated every one-chip clock and a spreading code for each one-chip clock, comprising: a part of the reception code; A partial correlation value calculating means for calculating each correlation value between each of the plurality of partial spreading codes obtained by dividing the code as a partial correlation value during one chip clock; and calculating the partial correlation value by the partial correlation value calculating means. A partial correlation value storage unit for storing a partial correlation value to be calculated, and a correlation value between the received code and the spread code is set to 1 based on the partial correlation value stored by the partial correlation value storage unit.
A digital matched filter comprising: a correlation value calculating means for sequentially calculating for each chip clock. 3. A digital matched filter for sequentially calculating a correlation value between a reception code updated every one-chip clock and a spreading code for each one-chip clock, wherein a plurality of divisions of the reception code are provided. A partial correlation value calculating means for calculating each correlation value between each of the partial reception codes and a corresponding partial spread code obtained by dividing the spread code as a partial correlation value during one chip clock. A partial correlation value storage unit that stores a partial correlation value calculated by the partial correlation value calculation unit; and a partial correlation value storage unit that stores the partial correlation value calculated by the partial correlation value storage unit. The correlation value between 1
A digital matched filter comprising: a correlation value calculating means for sequentially calculating for each chip clock. 4. The digital matched filter according to claim 2, wherein said partial correlation value calculating means stores said plurality of partial spreading codes, and said first storing means stores a part of said received code. A second storage unit, a multiplication unit that multiplies a storage content of one of the second storage units by a storage content of the first storage unit, and a second storage unit that is an operation target of the multiplication unit. Switching means for sequentially switching during one chip clock; and a digital matched filter. 5. A receiver comprising the digital matched filter according to claim 1. 6. A communication system comprising the receiver according to claim 5.