JP2000091848A - Integrated mixer circuit - Google Patents

Integrated mixer circuit

Info

Publication number
JP2000091848A
JP2000091848A JP10262685A JP26268598A JP2000091848A JP 2000091848 A JP2000091848 A JP 2000091848A JP 10262685 A JP10262685 A JP 10262685A JP 26268598 A JP26268598 A JP 26268598A JP 2000091848 A JP2000091848 A JP 2000091848A
Authority
JP
Japan
Prior art keywords
terminal
mixer circuit
circuit
mixer
transistors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10262685A
Other languages
Japanese (ja)
Other versions
JP3750890B2 (en
Inventor
Ryoichi Takano
亮一 高野
Satoshi Tanaka
聡 田中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP26268598A priority Critical patent/JP3750890B2/en
Publication of JP2000091848A publication Critical patent/JP2000091848A/en
Application granted granted Critical
Publication of JP3750890B2 publication Critical patent/JP3750890B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To realize a method for assigning ground terminals for improving the linearity of a source ground type frequency mixing circuit(mixer circuit). SOLUTION: Different terminals are assigned to the ground terminals of a local signal buffer amplifier circuit and a mixer circuit so that any influence of the pulsation of the potential of the ground terminal due to currents running through the mixer circuit side on the local signal buffer amplifier circuit can be reduced. Moreover, a resistance is added between the source and ground terminal of a pair of RF signal input MOS transistors so that any influence of the pulsation of the potential of the ground terminal can be reduced.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体回路のソー
ス接地型周波数混合回路(ミキサ回路)に係り、特に相
補的な電界効果トランジスタ(CMOS)を用いた周波
数混合回路の線形性を改善するのに好適なミキサ回路に
関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a grounded source type frequency mixing circuit (mixer circuit) for a semiconductor circuit, and more particularly to an improvement in the linearity of a frequency mixing circuit using complementary field effect transistors (CMOS). The present invention relates to a mixer circuit suitable for:

【0002】[0002]

【従来の技術】移動体通信の爆発的普及に伴い、携帯端
末等に使用する高周波回路の集積化の検討が活発になさ
れている。適用されるデバイスはSiバイポーラ,CM
OS(相補的な電界効果型トランジスタ)等、多岐にわ
たる。
2. Description of the Related Art With the explosive spread of mobile communication, integration of high-frequency circuits used in portable terminals and the like has been actively studied. Applicable devices are Si bipolar, CM
OS (complementary field effect transistor) and so on.

【0003】バイポーラトランジスタを適用した従来例
としては、例えばNEC民生用高周波デバイスデータブ
ック 1993/1994のp.1352〜1379 に
記載されている「μPC1694GR−ダウン・コンバ
ータ用Si−MMIC」がある。これは局部発振器,バ
ッファ増幅器,ミキサ回路を1チップに集積化したもの
である。
As a conventional example to which a bipolar transistor is applied, for example, there is “μPC1694GR-Si-MMIC for down converter” described in pp. 1352-1379 of the NEC consumer high-frequency device data book 1993/1994. This is one in which a local oscillator, a buffer amplifier, and a mixer circuit are integrated on one chip.

【0004】図2にこの従来例の回路接続の概要を示
す。図において、R1,R2はバイアス用抵抗、R8は
線形化用抵抗、R9,R10はバイアス抵抗、Q1,Q
2はRF信号入力npnトランジスタ、Q3,Q4,Q
5,Q6はnpnトランジスタ、端子1はミキサ用接地
端子、端子2はミキサ出力端子、端子3はミキサ出力端
子、端子7はミキサ局発信号入力端子(集積回路内端
子)、端子8はミキサ局発信号入力端子(集積回路内端
子)、端子対9はミキサRF信号入力端子である。
FIG. 2 shows an outline of circuit connection of this conventional example. In the figure, R1 and R2 are bias resistors, R8 is a resistor for linearization, R9 and R10 are bias resistors, and Q1 and Q
2 is an RF signal input npn transistor, Q3, Q4, Q
5, Q6 are npn transistors, terminal 1 is a mixer ground terminal, terminal 2 is a mixer output terminal, terminal 3 is a mixer output terminal, terminal 7 is a mixer station oscillation signal input terminal (terminal in an integrated circuit), and terminal 8 is a mixer station. An outgoing signal input terminal (terminal in the integrated circuit), terminal pair 9 is a mixer RF signal input terminal.

【0005】図2のミキサ回路はエミッタに線形化用抵
抗R8を加えたギルバート形乗算器である。差動対1に
RF(高周波)信号が印加され差動電流を発生する。こ
の電流は大振幅のLO(局部発振)信号を加えられスイ
ッチング動作をする差動対2,3によってON,OFF
されRF周波数とLO周波数の差と和の周波数成分を発
生する。出力端子に低域通過フィルタを適宜接続するこ
とで差の周波数成分を中間周波信号として摘出する。
[0005] The mixer circuit of FIG. 2 is a Gilbert-type multiplier in which a linearizing resistor R8 is added to the emitter. An RF (high frequency) signal is applied to the differential pair 1 to generate a differential current. This current is turned on and off by a differential pair 2 and 3 which are supplied with a large amplitude LO (local oscillation) signal and perform a switching operation.
Then, a frequency component of the difference between the RF frequency and the LO frequency and the sum is generated. By appropriately connecting a low-pass filter to the output terminal, a difference frequency component is extracted as an intermediate frequency signal.

【0006】このミキサを用いたICのブロック構成を
図3に示す。ここではすべての回路の接地電位が単一の
接地端子に接続され、パッケージのピンの内、接地端子
に割り当てられているのは1つのみである。本従来例は
ミキサ,バッファ増幅器,局部発振器のすべての回路が
エミッタを互いに接続し、接続点を電流源あるいは抵抗
に接続した差動対回路で構成されている。このため、R
F信号は接地端子の電位に影響を与えることが少ない。
これにより、ここで記載されているように1つの接地端
子で機能を満足している。
FIG. 3 shows a block configuration of an IC using this mixer. Here, the ground potentials of all the circuits are connected to a single ground terminal, and only one of the package pins is assigned to the ground terminal. In this conventional example, all circuits of a mixer, a buffer amplifier, and a local oscillator are constituted by a differential pair circuit in which emitters are connected to each other and a connection point is connected to a current source or a resistor. Therefore, R
The F signal rarely affects the potential of the ground terminal.
This satisfies the function with one ground terminal as described herein.

【0007】近年は前述したバイポーラ回路のみではな
く従来論理回路あるいは数10MHz以下のアナログ,デ
ィジタル混載回路に適用されてきたCMOSデバイスを
用いた高周波回路の研究開発も盛んになって来ている。
CMOSデバイスを適用したミキサ回路の代表的な例と
して、アイイーイーイー ジャーナル オブ ソリッド
ステートサーキッツ,31巻,7号,880頁から88
9頁(IEEE J of Solid−State Circuits,Vol.31,
No.7,July 1996)に記載された「ダイレクトコ
ンバージョン受信機用1GHz動作CMOS RF回
路」が挙げられる。
In recent years, research and development of high-frequency circuits using CMOS devices, which have been applied not only to the aforementioned bipolar circuits but also to conventional logic circuits or analog and digital mixed circuits of several tens of MHz or less, have become active.
As a typical example of a mixer circuit to which a CMOS device is applied, IEEJ Journal of Solid State Circuits, Vol. 31, No. 7, pp. 880-88.
Page 9 (IEEE J of Solid-State Circuits, Vol. 31,
No. 7, July 1996), "1 GHz operation CMOS RF circuit for direct conversion receiver".

【0008】図4に本従来例の回路図を示す。図におい
て、M1,M2はRF信号入力NMOSトランジスタ、M
3,M4,M5,M6はNMOSトランジスタ、M13〜
M18はPMOSトランジスタ、C1はキャパシタ、端
子1はミキサ用接地端子、端子2はミキサ出力端子、端
子3はミキサ出力端子、端子7はミキサ局発信号入力端
子(集積回路内端子)、端子8はミキサ局発信号入力端
子(集積回路内端子)、端子対9はミキサRF信号入力
端子である。
FIG. 4 shows a circuit diagram of the conventional example. In the figure, M1 and M2 are RF signal input NMOS transistors, M
3, M4, M5 and M6 are NMOS transistors, M13 to
M18 is a PMOS transistor, C1 is a capacitor, terminal 1 is a mixer ground terminal, terminal 2 is a mixer output terminal, terminal 3 is a mixer output terminal, terminal 7 is a mixer local oscillator signal input terminal (terminal in an integrated circuit), and terminal 8 is A mixer local oscillator signal input terminal (terminal in the integrated circuit), terminal pair 9 is a mixer RF signal input terminal.

【0009】これはバイポーラデバイスの従来例ですべ
ての回路を差動対を用いて構成していたのに対し、ミキ
サ回路のRF(高周波)信号入力をソース端子を接地し
た1組のトランジスタ対のゲートに入力するものであ
る。ソース端子が直接接地されているため差動対とは異
なり回路を流れる電流が、電流源あるいは抵抗で制限さ
れない。このため大振幅信号が入力されるとそれに追随
して大電流を流すことが可能になり、線形性の高い回路
が実現できる。
This is a conventional bipolar device in which all circuits are configured using differential pairs. On the other hand, an RF (high frequency) signal input of a mixer circuit is connected to a pair of transistor pairs whose source terminals are grounded. Input to the gate. Since the source terminal is directly grounded, the current flowing through the circuit is not limited by the current source or the resistor unlike the differential pair. For this reason, when a large amplitude signal is input, a large current can flow following the input, and a circuit with high linearity can be realized.

【0010】[0010]

【発明が解決しようとする課題】前述したようにソース
接地回路を活用すると線形性の高いミキサ回路が実現で
きるがソース端子が直接接地端子に接続されているた
め、接地端子を局部発振信号用のバッファ増幅器と共通
にした場合、図6に示すように入力RF信号が大きくな
った時にパッケージピンの寄生インダクタンスL1の影
響で集積回路内部の接地端子の電位が変動する。この影
響によりRF信号が局部発振信号用のバッファ増幅器等
に混入し、ミキサのスイッチング動作を不完全なものと
し、線形性を劣化させる。このようにFETのソースを
直接接地したミキサ回路においては接地端子につく共通
インピーダンス成分による線形性の劣化を対策すること
が課題となる。
As described above, a mixer circuit having high linearity can be realized by utilizing the source ground circuit. However, since the source terminal is directly connected to the ground terminal, the ground terminal is used for a local oscillation signal. When the buffer amplifier is used in common, as shown in FIG. 6, when the input RF signal increases, the potential of the ground terminal inside the integrated circuit fluctuates due to the influence of the parasitic inductance L1 of the package pin. Due to this effect, the RF signal is mixed into the buffer amplifier for the local oscillation signal and the like, so that the switching operation of the mixer is incomplete and the linearity is deteriorated. As described above, in the mixer circuit in which the source of the FET is directly grounded, it is necessary to take measures against degradation of linearity due to a common impedance component attached to the ground terminal.

【0011】[0011]

【課題を解決するための手段】上記課題は、ミキサ回路
とバッファ増幅器の接地端子を分離することと、両回路
を異なる分離した島上に形成することにより、寄生素子
と基板伝導に起因するミキサ回路の接地端子の電位の変
動が局発信号バッファ回路に伝わる量を低減することで
達成される。
SUMMARY OF THE INVENTION The object of the present invention is to provide a mixer circuit which is caused by parasitic elements and substrate conduction by separating the ground terminal of the mixer circuit and the buffer amplifier and forming both circuits on different isolated islands. This is achieved by reducing the amount of change in the potential of the ground terminal of the local signal transmitted to the local oscillation signal buffer circuit.

【0012】[0012]

【発明の実施の形態】本発明の第1の実施形態を図1,
図5,図6を用いて説明する。図において、M1,M2
はRF信号入力NMOSトランジスタ、M3,M4,M
5,M6はNMOSトランジスタ、M7〜M12は差動
対NMOSトランジスタ、R1,R2はバイアス用抵
抗、R3〜R6は負荷抵抗、L1はパッケージおよびボ
ンディングワイアの寄生インダクタ、C1はキャパシ
タ、端子1はミキサ用接地端子、端子2はミキサ出力端
子、端子3はミキサ出力端子、端子対(または端子)4
は局発信号バッファ増幅器入力端子、端子5は局発信号
バッファ増幅器電源端子、端子6は局発信号バッファ増
幅器接地端子、端子7はミキサ局発信号入力端子(集積
回路内端子)、端子8はミキサ局発信号入力端子(集積
回路内端子)、端子対9はミキサRF信号入力端子であ
る。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention is shown in FIGS.
This will be described with reference to FIGS. In the figure, M1, M2
Are RF signal input NMOS transistors, M3, M4, M
5, M6 are NMOS transistors, M7 to M12 are differential pair NMOS transistors, R1 and R2 are bias resistors, R3 to R6 are load resistors, L1 is a parasitic inductor of a package and a bonding wire, C1 is a capacitor, and terminal 1 is a mixer. Terminal 2 is a mixer output terminal, terminal 3 is a mixer output terminal, terminal pair (or terminal) 4
Is a local oscillation signal buffer amplifier input terminal, a terminal 5 is a local oscillation signal buffer amplifier power supply terminal, a terminal 6 is a local oscillation signal buffer amplifier ground terminal, a terminal 7 is a mixer local oscillation signal input terminal (terminal in an integrated circuit), and a terminal 8 is A mixer local oscillator signal input terminal (terminal in the integrated circuit), terminal pair 9 is a mixer RF signal input terminal.

【0013】図1は、本発明の一実施形態を示すブロッ
ク図である。図1において局発信号バッファ増幅回路と
ミキサ回路の接地端子には異なる端子(端子6および端
子1)が割り当てられている。その結果、ミキサ回路側
を流れる電流に起因する接地端子の電位の脈動が局発バ
ッファ増幅回路に与える影響を低減することが可能とな
る。
FIG. 1 is a block diagram showing an embodiment of the present invention. In FIG. 1, different terminals (terminal 6 and terminal 1) are assigned to ground terminals of the local oscillation signal buffer amplifier circuit and the mixer circuit. As a result, it is possible to reduce the influence of the pulsation of the potential of the ground terminal caused by the current flowing on the mixer circuit side on the local buffer amplifier circuit.

【0014】接地電位の脈動が与える影響について図
5,図6を用いて更に詳細を述べる。図5はバッファ増
幅回路の詳細を描き加えたものである。図5に示すミキ
サ回路とバッファ増幅回路が図6に示すように共通の接
地端子を持ち、共通インピーダンスとしてパッケージお
よびボンディングワイアのインダクタンスが存在したと
する。このとき、バッファ用接地端子にRF信号が混入
したとするとM11,M12はゲート接地型増幅器とし
て働き、M7〜M10によって更に大きなインピーダン
ス変換を受け、負荷抵抗R3〜R6に大きなRF信号振
幅が発生する。この信号はソースから入るため負荷抵抗
対に対して同相で発生する。この大きな同相信号により
バッファ増幅器の差動動作範囲が減少し、ミキサのスイ
ッチングに十分な差動信号を得ることができず、結果と
して利得,線形性が劣化する。
The influence of the pulsation of the ground potential will be described in further detail with reference to FIGS. FIG. 5 shows the details of the buffer amplifier circuit. It is assumed that the mixer circuit and the buffer amplifier circuit shown in FIG. 5 have a common ground terminal as shown in FIG. 6, and the package and bonding wire inductances exist as a common impedance. At this time, if an RF signal is mixed into the buffer ground terminal, M11 and M12 function as a gate-grounded amplifier, undergo further impedance conversion by M7 to M10, and generate a large RF signal amplitude in load resistors R3 to R6. . Since this signal comes from the source, it is generated in phase with the load resistance pair. The large common-mode signal reduces the differential operation range of the buffer amplifier, making it impossible to obtain a differential signal sufficient for switching of the mixer. As a result, gain and linearity deteriorate.

【0015】これに対し、本発明の回路では、図1,図
5に示すようにミキサの接地端子とバッファ用増幅器の
接地端子を分離することでRF信号によるLO信号の抑
圧効果を低減できる。
On the other hand, in the circuit of the present invention, the effect of suppressing the LO signal by the RF signal can be reduced by separating the ground terminal of the mixer and the ground terminal of the buffer amplifier as shown in FIGS.

【0016】本発明の第2の実施形態を図7を用いて説
明する。第1の実施形態ではミキサとバッファ増幅器の
接地端子を分離することで2つの接地端子の共通インピ
ーダンスをなくすることで対策を施した。しかしながら
実装基板の制約から、基板上で共通インピーダンスを持
つ場合が想定される。このような場合はミキサ回路から
接地端子に発せられるRF信号を低減する必要がある。
A second embodiment of the present invention will be described with reference to FIG. In the first embodiment, a countermeasure is taken by eliminating the common impedance of the two ground terminals by separating the ground terminals of the mixer and the buffer amplifier. However, due to the restrictions of the mounting substrate, a case where the substrate has a common impedance is assumed. In such a case, it is necessary to reduce the RF signal emitted from the mixer circuit to the ground terminal.

【0017】図5において局発信号バッファ回路とミキ
サ回路の接地端子には異なる端子が割り当てられてい
る。図7の実施形態では、さらにミキサ回路の接地端子
に発生するRF信号による脈動を抑圧するため、抵抗R
7を接地端子と高周波(RF)信号入力MOSトランジ
スタのM1およびM2の接続点との間に追加する。R7
はM1,M2対に対して同相除去効果を加え、ミキサ接
地端子の信号振幅を低減する。これによると、M1,M
2の動作状態が互いに影響し、互いに流れる電流量に制
限を加えるため線形性が若干劣化するが、基板上の接地
インピーダンスが低減できない場合は次善の策となる。
In FIG. 5, different terminals are assigned to ground terminals of the local oscillation signal buffer circuit and the mixer circuit. In the embodiment of FIG. 7, in order to further suppress pulsation due to an RF signal generated at the ground terminal of the mixer circuit, the resistance R
7 is added between the ground terminal and the connection point of the high frequency (RF) signal input MOS transistors M1 and M2. R7
Adds an in-phase removal effect to the M1 and M2 pairs and reduces the signal amplitude at the mixer ground terminal. According to this, M1, M
The two operating states affect each other and limit the amount of current flowing through each other, so that the linearity is slightly deteriorated. However, if the ground impedance on the substrate cannot be reduced, the next best measure is taken.

【0018】本発明の第3の実施形態を図8を用いて説
明する。図8(a)は、半導体基板の上面図、図8
(b)は、図8(a)A−A間の断面図である。基板材
料として、シリコン オン インシュレータ(Silicon
on insulator)基板を用い、局発信号バッファ回路とソ
ース接地型ミキサ回路を絶縁体に囲まれた異なる島上に
配置することにより、両回路間の干渉を低減し、接地端
子の脈動を低減することが可能となる。さらに、外部取
出し電極端子の周辺部を同様に絶縁体によって、囲むこ
とにより、この外部取出し電極端子と基板間の寄生容量
を減らすことが可能となり、各信号間の干渉低減が可能
となる。
A third embodiment of the present invention will be described with reference to FIG. FIG. 8A is a top view of the semiconductor substrate, and FIG.
FIG. 8B is a cross-sectional view taken along the line AA in FIG. Silicon on insulator (Silicon
By using a substrate and arranging a local signal buffer circuit and a grounded source mixer circuit on different islands surrounded by an insulator, interference between both circuits is reduced and pulsation of the ground terminal is reduced. Becomes possible. Furthermore, by surrounding the periphery of the external extraction electrode terminal with an insulator in the same manner, the parasitic capacitance between the external extraction electrode terminal and the substrate can be reduced, and interference between signals can be reduced.

【0019】本発明の第4の実施形態を図9を用いて説
明する。図9は、基板への給電用コンタクトを局発信号
バッファ増幅回路とソース接地型ミキサで分離すること
を示す半導体基板上面図である。このように接地する基
板コンタクトについてもミキサ回路,バッファ増幅器で
分けることでブロック間の干渉を低減している。
A fourth embodiment of the present invention will be described with reference to FIG. FIG. 9 is a top view of a semiconductor substrate showing that a power supply contact to the substrate is separated by a local signal buffer amplifier circuit and a grounded source mixer. In this way, the ground contact is also divided by the mixer circuit and the buffer amplifier to reduce the interference between blocks.

【0020】本発明の第5の実施形態を図10を用いて
説明する。図10は、静電破壊防止素子に対する給電方
法を示す図である。局発信号バッファ増幅回路の基板へ
の給電端子と局発信号バッファ増幅回路の接地端子を共
通にして外部に取出す。同様にソース接地型ミキサ回路
の基板への給電端子とソース接地型ミキサ回路の接地端
子を共通にして外部に取出す。静電破壊防止素子への給
電端子を局発信号バッファ増幅回路とソース接地型ミキ
サで分離する。局発信号バッファ増幅回路の静電破壊防
止素子への給電端子と局発信号バッファ増幅回路の接地
端子を共通にして外部に取出す。同様にソース接地型ミ
キサ回路の静電破壊防止素子への給電端子とソース接地
型ミキサ回路の接地端子を共通にして外部に取出す。
A fifth embodiment of the present invention will be described with reference to FIG. FIG. 10 is a diagram illustrating a power supply method for the electrostatic discharge protection element. A power supply terminal to the substrate of the local oscillation signal buffer amplifier circuit and a ground terminal of the local oscillation signal buffer amplifier circuit are commonly taken out. Similarly, the power supply terminal to the substrate of the common-source mixer circuit and the common ground terminal of the common-source mixer circuit are taken out. The power supply terminal to the electrostatic discharge protection element is separated by a local signal buffer amplifier circuit and a grounded source mixer. A power supply terminal to the electrostatic discharge protection element of the local oscillation signal buffer amplifier circuit and a ground terminal of the local oscillation signal buffer amplifier circuit are commonly taken out. Similarly, the power supply terminal to the electrostatic discharge protection element of the grounded source mixer circuit and the ground terminal of the grounded source mixer circuit are commonly taken out.

【0021】これにより両回路間の干渉を低減すること
が可能となる。1.9GHz 帯におけるシミュレーショ
ンによると、およそ0.3pF の静電破壊防止素子の寄
生容量の影響で3dB以上のコンプレッションポイント
の低下が確認されており、本実施例はソース接地型ミキ
サ回路の実用化には必要不可欠なものである。
This makes it possible to reduce the interference between the two circuits. According to the simulation in the 1.9 GHz band, it was confirmed that the compression point was reduced by 3 dB or more due to the influence of the parasitic capacitance of the electrostatic discharge protection element of about 0.3 pF. Is indispensable.

【0022】[0022]

【発明の効果】0.35μm CMOSデバイスを900
MHz帯の受信用周波数混合回路に対して適用すること
を想定した回路シミュレーションの結果、接地端子を共
通にした場合に比較して、本発明を適用して接地端子を
分離することにより、回路の線形性の指標である−1d
Bコンプレッションポイントを6dB改善できることを
確認した。−1dBコンプレッションポイントは入力電
力を増加したとき回路が飽和動作をして利得が1dB低
下する入力電力で定義される。
According to the present invention, a 0.35 .mu.m CMOS
As a result of a circuit simulation assuming that the circuit is applied to a reception frequency mixing circuit in the MHz band, as compared with a case where the ground terminal is shared, by applying the present invention and separating the ground terminal, -1d which is an index of linearity
It was confirmed that the B compression point could be improved by 6 dB. The -1 dB compression point is defined as the input power at which the circuit performs a saturation operation and the gain is reduced by 1 dB when the input power is increased.

【0023】また1.9GHz帯においては、およそ0.
3pFの静電破壊防止素子の寄生容量の影響で3dB以
上のコンプレッションポイントの低下がシミュレーショ
ンにより確認され、本発明の基板の分離,静電破壊防止
素子の電源分離が大きな効果を持つことが確認された。
In the 1.9 GHz band, about 0.9
By simulation, a reduction in the compression point of 3 dB or more due to the influence of the parasitic capacitance of the electrostatic discharge protection element of 3 pF was confirmed by simulation, and it was confirmed that the separation of the substrate of the present invention and the power supply separation of the electrostatic discharge prevention element had great effects. Was.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施例のソース接地型ミキサ回路を
示す回路図。
FIG. 1 is a circuit diagram showing a common-source mixer circuit according to one embodiment of the present invention.

【図2】従来のバイポーラトランジスタを用いたギルバ
ート乗算器の回路図。
FIG. 2 is a circuit diagram of a Gilbert multiplier using a conventional bipolar transistor.

【図3】従来のバッファ増幅回路付きダウンコンバータ
ICの構成例を示すブロック図。
FIG. 3 is a block diagram showing a configuration example of a conventional downconverter IC with a buffer amplifier circuit.

【図4】従来のソース接地型ミキサ回路の回路図。FIG. 4 is a circuit diagram of a conventional grounded source mixer circuit.

【図5】図1に示した回路のバッファ増幅器部の詳細を
加えた回路図。
FIG. 5 is a circuit diagram in which details of a buffer amplifier unit of the circuit shown in FIG. 1 are added.

【図6】ソース接地型ミキサ回路において従来例のよう
に接地端子を共通にした場合の線形性の劣化原因を示す
ブロック図。
FIG. 6 is a block diagram showing a cause of deterioration of linearity when a common ground terminal is used in a common-source mixer circuit as in a conventional example.

【図7】本発明の他の実施例のソース接地型ミキサ回路
を示す回路図。
FIG. 7 is a circuit diagram showing a common-source mixer circuit according to another embodiment of the present invention.

【図8】本発明の一実施例の回路を構成した半導体基板
の(a)上面図および(b)断面図。
FIG. 8A is a top view and FIG. 8B is a cross-sectional view of a semiconductor substrate constituting a circuit according to one embodiment of the present invention.

【図9】本発明の実施例のソース接地型ミキサ回路の基
板への給電端子割当て方法の実施例を示す平面図。
FIG. 9 is a plan view showing an embodiment of a method of allocating a power supply terminal to a substrate of a common-source mixer circuit according to an embodiment of the present invention.

【図10】静電破壊防止素子への給電端子割当て方法の
実施例を示すブロック図。
FIG. 10 is a block diagram showing an embodiment of a method of allocating a power supply terminal to an electrostatic discharge protection element.

【符号の説明】[Explanation of symbols]

M1,M2…RF信号入力NMOSトランジスタ、M
3,M4,M5,M6…NMOSトランジスタ、M7〜
M12…差動対NMOSトランジスタ、M13〜M18
…PMOSトランジスタ、R1,R2…バイアス用抵
抗、R3〜R6…負荷抵抗、R7…振幅減衰抵抗、R8
…線形化用抵抗、R9,R10…バイアス抵抗、Q1,
Q2…RF信号入力npnトランジスタ、Q3,Q4,
Q5,Q6…npnトランジスタ、L1…パッケージお
よびボンディングワイアの寄生インダクタ、C1…キャ
パシタ、端子1…ミキサ用接地端子、端子2…ミキサ出
力端子、端子3…ミキサ出力端子、端子対4および端子
4…局発信号バッファ増幅器入力端子、端子5…局発信
号バッファ増幅器電源端子、端子6…局発信号バッファ
増幅器接地端子、端子7…ミキサ局発信号入力端子(集
積回路内端子)、端子8…ミキサ局発信号入力端子(集
積回路内端子)、端子対9…ミキサRF信号入力端子。
M1, M2: RF signal input NMOS transistor, M
3, M4, M5, M6 ... NMOS transistors, M7 to
M12: Differential pair NMOS transistor, M13 to M18
... PMOS transistors, R1, R2 ... bias resistors, R3-R6 ... load resistors, R7 ... amplitude attenuation resistors, R8
... Resistor for linearization, R9, R10 ... Bias resistor, Q1,
Q2: RF signal input npn transistor, Q3, Q4
Q5, Q6 ... npn transistor, L1 ... parasitic inductor of package and bonding wire, C1 ... capacitor, terminal 1 ... ground terminal for mixer, terminal 2 ... mixer output terminal, terminal 3 ... mixer output terminal, terminal pair 4 and terminal 4 ... Local oscillation signal buffer amplifier input terminal, terminal 5: local oscillation signal buffer amplifier power supply terminal, terminal 6: local oscillation signal buffer amplifier ground terminal, terminal 7: mixer local oscillation signal input terminal (integrated circuit terminal), terminal 8: mixer Local oscillation signal input terminal (terminal in the integrated circuit), terminal pair 9: mixer RF signal input terminal.

Claims (8)

【特許請求の範囲】[Claims] 【請求項1】同一半導体基板上に形成された周波数混合
回路(ミキサ回路)および局部発振器の信号振幅をミキ
サ回路を駆動するために所定の大きさに増幅するための
増幅回路(局発信号バッファ回路)からなる回路におい
て、ミキサ回路および局発信号バッファ回路の接地(グ
ランド)端子を分離し、異なる端子に割り当てたことを
特徴とする集積化ミキサ回路。
An amplifier circuit (a local signal buffer) for amplifying a signal amplitude of a frequency mixing circuit (mixer circuit) and a local oscillator to a predetermined size to drive the mixer circuit formed on the same semiconductor substrate. A mixer circuit and a local oscillation signal buffer circuit, wherein ground terminals of the mixer circuit and the local signal buffer circuit are separated and assigned to different terminals.
【請求項2】請求項1に記載の集積化ミキサ回路におい
て第1および第2のトランジスタのソースをミキサ用接
地端子に接続し、第1および第2のトランジスタのゲー
トから差動信号を入力し、第3および第4のトランジス
タのソースと第1のトランジスタのドレインを接続し、
第5および第6のトランジスタのソースと第2のトラン
ジスタのドレインを接続し、第4および第6のトランジ
スタのドレインを接続した出力端子を第1のミキサ出力
端子とし、第3および第5のトランジスタのドレインを
接続した出力端子を第2のミキサ出力端子とするミキサ
回路と、局発信号の入力端子と電源供給端子と接地端子
と第1のバッファ出力端子および第2のバッファ出力端
子を持つ局発信号を増幅する局発信号バッファ増幅回路
よりなり、上記第1のバッファ出力端子は、上記第4お
よび第5のトランジスタのゲートに接続し、上記第2の
バッファ出力端子は、上記第3および第6のトランジス
タのゲートに接続したことを特徴とする集積化ミキサ回
路。
2. The integrated mixer circuit according to claim 1, wherein the sources of the first and second transistors are connected to a mixer ground terminal, and a differential signal is inputted from the gates of the first and second transistors. , Connecting the sources of the third and fourth transistors and the drain of the first transistor,
A third mixer and a fifth transistor, wherein the source of the fifth and sixth transistors is connected to the drain of the second transistor, the output terminal connecting the drains of the fourth and sixth transistors is the first mixer output terminal, A mixer circuit having an output terminal connected to the drain of the second as a second mixer output terminal, a station having an input terminal for a local oscillation signal, a power supply terminal, a ground terminal, a first buffer output terminal and a second buffer output terminal. The first buffer output terminal is connected to the gates of the fourth and fifth transistors, and the second buffer output terminal is connected to the third and fifth transistors. An integrated mixer circuit connected to the gate of a sixth transistor.
【請求項3】請求項2に記載の集積化ミキサ回路におい
てミキサ回路の第1および第2の信号入力トランジスタ
対のソース端子に抵抗の一端を接続し、上記抵抗の逆の
端子を接地端子に接続してなることを特徴とする集積化
ミキサ回路。
3. The integrated mixer circuit according to claim 2, wherein one end of a resistor is connected to a source terminal of the first and second signal input transistor pairs of the mixer circuit, and a terminal opposite to the resistor is connected to a ground terminal. An integrated mixer circuit characterized by being connected.
【請求項4】請求項2に記載の集積化ミキサ回路におい
て、第1〜第6のトランジスタはN型導電性MOSトラ
ンジスタであることを特徴とする集積化ミキサ回路。
4. The integrated mixer circuit according to claim 2, wherein the first to sixth transistors are N-type conductive MOS transistors.
【請求項5】請求項2に記載の集積化ミキサ回路におい
て、第1〜第6のトランジスタはP型導電性MOSトラ
ンジスタであることを特徴とする集積化ミキサ回路。
5. The integrated mixer circuit according to claim 2, wherein the first to sixth transistors are P-type conductive MOS transistors.
【請求項6】請求項1に記載の集積化ミキサ回路におい
て、基板材料として、シリコン オン インシュレータ
(Silicon on insulator)基板を用い、局発信号バッフ
ァ増幅回路,ソース接地型ミキサ回路本体および外部取
出し電極の各々について側面および底面を絶縁体にて誘
電体分離することを特徴とする集積化ミキサ回路。
6. The integrated mixer circuit according to claim 1, wherein a silicon-on-insulator (Silicon on insulator) substrate is used as a substrate material, and a local signal buffer amplifier circuit, a source grounded mixer circuit main body, and an external extraction electrode are used. Wherein the side and bottom surfaces of each of the above are separated from each other by an insulator.
【請求項7】請求項6に記載の集積化ミキサ回路におい
て、バッファ増幅回路を形成する分離された基板電位を
バッファ増幅器の交流的接地電位に接続し、ミキサ回路
を形成する分離された基板電位をミキサ回路の交流的接
地電位に接続したことを特徴とする集積化ミキサ回路。
7. The integrated mixer circuit according to claim 6, wherein the separated substrate potential forming the buffer amplifier circuit is connected to the AC ground potential of the buffer amplifier, and the separated substrate potential forming the mixer circuit is connected. Is connected to an AC ground potential of the mixer circuit.
【請求項8】請求項1に記載の集積化ミキサ回路におい
て、局発信号バッファ回路の入力端子に接続される静電
破壊防止用ダイオードの接地端子,電源端子をそれぞれ
バッファ増幅器の接地端子,電源端子に接続し、ミキサ
回路のRF信号入力端子に接続される静電破壊防止用ダ
イオードの接地端子をミキサ回路の接地端子に接続した
ことを特徴とする集積化ミキサ回路。
8. The integrated mixer circuit according to claim 1, wherein a ground terminal and a power supply terminal of a diode for preventing electrostatic destruction connected to an input terminal of the local oscillation signal buffer circuit are respectively connected to a ground terminal of a buffer amplifier and a power supply. An integrated mixer circuit, wherein a ground terminal of an ESD protection diode connected to a terminal of the mixer circuit is connected to a ground terminal of the mixer circuit.
JP26268598A 1998-09-17 1998-09-17 Integrated mixer circuit Expired - Fee Related JP3750890B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP26268598A JP3750890B2 (en) 1998-09-17 1998-09-17 Integrated mixer circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26268598A JP3750890B2 (en) 1998-09-17 1998-09-17 Integrated mixer circuit

Publications (2)

Publication Number Publication Date
JP2000091848A true JP2000091848A (en) 2000-03-31
JP3750890B2 JP3750890B2 (en) 2006-03-01

Family

ID=17379179

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Link
JP (1) JP3750890B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013048438A (en) * 2007-10-30 2013-03-07 Qualcomm Inc Local oscillator buffer and mixer having adjustable size
US8929840B2 (en) 2007-09-14 2015-01-06 Qualcomm Incorporated Local oscillator buffer and mixer having adjustable size

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8929840B2 (en) 2007-09-14 2015-01-06 Qualcomm Incorporated Local oscillator buffer and mixer having adjustable size
JP2013048438A (en) * 2007-10-30 2013-03-07 Qualcomm Inc Local oscillator buffer and mixer having adjustable size

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