JP2000091517A - Semiconductor memory and system lsi using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory suitable for constitution of the system LSI of a logic mixed DRAM or the like, capable of reducing the cell area and reducing the level difference from a peripheral circuit, without degrading the performance of a peripheral circuit MOSFET by substantially reducing heat processes. SOLUTION: A memory cell structure, without the need for a capacitor is formed of a laminated structure, composed of a metal 1/an insulation film 2/n-type silicon 3/an n-type delta doped layer 4/a non-doped buffer layer 5/a p-type delta doped layer 6/p-type silicon 7. In this case, impurities are doped in the two delta doped layers 4 and 6 at sufficiently high density and they are degenerated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor device which has a very small cell area, can be highly integrated, and is suitable for forming a random access memory (RAM) to be mixed with logic.

[0002]

2. Description of the Related Art A dynamic random access memory (DRAM), which has been improving the integration at a rate of four times in three years,
The demand is growing ever more, driven by the explosive sales of personal computers in recent years. Already, 16
Mass production of megabits has reached its peak, and development for mass production of 64 megabits using dimensions of 0.20 μm or smaller, which is the next generation of microfabrication technology, is in progress.

[0003] D which has been commercialized since 16 Kb
As shown in FIG. 1A, a memory cell of a RAM includes a transistor as a switch and a capacitor for storing information charges, and is called a one-transistor cell. In this memory cell, the signal voltage read to the data line is determined by the ratio between the capacitor capacitance Cs and the parasitic capacitance Cd of the data line. The information voltage of the cell is destructive reading because the information is charged to the voltage of the data line by reading the information.

[0004] The biggest problems with this memory cell are the following two points: cell signal voltage and soft error resistance.
The purpose is to secure a necessary and sufficient capacitor capacity. In order to solve this problem, the memory cell has a three-dimensional structure as shown in FIG. 1B, and the height of the capacitor has been increasing with miniaturization in order to secure a necessary and sufficient storage capacity. . However, an increase in the height of the capacitor causes a high step between the memory cell array section and the peripheral circuit, and significantly reduces the process margin including lithography, which directly leads to an increase in manufacturing cost. In DRAMs of 256 Mbits or later, it is essential that this problem becomes more and more serious.

[0005] In order to reduce the height of the capacitor, BS
The high dielectric film such as T have been studied, problem to be solved is abound, timing prospect of applying the LSI is not standing. Against this background, there is a high expectation for a memory cell that does not require a capacitor in place of the conventional one-transistor cell.

[0006]

As described above, 256
For DRAMs after M, it is expected that the conventional one-transistor cell will be quite difficult to implement due to its increased capacitor height. The present invention proposes a semiconductor memory device having a memory cell based on a new operation principle, which replaces a conventional one-transistor cell, and a method of manufacturing the same.

[0007]

Means for achieving the object of the present invention will be described with reference to the drawings.

FIG. 2 shows components (a) and a band structure (b) of a memory cell according to the present invention. This memory cell has the following laminated structure. That is, metal 1 / insulating film 2 / n-type silicon 3 / n-type delta-doped layer 4 / non-doped buffer layer 5 / p-type delta-doped layer 6 / p-type silicon 7. The two delta-doped layers are sufficiently doped with impurities and degenerate. As a result,
A band diagram in a state where no voltage is applied is as shown in FIG.

Next, the operation principle of the memory cell will be described. In the memory cell shown in FIG. 2A, a positive bias is applied to the p-type silicon 7. Initially, Figure 3
As shown in (2), at the interface between the insulator 2 and the n-type silicon 3, the band of the n-type silicon is bent. However, since holes are not injected into the interface, a so-called deep depletion state occurs. As a result, most of the applied voltage is applied to the depletion layer of the n-type silicon 3, so that the voltage applied to the insulating film 2 is weak, so that carrier tunneling is prevented and the memory cell is in a high resistance state. At this time, the n-type delta doped layer 4
Function as a barrier for hole injection from the p-type silicon 7 by diffusion, as shown in FIG.

[0010] When the applied voltage is further increased, the depletion layer at the interface between the insulator 2 and the n-type silicon 3 reaches the n-type delta-doped layer 4. Then, the diffusion barrier for holes formed by the n-type delta-doped layer 4 is lowered, and holes can be injected from the p-type silicon 7 to the interface of the insulator 2.
As a result, as shown in FIG. 4, an inversion layer is formed at the interface between the insulator 2 / n-type silicon 3 and the width of the depletion layer is reduced,
This time, most of the applied voltage is applied to the oxide film.
Since the oxide film thickness is as thin as 4 nm, tunneling of electrons from the metal 1 becomes possible, and the memory cell enters a low resistance state. Furthermore, at this time, the electrons injected from the metal 1 neutralize the donor of the n-type delta-doped layer 4, so that the barrier for hole injection further decreases and the current further increases. As a result,
The difference between the resistances of the memory cells in the high resistance state and the low resistance state can be increased. This is one of the features of introducing a delta-doped layer into a memory cell.

If a load resistor is connected in series to the memory cell according to the present invention, there are two stable points as shown in FIG.

Next, the differences from the past known examples will be described. 1
In 976, Yamamoto et al. Observed the characteristics shown in FIG. 7 with the structure shown in FIG. The difference from the present invention is that a simple PN junction is formed without a delta-doped layer. For this reason, as is clear from the above-described operation principle, compared with the present invention, the leakage current in the high resistance state is large, and the current in the low resistance state is small, that is,
There is a fatal drawback as a memory element that the signal difference between "H" and "L" is small. Further, since the switching voltage is as high as several tens of volts, there is a problem that it is unsuitable as a memory element of a modern LSI. The present invention solves such a problem and proposes a memory element that is resistant to noise.

According to the present invention, as shown in a bird's eye view in FIG. 8, a so-called cross-point type memory cell array in which a memory element is formed at an intersection of a data line and a word line can be realized. At this time, as shown in FIG. 9, the memory cell area is 4F ² where F is the minimum processing dimension. In the case of a conventional one-transistor memory cell, the area is half since it is 8F ² . Further, the semiconductor memory device having the memory element according to the present invention has an advantage that it can be formed much more easily in terms of process than the conventional element.

Next, the actual operation of the memory circuit will be described.
First, as is apparent from the above-described operation principle, it is necessary to apply a constant voltage between a word line and a data line in order to hold data. When it is defined as V0, the “H” state and the “L” state are held as shown in FIG. In order to explain the circuit operation, FIG.
Define h and Vw. Vh is the minimum voltage required to maintain the low resistance state, and Vw is the maximum voltage required to maintain the high resistance state.

FIG. 11 shows word line and data line voltages when "H" is written. Initially, the difference between the word line voltage and the data line voltage is V0 in order to hold data. In order to write the "H" state, the potential difference between the word line and the data line is temporarily set to 0, and then the potential difference between the word line and the data line is increased to Vw or more. At this time, it is important to prevent the data from being erroneously written to the non-selected memory cells, as shown in FIG. Is set to Vh or more. As a result, the memory cell transitions to the low resistance state, and the "H" state is maintained by setting the potential difference between the word line and the data line to V0.

When data is read, the potential of the word line connected to the read cell is raised, the data line is lowered, and sensing is performed with a current flowing between the word line and the data line.

FIG. 12 shows a case where the "L" state is written. In writing data, the difference between the word line potential and the data line potential may be set to Vh or less. The other points are the same as those at the time of writing “H”, including precautions for non-selected cells.

[0018]

(Embodiment 1) Hereinafter, embodiments of the present invention will be described in detail while following a manufacturing process.

The flow of the entire process is as follows: first, a MOSFET used for a peripheral circuit is formed, and then a memory cell array,
Finally, it is the order of wiring layers. This is because an annealing step necessary for forming a diffusion layer of a MOSFET is performed before forming a memory cell array, thereby keeping an impurity profile of a delta-doped layer formed in a memory cell as sharp as possible.

Now, the actual process flow will be described. First, a semiconductor substrate 11 is prepared, and a MOSFET used for a peripheral circuit is manufactured. For this purpose, first, an element isolation oxide film 12 for isolating a MOSFET is formed on the surface of a semiconductor substrate 11 by using a known selective oxidation method or a shallow trench isolation method. In this embodiment, a shallow groove separation method capable of flattening the surface is used.

Therefore, first, a separation groove having a depth of about 0.3 μm is formed in the substrate by using a known dry etching method, and after removing the damage due to the dry etching on the groove side wall and the bottom surface,
Using a known CVD (Chemical Vapor Deposition) method, a silicon oxide film is deposited to a thickness of about 0.7 μm, and an oxide film in a portion other than the groove is also replaced with a known CM.
It was selectively polished by a P (Chemical Mechanical Polishing) method to leave only the oxide film 12 buried in the groove.

Next, by implanting high energy impurities,
Two types of wells having different conductivity types were formed. Next, after cleaning the surface of the semiconductor substrate, the gate oxide film 13 of the MOSFET is removed.
Was grown by a known thermal oxidation method. The oxidation temperature is 800 degrees,
The thickness of the oxide film is 6 nm. Polycrystalline silicon containing impurities at a high concentration was deposited to a thickness of 100 nm as a gate electrode 14 on the surface of the gate oxide film.

In this embodiment, as the gate electrode,
Although polycrystalline silicon is used, it is of course possible to use a laminated film of polycrystalline silicon and a metal provided with a barrier metal for suppressing the reaction in order to reduce the gate resistance. Further, as this metal, a silicide film which does not react with polycrystalline silicon may be used.

Next, the laminated film thus formed is
The gate electrode is processed into a shape using a known dry etching method, and further, impurity ions are implanted to form the diffusion layer 15 using the gate electrode and the resist as a mask. 5 × 10 ¹⁴ arsenic is used for the n-type MOSFET in the peripheral circuit.
/ Cm ² and the same amount of boron was implanted in the p-type MOSFET of the peripheral circuit. Then, the substrate is heated under a condition of heat treatment, specifically, at 950 ° C. for 10 seconds to activate the implanted impurities, thereby forming the diffusion layer 15.
As shown in FIG. In FIG. 13, the diffusion layer is 1
Although a schematic diagram of a so-called single drain structure formed by two ion implantation steps is drawn, it is needless to say that an electric field relaxation type diffusion layer can be formed by two ion implantation steps.

After forming the MOSFET in this manner, a silicon oxide film 16 is deposited on the entire surface to a thickness of 0.7 μm, and the surface unevenness caused by the gate electrode is flattened by a known CMP method. An oxide film of about 0.1 μm was left on the substrate. Subsequently, a contact was opened to the diffusion layer and the gate electrode of the peripheral circuit MOSFET, as shown in FIG. Further, Ti, Ti
N and W laminated films 17 were deposited, and the result was as shown in FIG.

This laminated film was processed as a word line in the memory cell array region and as a local wiring in the peripheral circuit region by a known dry etching method to obtain a structure as shown in FIG. FIG. 16B shows a top view of a word line in the memory cell array area.

In the present embodiment, the embedding of the peripheral circuit contact holes and the formation of the wiring layer are performed simultaneously. However, it is of course possible to form plugs in order to improve the flatness. Further, an oxide film 19 covering the word line and the local wiring was deposited and flattened using a known CMP method, and at the same time, the upper portions of the word line and the local wiring were exposed, as shown in FIG.

Next, a memory cell array is formed. For this purpose, a laminated film was deposited as follows using a known UHV-CVD method at a temperature of about 600 degrees Celsius. That is,
100 nm of p-type polycrystalline silicon 701 containing boron at a concentration of 1 × 10 ²⁰ / cm ³ , delta-doped layer 601 containing boron at a concentration of 1 × 10 ²¹ / cm ³ , 50 nm of non-doped polysilicon 501, 1 × 10 ²¹ / a n-type polycrystalline silicon 301 containing phosphorus at a concentration of the delta doped layer 401,5 × 10 ¹⁹ / cm ³ containing phosphorus is deposited on the order of 100nm in a concentration of cm ^3, was as shown in Figure 18.

Next, the resultant is processed into a columnar shape by a known dry etching method, as shown in FIG. FIG. 19B shows a top view at this time. A columnar memory cell stands on the exposed word line, and its height is only about 250 nm. In a normal one-transistor type memory, the height of the storage capacitor electrode is about 1 to 2 microns, so it can be seen that the present invention is extremely effective in reducing the level difference between the memory cell array and peripheral circuits.

Subsequently, a 0.7 micron silicon oxide film 20 is deposited on the entire surface. Using a known CMP method, the surface irregularities caused by the memory array were flattened to expose the uppermost n-type polycrystalline silicon 301 constituting the memory cell, as shown in FIG. Next, the known CVD
An oxide film 201 having a thickness of 5 nm is deposited by the
It became like. Further, in the peripheral circuit area, FIG.
As shown in FIG. 2, a contact was opened, and a laminated film 21 of Ti, TiN, and W was sequentially deposited by a known CVD method, as shown in FIG.

The laminated film 21 is used as a data line in the memory cell array area, and is used in the peripheral circuit area.
The wiring is processed by a known dry etching method, and FIG.
4 (a). FIG. 24B is a top view of the data lines in the memory cell array area. The data line is arranged so as to cover the memory cell, and the memory cell is formed at a crossing portion of each data line and the word line when viewed from above.

In this embodiment, the burying of the contact holes and the formation of the wiring layer are performed at the same time, but it is of course possible to form a plug in order to improve the flatness. At this time, it is of course possible to use Al or Cu having a lower resistance than W as the wiring layer.

Further, if necessary, an interlayer insulating film 23 is deposited, contacts are opened, and a wiring layer 24 is formed.
The semiconductor memory device shown in FIG. 25 was obtained.

Finally, the features of this embodiment are summarized as follows.

Since no capacitor is required, the step between the memory cell array and the peripheral circuit is small. In addition, the performance of the peripheral circuit MOSFET is excellent because the heat step associated with the capacitor step is unnecessary. Further, the process is much simpler than that of a DRAM having a conventional one-transistor memory, and as a result, a high yield and a low cost can be expected.

(Embodiment 2) This embodiment is characterized by a method of manufacturing a memory cell array. Hereinafter, the manufacturing process will be described while clarifying the difference from the first embodiment.

In the present embodiment, the same manufacturing steps as in the first embodiment were performed from FIG. 13 to FIG. Next, a memory cell array is formed. For this purpose, as shown in FIG. 26, a known UHV-CVD method was used to deposit a laminated film at a temperature of about 600 degrees as follows. That is, 1 ×
100 nm of p-type polycrystalline silicon 701 containing boron at a concentration of 10 ²⁰ / cm ³ , delta-doped layer 601 containing boron at a concentration of 1 × 10 ²¹ / cm ³ , 50 nm of non-doped polysilicon 501 at 1 × 10 ²¹ / cm 3 100nm n-type polycrystalline silicon 301 containing phosphorus at a concentration of the delta doped layer 401,5 × 10 ¹⁹ / cm ³ containing phosphorus at ³ concentrations, (in the case of example 1 was laminated so far) further oxide film 201
Of 5 nm and tungsten 101 of 100 nm.
As described above, in this example, all the films to be the memory cells were continuously deposited.

Next, in the same manner as in the first embodiment, the laminated film is processed into a columnar shape by a known dry etching method, as shown in FIG. Further, a silicon oxide film 2001 is deposited on the entire surface to a thickness of 1 μm, and the surface unevenness caused by the memory array is flattened by using a known CMP method to expose the uppermost tungsten 101 constituting the memory cell. It became like.

Next, in the peripheral circuit region, a peripheral circuit contact is opened as shown in FIG.
A laminated film 2101 of Ti, TiN, W is deposited by a method,
The result is as shown in FIG. Thereafter, through the same manufacturing steps as in Example 1, a desired semiconductor memory device was obtained.

In this embodiment, since all the layers to be the memory cells are continuously stacked, the step between the memory array and the peripheral circuit region is about 350 nm, which is 100 nm larger than that in the first embodiment. However, this is not a problematic step. Further, the present embodiment has a feature that the variation in the effective dimensions of the memory cells is much smaller than that of the first embodiment. This is because in the first embodiment,
While the effective size of the memory cell is determined by the overlap of the columnar laminated film and the data line, in the second embodiment, since the batch processing is performed, the variation due to such misalignment is reduced. This is because there is no principle.

(Embodiment 3) The present embodiment relates to a semiconductor memory device in which a load resistor is connected in series to a memory cell. In the first and second embodiments, since the parasitic resistance is used as the load resistance, the magnitude may vary. This embodiment solves this problem.

The manufacturing process will be described below with reference to the drawings.
13 to 17 have undergone the same steps as in the first embodiment.
Next, a laminated film to be a memory cell was deposited in the same manner as in Example 2 as follows. That is, p-type polycrystalline silicon 701 containing boron at a concentration of 1 × 10 ²⁰ / cm ³ is deposited at 100 nm, 1 ×
Delta-doped layer 60 containing boron at a concentration of 10 ²¹ / cm ³
1. Non-doped polysilicon 501 is 50 nm, 1 × 1
A delta-doped layer 401 containing phosphorus at a concentration of 0 ²¹ / cm ³ ,
100 nm of n-type polycrystalline silicon 301 containing phosphorus at a concentration of 5 × 10 ¹⁹ / cm ³ , 5 nm of oxide film 201 and 100 nm of tungsten 101 were deposited. Further, in this embodiment, polycrystalline silicon 25 containing phosphorus was deposited at a concentration of 5 × 10 ¹⁸ / cm ³ as a load resistance connected in series to the memory cell, as shown in FIG. Of course, in order to suppress the silicidation reaction between the tungsten 101 and the polycrystalline silicon 25, it is of course possible to sandwich titanium nitride or the like as a barrier metal therebetween.

Then, similarly to the first and second embodiments, the memory cells are processed into a columnar shape by a known dry etching method, and FIG.
It looked like 1. Thereafter, through the same manufacturing process as in Example 1, a desired semiconductor memory device was obtained.

As described above, in this embodiment,
The structure is such that polycrystalline silicon 25 serving as a load resistance is connected in series to the memory cell. As a result, it is possible to suppress variations in signal strength between memory cells. The present embodiment also has an advantage that the magnitude of the load resistance can be arbitrarily changed by adjusting the impurity concentration doped into the polycrystalline silicon.

Fourth Embodiment In the first to third embodiments, a memory cell having a structure of metal / insulator / n-type semiconductor / p-type semiconductor was used. This embodiment relates to a cell having a structure of p ⁺ polycrystalline silicon / insulator / p-type semiconductor / n-type semiconductor.

In the memory cell according to the present invention, pn
It is of course possible to reverse the polarity of the junction, but at this time, it is necessary to change the polarity of the conductor formed on the insulator. This is because, as is clear from the operation principle, carriers having the opposite polarity to the inversion layer carriers are injected from the conductor.

The manufacturing process is almost the same as in Examples 1 to 3. FIG. 32 shows a cross-sectional view after the memory cell processing is completed. The laminated film constituting the cell is 5 × 10 ¹⁹ /
delta doped layer 401 containing phosphorus at a concentration of n-type polycrystalline silicon 301,1 × 10 ²¹ / cm ³ with a thickness of 100nm containing phosphorus at a concentration of cm ^3, a thickness of 50nm non-doped polysilicon 501,1 × 10 ²¹ / p-type polycrystalline silicon 701 having a thickness of 100nm containing boron at a concentration of the delta doped layer 601,1 × 10 ²⁰ / cm ³ containing boron at a concentration of cm ^3,
5 nm oxide film 201, 100 nm thick polycrystalline silicon 26 containing boron at a concentration of 1 × 10 ²⁰ / cm ³ .

(Embodiment 5) This embodiment is a case where the present invention is applied to a logic embedded RAM.

As is apparent from the above description, when forming the memory cell according to the present invention, the peripheral circuit MOSF
No thermal process is required to degrade the properties of the ET. This is because the present invention is applied to a system LS represented by a logic embedded DRAM or the like.
It means that it is very suitable for I.

FIG. 33 is a cross-sectional view after processing a memory cell when a semiconductor memory device according to the present invention is applied to a system LSI whose performance has been improved by applying a self-aligned silicidation process to a peripheral circuit MOSFET. The figure is shown.

[0051]

According to the present invention, the cell area can be reduced by the conventional DR.
Since it can be reduced to half the AM, the chip area can be significantly reduced. In addition, since a capacitor is basically unnecessary, a step with a peripheral circuit can be reduced, and a heat process can be greatly reduced as compared with the related art. It is very suitable for Further, since no capacitor is required, the present invention reduces the number of masks and significantly simplifies the process compared to conventional DRAMs.
There is also an effect of reducing manufacturing costs. Also, since refreshing is not required, power consumption is extremely small.

[Brief description of the drawings]

1A is a sectional view of an equivalent circuit of a conventional one-transistor memory cell, and FIG. 1B is a cross-sectional view of a semiconductor memory device having the conventional one-transistor memory cell.

2A is a memory cell structure according to the present invention, and FIG. 2B is a band diagram of the memory cell according to the present invention.

FIG. 3 is a band diagram of a memory cell according to the present invention in a deep depletion state (high resistance state).

FIG. 4 is a band diagram of a memory cell according to the present invention when an inversion layer is formed (low resistance state).

FIG. 5 is a diagram showing characteristics of a memory cell according to the present invention and its operation principle.

FIG. 6 is a sectional view of a known diode and a band diagram thereof.

FIG. 7 is a view showing characteristics of the diode shown in FIG. 6;

FIG. 8 is a bird's-eye view of an array of memory cells according to the present invention.

FIG. 9 is a top view of a memory cell array according to the present invention.

FIG. 10 is a characteristic diagram when data is retained in a memory cell according to the present invention.

FIG. 11 is a diagram showing an “H” writing and reading method in a memory cell according to the present invention.

FIG. 12 is a diagram showing an “L” writing and reading method in a memory cell according to the present invention.

FIG. 13 is a sectional view in a manufacturing process of the semiconductor memory device of the present invention;

FIG. 14 is a sectional view in a manufacturing process of the semiconductor memory device of the present invention.

FIG. 15 is a sectional view in a manufacturing process of the semiconductor memory device of the present invention.

16A is a cross-sectional view in a manufacturing process of the semiconductor memory device of the present invention, and FIG. 16B is a top view of the memory cell array in the manufacturing process of the semiconductor memory device of the present invention.

FIG. 17 is a sectional view in a manufacturing step of the semiconductor memory device of the present invention.

FIG. 18 is a sectional view in a manufacturing process of the semiconductor memory device of the present invention.

19A is a cross-sectional view in a manufacturing process of the semiconductor memory device of the present invention, and FIG. 19B is a top view of the memory cell array in the manufacturing process of the semiconductor memory device of the present invention.

FIG. 20 is a sectional view in a manufacturing process of the semiconductor memory device of the present invention;

FIG. 21 is a sectional view in a manufacturing process of the semiconductor memory device of the present invention;

FIG. 22 is a sectional view in a manufacturing process of the semiconductor memory device of the present invention;

FIG. 23 is a sectional view in a manufacturing process of the semiconductor memory device of the present invention;

24A is a cross-sectional view in a manufacturing process of the semiconductor memory device of the present invention, and FIG. 24B is a top view of the memory cell array in the manufacturing process of the semiconductor memory device of the present invention.

FIG. 25 is a sectional view in a manufacturing step of the semiconductor memory device of the present invention;

FIG. 26 is a sectional view in a manufacturing process of the semiconductor memory device of the present invention;

FIG. 27 is a sectional view in a manufacturing process of the semiconductor memory device of the present invention;

FIG. 28 is a sectional view in a manufacturing process of the semiconductor memory device of the present invention;

FIG. 29 is a sectional view in a manufacturing process of the semiconductor memory device of the present invention;

FIG. 30 is a sectional view in a manufacturing step of the semiconductor memory device of the present invention;

FIG. 31 is a sectional view in a manufacturing process of the semiconductor memory device of the present invention;

FIG. 32 is a sectional view in a manufacturing step of the semiconductor memory device of the present invention;

FIG. 33 is a sectional view in a manufacturing step of the semiconductor memory device of the present invention;

[Explanation of symbols]

1,101: metal, 2,201: insulating film, 3,301:
n-type semiconductor, 4,401 ... n-type delta doped layer, 5,50
DESCRIPTION OF SYMBOLS 1 ... Non-doped silicon, 6,601 ... p-type delta doped layer, 7,701 ... p-type semiconductor, 8 ... word line, 9 ... memory cell, 10 ... data line, 11 ... semiconductor substrate, 12 ...
Element isolation oxide film, 13 gate oxide film, 14 gate electrode, 15 impurity diffusion layer, 16 interlayer insulating film, 17
Metal or its laminated film, 18 word line, 19 interlayer insulating film, 20, 2001 interlayer insulating film, 21, 101
... Metal or its laminated film, 22. Data line, 23... Interlayer insulating film, 24... Metal or its laminated film, 25... Polycrystalline silicon, 26.

 ────────────────────────────────────────────────── ─── Continuing from the front page (72) Inventor Shinichiro Kimura 1-280 Higashi Koikekubo, Kokubunji-shi, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd. Central Research Laboratory (72) Inventor Akio Nishida 1-280 Higashi Koigakubo, Kokubunji-shi, Tokyo F-term (reference) 5F038 CD18 CD19 DF05 5F083 AD70 EP42 GA02 GA05 GA09 GA28 JA32 JA35 JA36 JA37 JA39 JA40 PR53 PR38 PR40

Claims (10)

[Claims] A plurality of memory cells arranged on a main surface of a semiconductor substrate and having a word line and a data line for selecting the memory cells; and a plurality of MISFETs around the memory cell array section. Wherein the memory cell comprises a stacked film of a conductor, an insulator, and a plurality of semiconductor layers containing impurities. 2. The conductor constituting the memory cell,
Polycrystalline silicon containing a high concentration of impurities, tungsten,
2. The semiconductor memory device according to claim 1, comprising at least one of aluminum, copper, titanium, platinum, and gold. 3. A semiconductor device according to claim 1, wherein said plurality of semiconductor layers containing impurities constituting said memory cell are semiconductors containing n-type impurities, and semiconductors locally doped with impurities at a concentration of about 1 × 10 ²⁰ / cm ³ or more. 3. The semiconductor memory device according to claim 1, further comprising a semiconductor containing a p-type impurity. 4. The insulator constituting the memory cell,
2. The film according to claim 1, wherein said film thickness is 5 nm or less.
4. The semiconductor memory device according to any one of items 3 to 3. 5. The semiconductor device according to claim 1, wherein a conductor separated for each memory cell is in contact with said conductor in contact with said insulating film forming said memory cell.
The semiconductor memory device according to any one of the above. 6. The conductor constituting the memory cell,
6. The semiconductor memory device according to claim 5, wherein said conductor separated for each memory cell is polycrystalline silicon containing impurities. 7. The semiconductor according to claim 1, wherein said memory cell is interposed between said word line and said data line formed in said memory cell array. Storage device. 8. The semiconductor memory device according to claim 1, wherein said word line electrically connected to said memory cell is a local wiring of said peripheral circuit region. 9. The semiconductor memory device according to claim 1, wherein said data line electrically connected to said memory cell is a local wiring of said peripheral circuit region. 10. A system LSI using the semiconductor memory device according to claim 1.