JP2000091508A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of more surely protecting a MOSFET of an FET switch (switch for a field-effect transistor) from static electricity. SOLUTION: In an N-MOS 11 where a gate voltage is controlled by an inverter 15, a gate is connected through a resistor 25 to the output of the inverter 15. In this case, a lateral transistor 31 is formed between a drain and a power supply terminal Vcc, the lateral transistor 32 is formed between a source and the power supply terminal Vcc and the static electricity applied to the drain, and the source is bypassed by the respective lateral transistors 31 and 32.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device comprising a semiconductor integrated circuit, and more particularly to a semiconductor device provided with a protection circuit for preventing electrostatic breakdown in a field effect transistor having a reduced parasitic capacitance.

[0002]

2. Description of the Related Art In recent years, the speed of signals transmitted and received between integrated circuits has been increased with the speeding up of semiconductor integrated circuits. In particular, as the speed of the digital signal increases, the rise and fall times of the signal decrease. When the rise and fall times of the signal are shortened, the signal on the printed circuit board to which the signal is transmitted is distorted such that the overshoot voltage and / or the undershoot voltage increases and the signal waveform becomes stair-like. More likely to occur. If the overshoot voltage and / or the undershoot voltage increases, the resulting ringing exceeds the threshold value of the next stage circuit, resulting in a false signal and spurious (pseudo) switching.

FIG. 10 is a schematic diagram showing a case where a memory module composed of a plurality of memory LSIs is mounted on a printed circuit board. In FIG. 10, each memory module 101 includes a plurality of memory LSIs 102 mounted on a multilayer printed circuit board 103. Each memory module 1
Numeral 01 is mounted on a multilayer printed circuit board on which a transmission line 105 for transmitting a signal for driving a signal for operating the memory LSI 102, for example, a signal output from a driver circuit 104 for driving a clock signal or the like is formed.

The external terminals of each memory module 101 corresponding to the external terminals of the memory LSI 102 are connected by branch wirings 106 formed on a printed circuit board 103. Further, each branch wiring 106 is connected to a corresponding transmission line 105 by using a connector (not shown), and the connection portion forms an electrical branch point 107 from the transmission line 105 to each branch wiring 106. ing.

In the above-described system, the output impedance of the driver circuit 104 and the characteristic impedance of the transmission line 105 are matched, but the impedance mismatch occurs due to the parasitic capacitance and the parasitic inductance attached to the branch wiring 106, and the signal is not matched. In some cases, the signal was distorted due to reflection. When the values of the parasitic capacitance and the parasitic inductance are large, the generated distortion becomes larger, and when there are many branch points on the same transmission line, the generated distortion becomes large.

Normally, the input of the memory LSI 102 is connected to the gate of a high-resistance MOS transistor and is in a high impedance state. This state is the branch point 1
From 07, it means that the end of the branch wiring 106 is open. That is, the signal sent from the branch point 107 to the memory LSI 102 is
2, and overshoot and undershoot are likely to occur. For this reason, in a system that normally operates at high speed, the branch wiring 106 and the branch point 10
It has been an issue to suppress the parasitic capacitance and the parasitic inductance at the branch portion of No. 7.

As one countermeasure against this problem, there is known a method of providing a switch of a field effect transistor (hereinafter referred to as an FET switch) between the memory LSI 102 and the transmission line 105 to suppress a parasitic capacitance and a parasitic inductance. I have. That is, in a system in which a plurality of memory modules 101 are mounted as shown in FIG. 10, all of the plurality of memory modules 101 do not operate at the same time, but operate any one. Therefore, the other memory modules are electrically separated. Thereby, the parasitic capacitance and the parasitic inductance of the branch part can be reduced.

FIG. 11 is a circuit diagram showing a conventional example of an FET switch. In FIG. 11, a plurality of N-channel MOSFETs (hereinafter, referred to as FET switches) are provided.
A description will be given by taking an example of an arbitrary N-MOS in an IC including an N-MOS. In FIG.
C110 is an N-MOS 111 and an inverter 11 that drives and controls the N-MOS 111 in response to an external signal.
2 is provided.

The inverter 112 is a P-channel type MOS
FET (hereinafter referred to as P-MOS) 113 and N-MOS
Further, an electrostatic protection diode 115 is provided between the input terminal S and the power supply terminal Vcc, and an electrostatic protection diode 116 is provided between the ground and the input terminal S. Further, an electrostatic protection diode 117 is provided between the back gate electrode of the N-MOS 111 and the power supply terminal Vcc. In addition, 118-121 is MO
2 shows a parasitic diode of an SFET.

In such a configuration, when static electricity is applied between the terminal A1 and the ground, the static electricity is bypassed by the parasitic diode 120, and when static electricity is applied between the terminal B1 and the ground, the static electricity is added by the parasitic diode 121. By bypassing, the destruction of the N-MOS 111 is prevented.

[0011]

However, the terminal A1 is connected between the terminal A1 and the power supply terminal Vcc with reference to the power supply terminal Vcc.
When positive static electricity is applied to the
7 and the parasitic diode 120 function as a bypass element, but at the same time, the parasitic diode 118 is biased in the forward direction. Therefore, the portion where the drain and the gate of the N-MOS 111 shown in FIG. High voltage is applied. For this reason, if the breakdown of the parasitic diode 120 is delayed, N
-There was a problem that the insulating film in the portion where the drain and the gate overlap in the MOS 111 was destroyed.

Similarly, when positive static electricity is applied to the terminal B1 between the terminal B1 and the power supply terminal Vcc with reference to the power supply terminal Vcc, the static electricity protection diode 117 and the parasitic diode 121 function as bypass elements. at the same time,
Since the parasitic diode 118 is forward biased,
A high voltage is applied via the parasitic diode 118 to a portion where the drain and the gate of the N-MOS 111 shown by f in the figure overlap. Therefore, if the breakdown of the parasitic diode 121 is delayed, the N-MOS 11 shown in FIG.
1 has a problem that the insulating film in the portion where the drain and the gate overlap is destroyed.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem, and has been made in consideration of the above-mentioned problems.
An object of the present invention is to provide a semiconductor device capable of more reliably protecting a MOSFET of an FET switch from static electricity by inputting a control signal to a gate of the FET via a resistor and forming a lateral bipolar transistor.

Although the configuration is different from that of the present invention, the following contents are disclosed in the official gazette. The content of inserting a resistor into the gate to protect the MOS transistor
JP-A-57-37876, JP-A-64-42855
JP-A-4-316369 and JP-A-6-2959
No. 89 discloses this. Further, the contents of forming a lateral bipolar transistor at the input / output terminal are described in JP-A-6-318677, JP-A-63-289962, JP-A-63-107163, and JP-A-59-92557.
JP-A-6-151744, JP-A-5-23534
No. 4 and JP-A-62-69660. JP-A-6-188377 discloses that a protection circuit using a lateral bipolar transistor with an open base potential is disclosed, and JP-A-10-51286 discloses that an analog switch of a MOS transistor is a parasitic bipolar transistor. Have been.

[0015]

According to the present invention, there is provided a semiconductor device which performs a switching operation in response to an external control signal, wherein at least one field effect transistor which controls connection between external terminals by the switching operation. A logic circuit for controlling a switching operation of the field effect transistor in response to a control signal from the outside, a resistance element provided between an output of the logic circuit and a gate of the field effect transistor, First
A first transistor circuit comprising a lateral bipolar transistor provided between a first voltage supply terminal to which a constant voltage is supplied and each external terminal.

In the semiconductor device according to the present invention, the first transistor circuit may be configured such that the first transistor circuit has a first impurity diffusion region forming a drain of the field effect transistor and a second impurity diffusion region forming a source of the field effect transistor. A third impurity diffusion region of the same conductivity type as the first and second impurity diffusion regions, the third impurity diffusion region being formed parallel to the first impurity diffusion region at a predetermined distance and connected to the first voltage supply terminal; The first impurity diffusion region is formed parallel to the second impurity diffusion region at a predetermined distance and connected to the first voltage supply terminal.
And a fourth impurity diffusion region having the same conductivity type as the second impurity diffusion region formed on a semiconductor substrate.

According to a first aspect of the present invention, there is provided a semiconductor device according to any one of the first and second aspects, wherein a second voltage supply terminal to which a predetermined second constant voltage is externally supplied and each external terminal. The semiconductor device further includes a second transistor circuit including the respective lateral bipolar transistors.

According to a third aspect of the present invention, in the semiconductor device according to the third aspect, the second transistor circuit includes a first impurity diffusion region forming a drain of the field effect transistor and a second impurity diffusion region forming a source of the field effect transistor. A fifth impurity diffusion region of the same conductivity type as the first and second impurity diffusion regions, the fifth impurity diffusion region being formed parallel to the first impurity diffusion region at a predetermined distance and connected to the second voltage supply terminal; The first impurity diffusion region is formed parallel to the second impurity diffusion region at a predetermined distance and connected to the second voltage supply terminal.
And a sixth impurity diffusion region of the same conductivity type as the second impurity diffusion region formed on the semiconductor substrate.

Further, in the semiconductor device according to the present invention, the width of the third and fourth impurity diffusion regions is made equal to the predetermined value W1 and the width of the fifth and sixth impurity diffusion regions is set to the predetermined value. W2 and make the predetermined value W2 a predetermined value W
It should be less than 1.

In the semiconductor device according to the present invention, the first transistor circuit is electrically connected in series to form a drain of the field effect transistor.
A plurality of first impurity diffusion regions formed in parallel with each other and a plurality of second impurity diffusion regions formed in parallel with each of the first impurity diffusion regions and electrically connected in series to form a source of the field effect transistor; A first and second impurity diffusion regions formed in parallel with a certain distance between one of the first impurity diffusion regions and one of the second impurity diffusion regions, and connected to the first voltage supply terminal; Third of the same conductivity type as the impurity diffusion region
An impurity diffusion region is formed on a semiconductor substrate.

According to a sixth aspect of the present invention, in the semiconductor device according to the sixth aspect, the second transistor circuit is arranged adjacent to the second impurity diffusion region formed in parallel with the third impurity diffusion region at a predetermined distance. A first impurity diffusion region to be formed, and the same conductivity type as the first and second impurity diffusion regions formed parallel to the first impurity diffusion region at a predetermined distance and connected to a second voltage supply terminal. A fifth impurity diffusion region, a second impurity diffusion region disposed adjacent to the first impurity diffusion region formed in parallel with the third impurity diffusion region at a predetermined distance, and the second impurity diffusion region. A sixth conductive layer, which is formed in parallel at a predetermined distance and is connected to the second voltage supply terminal and having the same conductivity type as the first and second impurity diffusion regions.
An impurity diffusion region is formed on a semiconductor substrate.

Further, according to the semiconductor device of the present invention, in any one of the first to seventh aspects, the resistance element has a resistance of 10%.
It is about 0Ω to 500Ω.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described in detail based on an embodiment shown in the drawings. Embodiment 1 FIG. FIG. 1 is a schematic diagram showing an example of a memory module using the semiconductor device according to the first embodiment of the present invention. In FIG. 1, a memory module 1 includes a plurality of memory LSIs 2 mounted on a multilayer printed circuit board 3. Each terminal of the memory module 1 and each memory LSI
2 correspond to external terminals provided with a plurality of field effect transistor switches (hereinafter referred to as FET switches).
It is connected via C4.

FIG. 2 is a schematic circuit diagram showing an example of the IC 4 of FIG. In FIG. 2, the IC4 has four FETs.
The case where a switch is provided is shown as an example. In FIG. 2, an IC 4 includes four N-channel MOSFETs (hereinafter referred to as N-MOS) 11 to 14 and an inverter 15.
It is composed of The input of the inverter 15 is connected to the input terminal S of the IC 4, and the output of the inverter 15 is connected to each gate of the N-MOSs 11 to 14. Each drain in the N-MOSs 11 to 14 is an IC
4 are connected to the corresponding terminals of the external terminals A1 to A4, and the sources of the N-MOSs 11 to 14 are connected to the IC4
Are connected corresponding to the external terminals B1 to B4.

The external terminals A1 to A4 of the IC 4 are connected to corresponding external terminals of the memory LSI 2, and the external terminals B1 to B4 of the IC 4 are connected to corresponding terminals of the memory module 1. As described above, each terminal of the memory module 1 and each external terminal of the corresponding memory LSI 2 are connected to the FET formed by one N-MOS of the IC 4.
Each terminal of the memory module 1 is connected to each external terminal of the corresponding memory LSI 2 according to a signal input to the input terminal S via a switch.

FIG. 3 is a circuit diagram showing an example of the semiconductor device according to the first embodiment of the present invention. FIG. 3 shows the N-MOS 11 and the inverter 15 in the IC 4 of FIG. 2 as an example. . In FIG. 3, a P-channel type MO
SFET (hereinafter referred to as P-MOS) 21, N-MOS2
2 and the diodes 23 and 24 form an inverter 15, and the output of the inverter 15 is a resistor 25.
Is connected to the gate of the N-MOS 11. P-
A parasitic diode 26 is formed between the drain and the back gate electrode of the MOS 21, and a parasitic diode 27 is formed between the back gate electrode and the drain of the N-MOS 22.

A parasitic diode 28 is provided between the back gate electrode and the drain of the N-MOS 11
Parasitic diodes 29 are formed between the back gate electrode and the source in S11. Furthermore, N
A lateral bipolar transistor (hereinafter, referred to as a lateral transistor) 31 is formed between the drain of the -MOS 11 and the power supply terminal Vcc, and a lateral transistor 32 is formed between the source of the N-MOS 11 and the power supply terminal Vcc. Have been.

The collector of the lateral transistor 31 is
The drain of the N-MOS 11 is connected, and the emitter of the lateral transistor 31 is connected to the power supply terminal Vcc. The collector of the lateral transistor 32 is N
-Connected to the source of the MOS 11, the emitter of the lateral transistor 32 is connected to the power supply terminal Vcc.
Further, each base of the lateral transistors 31 and 32 is connected to the ground terminal GND.

In such a configuration, when positive static electricity is applied to the external terminal A1 with respect to the power supply terminal Vcc, a breakdown occurs between the collector and the base of the lateral transistor 31 and the base potential rises. Along with this, a base current flows between the base and the emitter of the lateral transistor 31 and a current amplified between the collector and the emitter flows, and the static electricity applied to the external terminal A1 is bypassed to the power supply terminal Vcc. Until the lateral transistor 31 breaks down, the resistor 25 breaks down the insulating film at the portion where the drain and gate overlap in the N-MOS 11 shown in FIG. To prevent it from being done.

Similarly, when positive static electricity is applied to the external terminal B1 with reference to the power supply terminal Vcc, the collector-base breakdown occurs in the lateral transistor 32, and the base potential rises. When the current flows, the amplified current flows between the collector and the emitter, and the static electricity applied to the external terminal B1 is bypassed to the power supply terminal Vcc. Until the lateral transistor 32 breaks down, the resistor 25 destroys the insulating film at the portion where the drain and gate overlap in the N-MOS 11 shown in FIG. To prevent it from being done.

Here, the resistance 25 is N-MO from static electricity.
It is preferable that the resistance value is large from the viewpoint of protecting S11. However, the resistance value is selected in consideration of the switching speed of the N-MOS 11, and is about 100Ω to several 100Ω, for example, 100Ω
To a value of about 500Ω. The resistance 25 is a MOS
If polysilicon is used as the gate electrode material of the FET or the diffusion resistance is the same as that of the impurity diffusion layers of the source region and the drain region, it is not necessary to add a manufacturing process.

FIG. 4 is a diagram showing an example of the layout of the N-MOS 11 and the lateral transistors 31 and 32, and FIG. 5 is a sectional view showing a section taken along the line AA 'in FIG.

In FIG. 4 and FIG. 5, N ⁺ diffusion region 41 a fixed distance forming a drain of the N-MOS 11 (e.g., about 1 micron) is N ⁺ diffusion region 42 away, N-M
Certain distance between N ⁺ diffusion region 43 forming the source of the OS 11 (e.g., about 1 micron) Release the N ⁺ diffusion region 44
Are P-type semiconductor substrates (hereinafter referred to as P-type substrates)
45. The N ⁺ diffusion region 41 is
N ⁺ diffusion region 43 is connected to external terminal A1 of IC
4 is connected to the external terminal B1. The N ⁺ diffusion regions 42 and 44 are connected to the power supply terminal Vcc, the gate electrode 46 is connected to the output of the inverter 15 via the resistor 25, and the P-type substrate 45 is grounded.

In such a configuration, the N ⁺ diffusion region 4
Numeral 1 forms the drain of the N-MOS 11 and forms the collector of the lateral transistor 31, and the N ⁺ diffusion region 42 forms the emitter of the lateral transistor 31. Further, N ⁺ diffusion region 43 forms a collector of the lateral transistor 32 with forming the source of the N-MOS11, N ⁺
Diffusion region 44 forms the emitter of lateral transistor 32. Further, P-type substrate 45, as well as forming the respective base of the lateral transistor 31 and 32, without the respective anode of the parasitic diode 28 and 29, N ⁺ diffusion region 4
1 denotes the cathode of the parasitic diode 28 and the N ⁺ diffusion region 4
Numerals 3 each form a cathode of the parasitic diode 29.

As described above, in the semiconductor device according to the first embodiment, in the N-MOSs 11 to 14 whose gate voltages are controlled by the inverter 15,
5, a lateral transistor 31 is connected between the drain and the power supply terminal Vcc.
Lateral transistor 3 between source and power supply terminal Vcc
2 was formed, and the static electricity applied to the drain and the source was bypassed by the respective lateral transistors 31 and 32. From this, without increasing the parasitic capacitance to the MOSFET forming the FET switch,
It is possible to more reliably protect against static electricity.

Embodiment 2 FIG. 6 is a circuit diagram showing an example of a semiconductor device according to the second embodiment of the present invention. The semiconductor device shown in FIG. 6 shows the N-MOS 11 and the inverter 15 in the IC 4 of FIG. 2 as an example. 6, the same components as those in FIG. 3 are denoted by the same reference numerals, and the description thereof will be omitted, and only the differences from FIG. 3 will be described. 6 is different from FIG. 3 in that lateral transistors 51 and 52 are added.

In FIG. 6, a lateral transistor 51
Is connected to the drain of the N-MOS 11,
The collector and the base of the lateral transistor 51 are connected to the ground terminal GND, respectively. Further, the emitter of the lateral transistor 52 is connected to the source of the N-MOS 11, and the collector and base of the lateral transistor 52 are connected to the ground terminal GND.

In such a configuration, when static electricity is applied between the external terminal A1 and the ground terminal GND, the lateral transistor 51 operates as an electrostatic bypass element in addition to the parasitic diode 28, and the static electricity is applied to the ground terminal G.
Bypass to ND. Similarly, when static electricity is applied between the external terminal B1 and the ground terminal GND, the lateral transistor 52 operates as an electrostatic bypass element in addition to the parasitic diode 29, and bypasses the static electricity to the ground terminal GND.

FIG. 7 is a diagram showing an example of the layout of the N-MOS 11 and the lateral transistors 31, 32, 51 and 52. In FIG. 7, the same components as those in FIG. 4 are denoted by the same reference numerals. In FIG. 7, a certain distance (for example, N ⁺ diffusion region 41 forming the drain of N-MOS 11)
N ⁺ diffusion regions 42 and 61 (about 1 micron apart)
The N ⁺ diffusion region 43 is separated from the N ⁺ diffusion region 43 serving as the source of the N-MOS 11 by a certain distance (for example, about 1 μm).
4 and 62 are each formed on a P-type substrate.

The N ⁺ diffusion region 41 is connected to the external terminal A of the IC 4.
1 and the N ⁺ diffusion region 43 is connected to the external terminal B1 of the IC4. Also, the N ⁺ diffusion regions 42 and 4
4 is connected to the power supply terminal Vcc, N ⁺ diffusion regions 61 and 62 are connected to the ground terminal GND, respectively, and the gate electrode 46 is connected to the output of the inverter 15 via the resistor 25. N ⁺ diffusion regions 61 and 62 have the same width, and similarly, N ⁺ diffusion regions 42 and 44 have the same width.

In such a configuration, the N ⁺ diffusion region 4
Reference numeral 1 denotes a drain of the N-MOS 11 and a collector of the lateral transistor 31 and a lateral transistor 5.
The N ⁺ diffusion region 42 forms the emitter of the lateral transistor 31, and the N ⁺ diffusion region 61 forms the collector of the lateral transistor 51. Also, N
⁺ Diffusion region 43 forms the drain of N-MOS 11 and also forms the collector of lateral transistor 32 and the emitter of lateral transistor 52, N ⁺ diffusion region 42 forms the collector of lateral transistor 32, and N ⁺ diffusion region 62 forms the lateral transistor 52. The emitter.

Further, the P-type substrate forms the base of each of the lateral transistors 31, 32, 51 and 52, forms the anode of each of the parasitic diodes 28 and 29, and the N ⁺ diffusion region 41 forms the cathode of the parasitic diode 28. N ⁺ diffusion regions 43 form the cathodes of parasitic diodes 29, respectively.

Here, when the width of the N ⁺ diffusion regions 42 and 44 is W1 and the width of the N ⁺ diffusion regions 61 and 62 is W2,
By optimizing W1 and W2 so that W1> W2, between each of the external terminals A1 and B1 and the ground terminal GND, and between each of the external terminals A1 and B1 and the power terminal Vcc. , The effect of protection from static electricity can be enhanced.

In FIG. 7, the N ⁺ diffusion region 42 and the N ⁺
Although the diffusion region 44, the N ⁺ diffusion region 61, and the N ⁺ diffusion region 62 are arranged at opposing positions, as shown in FIG. 8, the N ⁺ diffusion region 42 and the N ⁺ diffusion region 61, or N ⁺ The positions of the diffusion region 44 and the N ⁺ diffusion region 62 may be switched, and the N ⁺ diffusion region 42 and the N ⁺ diffusion region 44, the N ⁺ diffusion region 61 and the N ⁺ diffusion region 62 may be arranged diagonally.

FIG. 9 is a diagram showing another layout example of the N-MOS 11 and the lateral transistors 31, 32, 51 and 52. In FIG. 9, the same components as those in FIG. 7 are denoted by the same reference numerals. In FIG. 9, N ⁺
The diffusion regions 41a and 41b are connected to form the N-MOS 11
, And the N ⁺ diffusion regions 43a and 43b are connected to form the source of the N-MOS 11. The gate electrodes 46a and 46b are connected to each other to form an N-MO.
The gate of S11 is formed. In the N ⁺ diffusion region 41a, the end opposite to the end connected to the N ⁺ diffusion region 41b is connected to the external terminal A1, and the N ⁺ diffusion region 4
In 3a, the end opposite to the end connected to the N ⁺ diffusion region 43b is connected to the external terminal B1.

The end of the gate electrode 46a opposite to the end connected to the gate electrode 46b is connected to the output of the inverter 15 via the resistor 25.
Further, a certain distance between N ⁺ diffusion region 41a (e.g., about 1
Release the micron) N ⁺ diffusion region 71 is formed, N ⁺ diffusion region 43a and N ⁺ diffusion region 41b and a fixed distance (e.g., N ⁺ diffusion region 72 apart about 1 micron) is N ⁺ diffusion region 43a And N ⁺ diffusion region 41b. An N ⁺ diffusion region 73 is formed at a certain distance (for example, about 1 micron) from the N ⁺ diffusion region 43b. N ⁺ diffusion regions 71 and 73 are ground terminals GN
D, and the N ⁺ diffusion region 72 is connected to the power supply terminal Vcc.

In such a configuration, the N ⁺ diffusion region 7
1 is a collector of the lateral transistor 51 and N
⁺ Diffusion region 41a forms the emitter of lateral transistor 51. Further, N ⁺ diffusion region 72 forms a respective emitter of the lateral transistor 31 and 32, N ⁺
Diffusion region 43a forms the collector of lateral transistor 32, and N ⁺ diffusion region 41b forms the collector of lateral transistor 31. The N ⁺ diffusion region 73
N ⁺ diffusion region 43b forms the collector of lateral transistor 52, and N ⁺ diffusion region 43b forms the emitter of lateral transistor 52.

FIG. 9 shows a case where each gate width of the gate electrodes 46a and 46b is set to half the gate width of the gate electrode 46 of FIG. 7, and the width of the N ⁺ diffusion regions 41a and 41b is of N ⁺ half the width of the diffusion region 41, the width of the N ⁺ diffusion regions 43a and 43b, as shown in FIG. 7 of the N ⁺
This is half the width of the diffusion region 43. Thus, N-MO
By dividing S11 into two, the N ⁺ diffusion region connected to the power supply terminal Vcc can be made one, and the layout area can be saved. Although FIG. 9 illustrates an example in which the N-MOS 11 is divided into two, the number of divisions of the N-MOS 11 may be increased.

As described above, the semiconductor device according to the second embodiment is different from the semiconductor device according to the first embodiment in that the external terminal A1 is connected to the ground terminal GND and the external terminal B1 is connected to the ground terminal GND. Lateral transistors 51 and 52 were formed between them. For this reason, between the external terminal A1 and the ground terminal GND, and between the external terminal B1
From the static electricity applied between the
The MOS 11 can be protected. From this, it is possible to protect against static electricity between each of the external terminal A1 and the external terminal B1 and the ground terminal GND, and between each of the external terminal A1 and the external terminal B1 and the power supply terminal Vcc.
The protection from static electricity can be ensured without increasing the parasitic capacitance of the MOSFET forming the FET switch.

The first embodiment and the second embodiment
In the above, the case where the gate voltage of the N-MOSs 11 to 14 is controlled by the inverter 15 has been described as an example. However, this is an example, and the present invention is not limited to this.
The control may be performed by a logic circuit such as ND or NOR.

[0051]

According to the semiconductor device of the present invention, the switching operation is controlled by the logic circuit, and the gate of the field effect transistor forming the FET switch for controlling the connection between the external terminals by the switching operation is logically connected through the resistance element. A lateral bipolar transistor is provided between each external terminal and a first voltage supply terminal connected to an output of the circuit and supplied with a predetermined first constant voltage from the outside. From this, the field effect transistor can be protected from static electricity applied between each external terminal and the first voltage supply terminal, so that the field effect transistor forming the FET switch is more reliably protected from static electricity. be able to.

A semiconductor device according to a second aspect of the present invention is the semiconductor device according to the first aspect, specifically, a first impurity diffusion region formed on a semiconductor substrate and serving as a drain of a field effect transistor, and the first impurity diffusion region. And a third impurity diffusion region formed in parallel with a certain distance therebetween to form one lateral bipolar transistor, and a second impurity diffusion region serving as a source of a field effect transistor formed on a semiconductor substrate; One lateral bipolar transistor was formed by the second impurity diffusion region and a fourth impurity diffusion region formed in parallel at a predetermined distance. From this,
By connecting the third impurity diffusion region and the fourth impurity diffusion region to the first voltage supply terminal, the field effect transistor can be protected from static electricity applied between each external terminal and the first voltage supply terminal. Therefore, the field effect transistor serving as the FET switch can be more reliably protected from static electricity without increasing the parasitic capacitance.

According to a third aspect of the present invention, in any one of the first and second aspects, a lateral bipolar transistor is provided between each external terminal and the second voltage supply terminal. From this, furthermore, each external terminal and the second
Since the field effect transistor can be protected from static electricity applied to the voltage supply terminal, the field effect transistor forming the FET switch can be more reliably protected from static electricity.

According to a fourth aspect of the present invention, there is provided a semiconductor device according to the third aspect, specifically, a first impurity diffusion region formed on a semiconductor substrate and serving as a drain of a field effect transistor, and the first impurity diffusion region. And a fifth impurity diffusion region formed in parallel at a predetermined distance to form one lateral bipolar transistor, and a second impurity diffusion region forming a source of the field effect transistor formed on the semiconductor substrate; One lateral bipolar transistor was formed by the second impurity diffusion region and a sixth impurity diffusion region formed in parallel at a predetermined distance. From this,
By connecting the fifth impurity diffusion region and the sixth impurity diffusion region to the second voltage supply terminal, the field effect transistor can be protected from static electricity applied between each external terminal and the second voltage supply terminal. Therefore, the field effect transistor serving as the FET switch can be more reliably protected from static electricity without increasing the parasitic capacitance.

According to a fifth aspect of the present invention, in the semiconductor device according to the fourth aspect, the width of the third and fourth impurity diffusion regions is set to a predetermined value W1.
And the widths of the fifth and sixth impurity diffusion regions are made the same at a predetermined value W2 so that the predetermined value W2 is less than the predetermined value W1. From this, the predetermined values W1 and W2
Is optimized, the effect of protecting the field-effect transistor from static electricity can be enhanced between each external terminal and the first voltage supply terminal and between each external terminal and the second voltage supply terminal. .

According to a sixth aspect of the present invention, in the semiconductor device according to the third aspect, specifically, the plurality of first impurity diffusion regions electrically connected in series and forming a drain of the field effect transistor are electrically connected in series. And a plurality of second impurity diffusion regions which are connected to each other and form a source of the field effect transistor, and are formed in parallel with a certain distance between one of the first impurity diffusion regions and one of the second impurity diffusion regions. A field effect transistor is divided by forming a third impurity diffusion region on a semiconductor substrate, and one of the first impurity diffusion regions and one of the third impurity diffusion regions disposed adjacent to the first impurity diffusion region form one. A lateral bipolar transistor is formed, and one lateral bipolar transistor is formed by one of the second impurity diffusion regions and the third impurity diffusion region disposed adjacent to the second impurity diffusion region. Form was. Therefore, the third impurity diffusion region and the fourth impurity diffusion region constituting each lateral bipolar transistor of the first transistor circuit can be made one, and the area occupied by the impurity diffusion region on the semiconductor substrate can be reduced. Can be.

According to a seventh aspect of the present invention, in the semiconductor device according to the sixth aspect, specifically, one of the first impurity diffusion regions forming the drain of the field-effect transistor formed on the semiconductor substrate, One lateral diffusion transistor is formed by one impurity diffusion region and a fifth impurity diffusion region formed in parallel at a predetermined distance, and a second impurity formed on a semiconductor substrate and serving as a source of a field effect transistor One lateral bipolar transistor was formed by the diffusion region and a sixth impurity diffusion region formed in parallel with the second impurity diffusion region at a predetermined distance from the second impurity diffusion region.
For this reason, even when the second transistor circuit is provided, the third impurity diffusion region and the fourth impurity diffusion region constituting each lateral bipolar transistor of the first transistor circuit can be reduced to one, and the The area occupied by the impurity diffusion region can be reduced.

In a semiconductor device according to an eighth aspect, in any one of the first to seventh aspects, the resistance element is specifically set to about 100Ω to 500Ω. Accordingly, the field effect transistor can be protected from static electricity while suppressing a decrease in the switching operation of the field effect transistor.

[Brief description of the drawings]

FIG. 1 is a schematic diagram showing an example of a memory module using a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a schematic circuit diagram showing an example of an IC 4 of FIG.

FIG. 3 is a circuit diagram illustrating an example of the semiconductor device according to the first embodiment of the present invention;

FIG. 4 is a diagram showing an example of a layout of the N-MOS 11 and the lateral transistors 31 and 32 of FIG. 3;

FIG. 5 is a sectional view showing a section taken along the line AA ′ of FIG. 4;

FIG. 6 is a circuit diagram showing an example of a semiconductor device according to a second embodiment of the present invention.

7 is a diagram showing an example of a layout of the N-MOS 11 and the lateral transistors 31, 32, 51, and 52 of FIG. 6;

8 is a diagram illustrating another example of the layout of the N-MOS 11 and the lateral transistors 31, 32, 51, and 52 in FIG.

9 is a diagram showing another example of the layout of the N-MOS 11 and the lateral transistors 31, 32, 51, and 52 of FIG.

FIG. 10 is a schematic diagram showing a case where a memory module including a plurality of memory LSIs is mounted on a printed circuit board.

FIG. 11 is a circuit diagram showing a conventional example of an FET switch.

[Description of Signs] 1 memory module, 2 memory LSI, 4 I
C, 11-14 N-MOS, 15 inverters,
25 resistors, 31, 32, 51, 52 lateral transistors, 41 to 44, 41a, 41b, 43a,
43b, 61, 62, 71 to 73 N ⁺ diffusion region, 4
5 P-type substrate, 46, 46a, 46b gate electrode, A
1, B1 external terminal, Vcc power terminal, GND ground terminal.

Claims (8)

[Claims] 1. A semiconductor device that performs a switching operation in response to an external control signal, wherein at least one field effect transistor that controls connection between external terminals by the switching operation; A logic circuit for controlling a switching operation of the effect transistor, a resistor element provided between an output of the logic circuit and a gate of the field effect transistor, and a first constant voltage externally supplied with a first constant voltage. A semiconductor device comprising: a first transistor circuit including a lateral bipolar transistor provided between a voltage supply terminal and each of the external terminals. 2. The first transistor circuit, wherein: a first impurity diffusion region forming a drain of the field effect transistor; a second impurity diffusion region forming a source of the field effect transistor; A third impurity diffusion region formed in parallel with a distance of and having the same conductivity type as the first and second impurity diffusion regions and connected to the first voltage supply terminal; fixed to the second impurity diffusion region; Forming, on a semiconductor substrate, first and second impurity diffusion regions and a fourth impurity diffusion region of the same conductivity type, which are formed in parallel at a distance from each other and connected to the first voltage supply terminal. The semiconductor device according to claim 1, wherein: 3. A semiconductor device further comprising a second transistor circuit comprising a lateral bipolar transistor provided between a second voltage supply terminal to which a predetermined second constant voltage is externally supplied and each of the external terminals. The semiconductor device according to claim 1, wherein: 4. The second transistor circuit, wherein: a first impurity diffusion region forming a drain of the field effect transistor; a second impurity diffusion region forming a source of the field effect transistor; A fifth impurity diffusion region having the same conductivity type as the first and second impurity diffusion regions, being formed parallel to each other at a distance of and connected to the second voltage supply terminal; Forming a sixth impurity diffusion region of the same conductivity type as the first and second impurity diffusion regions, which are formed in parallel at a distance from each other and connected to the second voltage supply terminal, on the semiconductor substrate; The semiconductor device according to claim 3, wherein: 5. The width of the third and fourth impurity diffusion regions is made equal to a predetermined value W1, and the width of the fifth and sixth impurity diffusion regions is made equal to a predetermined value W2. 5. The semiconductor device according to claim 4, wherein the value is less than the value W1. 6. The first transistor circuit is electrically connected in series with a plurality of first impurity diffusion regions formed in parallel and electrically connected in series to form a drain of the field effect transistor. A plurality of second impurity diffusion regions alternately and in parallel with each of the first impurity diffusion regions forming a source of the field effect transistor; and one of the first impurity diffusion regions and the second impurity diffusion region. The first and second power supply terminals are formed in parallel at a predetermined distance from each other and connected to the first voltage supply terminal.
4. The semiconductor device according to claim 3, wherein the impurity diffusion region and a third impurity diffusion region of the same conductivity type are formed on a semiconductor substrate. 7. The second transistor circuit includes: a first impurity diffusion region disposed adjacent to a second impurity diffusion region formed in parallel with the third impurity diffusion region at a predetermined distance from the third impurity diffusion region; A fifth impurity diffusion region having the same conductivity type as the first and second impurity diffusion regions, the fifth impurity diffusion region being formed parallel to the first impurity diffusion region at a predetermined distance and connected to the second voltage supply terminal; A second impurity diffusion region disposed adjacent to the first impurity diffusion region formed in parallel with the third impurity diffusion region at a predetermined distance, and in parallel with the second impurity diffusion region at a predetermined distance from the second impurity diffusion region; The first and second impurity diffusion regions connected to the second voltage supply terminal are formed and a sixth impurity diffusion region of the same conductivity type is formed on a semiconductor substrate. The semiconductor device according to claim 6. 8. The resistance element according to claim 1, wherein the resistance element is 100Ω to 500Ω.
The semiconductor device according to any one of claims 1 to 7, wherein the semiconductor device is of the order of magnitude.