JP2000090237A - Plotting processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To accelerate processing in small circuit scale by performing optimum reloading control to a logic to be operated by a reconfigurable hardware composing a non-real time path and a real time path. SOLUTION: Based on processing contents and the size of image data to be processed, a path determining means 11 determines whether processing is to be performed by a real time path means 21 or non-real time path means 22. Image data inputted from an arithmetic unit and stored in an image data buffer belonging to an arithmetic unit I/F 23 are sent to the non-real time path means 22 and returned into the image data buffer after processing determined by the path determining means 11 is executed. The returned data are further sent to the real time path processing means 21, processing determined by the path determining means 11 is executed and data, to which the prescribed processing is completed, are sent through an output device I/F 24 to an output device 3 and printed out or displayed out.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a drawing process for executing processing of image data generated and input by a computer or the like, and executing drawing processing for conversion to data that can be displayed on a display or output by a printer. Related to the device.

[0002]

2. Description of the Related Art Conventionally, when an image generated by a computer is processed and displayed on a display screen or output to a printer, input data such as PDL (page description language) can be output by a printer or the like. A drawing process for converting to data is executed. In order to achieve a drawing processing speed corresponding to the output speed of recent high-speed printers,
Improving the processing speed has been an issue. In particular, in the case of a color image, it takes a lot of time to draw the image, so that a device for accelerating the processing speed is generally added.

For example, there are compression / expansion processing, rotation / enlargement processing, color correction and the like as modes of drawing processing of a color image.
The hardware added to improve the processing speed is generally called an accelerator. The use of the hardware accelerator enables higher-speed processing than software processing using an arithmetic processing unit of a computer. However, the disadvantage of hardware accelerators is that all the functions you want to accelerate need to be prepared in hardware. In addition to the processing functions required for the original drawing processing device, for example, a printer interprets PDL, develops an image, operates the printer, and monitors the normal termination. Will be needed. Therefore, there is a disadvantage that the circuit scale of the entire processing apparatus basically increases, though it depends on the number of functions to be supported.

As one technique for solving the above-mentioned problem of increasing the circuit scale, there is a technique described in JP-A-06-131155. The configuration described in this publication uses a programmable logic for an address generator block and an operation block and stores various image processing change data as a file, thereby changing a common programmable logic and supporting various image processing. It is.

In Japanese Patent Application Laid-Open No. 06-282432,
There has been proposed an apparatus that controls the flow of data for a combination of these arithmetic circuits in accordance with various types of processing, thereby performing various types of processing with a smaller number of arithmetic combinations, thereby reducing the size of the arithmetic circuit.

[0006]

However, in any of the above-mentioned conventional systems, there are great restrictions when performing image processing, and the circuit scale of the processing apparatus cannot be fully utilized. For example, a method in which a macro processing group required for predetermined image processing is registered in an arithmetic unit in a drawing processing apparatus, an instruction code input from the outside is temporarily decoded to generate an address, and an operation is selected and processed is as follows. This method is effective when the processing is a group of simple processing, but is inefficient in implementing complicated and many types of processing.

[0007] Further, installing a plurality of ALUs and performing parallel processing is one improvement. However, in the case of image processing, a pipelined system in which sequential processing is performed is suitable, and parallel processing is faster than general-purpose program processing. However, as a hardware accelerator, the effect is small for the scale.

In any case, these prior art configurations have special additional hardware for executing a part of the image processing separately from the processing functions necessary for the original drawing processing apparatus as described above. However, new hardware is added as the whole drawing processing apparatus, and it does not achieve the overall compactness. Also, as can be seen in the print processing, the order of processing is fixed, and if the entire operation is to be compacted by changing the data flow, a large memory is required for raster images, and the scale of the peripheral part is smaller than the compact operation part. It grows and does not lead to overall reduction.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems of the prior art, and integrate hardware that is essentially essential in a drawing processing apparatus with an accelerator function that accelerates exceptionally heavy processing. By configuring
An object of the present invention is to realize high-speed processing using integrated hardware having a small circuit scale. The processing performed by the integrated hardware is a raster processing that is time-consuming, especially in software. The rendering processing apparatus provided by the present invention has a small circuit scale of integrated hardware including a storage device, realizes a compact circuit processing scale of the entire rendering processing apparatus, and realizes sufficiently high-speed processing. Is what you do.

[0010]

In order to achieve the above-mentioned object, a drawing processing apparatus according to the present invention is constituted by reconfigurable hardware whose processing function is determined by the connection relation of internal elements, and converts raster image data. A rendering processing apparatus that processes input image data including the input image data and drives an output device; a real-time path unit that performs processing in synchronization with an image processing speed of the output device; Non-real-time path means for processing at a speed lower than the synchronization speed, and processing of the image data by the real-time path means or non-real-time processing based on the image processing size and processing contents of the input image data. Changed path determination means to determine whether to execute by path means and processing function of reconfigurable hardware And having a because of the rewrite control means.

Furthermore, in the drawing processing apparatus of the present invention,
The reconfigurable hardware is characterized in that processing is performed in units of bands obtained by dividing image data in a processing page.

Furthermore, in the drawing processing apparatus of the present invention,
The reconfigurable hardware includes an FPGA (Field Programmable Gate Array) as a component.

Further, in the drawing processing apparatus according to the present invention,
Storage capacity detection means for detecting the capacity of a storage device incorporated in the drawing processing apparatus; compression means for compressing raster image data as necessary based on the detection of the storage capacity detection means;
Decompression means for performing decompression processing corresponding to the algorithm used by the compression means, wherein at least some of the functions of the compression means and the decompression means are constituted by reconfigurable hardware. .

Further, in the drawing processing apparatus of the present invention,
The non-real-time path means reads the raster image data from the storage device in band units, executes the processing of the read raster image data in band units in reconfigurable hardware constituting the non-real-time path means, and processes the processed data. It is characterized by having a configuration for re-storing in a storage device.

Further, in the drawing processing apparatus according to the present invention,
The real-time path means reads the raster image data from the storage device in band units, executes the processing of the read raster image data in band units in reconfigurable hardware constituting the real-time path means, and outputs the processed data. It is characterized by having a configuration for sequentially outputting to a device.

Further, in the drawing processing apparatus according to the present invention,
The rewriting control means includes processing logic data for determining a non-real-time path means required for at least one-page processing of input image data and an internal element connection mode of reconfigurable hardware of the real-time path means, and one-page processing. Reconfigurable to configure the non-real-time path means or the real-time path means based on control data including non-real-time path means, processing procedure data in the real-time path means, and processing parameters attached to processing logic data as necessary. The reconfigurable hardware executes the reconfiguration of the hardware, performs the reconfiguration based on the control data, and executes the processing of the input image data.

Further, in the drawing processing apparatus of the present invention,
The drawing processing apparatus executes processing of an image in one page with respect to input image data in a non-real-time path unit, stores the processed data in a memory, and transfers the processed data in the non-real-time path unit stored in the memory to a real-time path. Characterized in that it has a configuration for processing in.

Further, in the drawing processing apparatus of the present invention,
When the processing logic data has a plurality of raster data in the area of the processing unit in the non-real-time path means or the real-time path means, the processing logic data is formed by a series of tables in which the processing logic data of each individual raster data included in the area are linked. It is characterized by being constituted.

Further, in the drawing processing apparatus of the present invention,
The rewriting control means configures rewriting control data in units of processing modules obtained by decomposing a series of image processing of input image data into a plurality of processing modules, and the rewriting control means gates an FPGA that constitutes reconfigurable hardware. The rewriting of the FPGA is controlled based on the combination of the processing modules corresponding to the value converted into the size, and the rewriting-controlled FPGA is configured to collectively execute the combination of the processing modules based on the rewriting. .

Further, in the drawing processing apparatus according to the present invention,
The reconfigurable hardware has a configuration in which image data stored in a storage device in the drawing processing apparatus is sequentially read and executed, and two or more band buffers are provided between the storage device and the reconfigurable hardware. And the data transfer from the storage device to the reconfigurable hardware is executed via the two or more band buffers.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A system to which a drawing processing apparatus according to the present invention is applied includes, for example, an arithmetic unit for generating drawing data such as PDL, an integrated drawing processing apparatus for processing drawing data, and display of processed data. An output device for executing printing; more specifically, a path determination unit for determining a path of a drawing process in a drawing processing device or the like, an image transfer unit, an arithmetic unit I / F, a storage device, a real-time path image processing unit, Real-time path image processing means,
It is composed of an output device I / F and the like.

The non-real-time path image processing means executes processing without synchronizing with the speed required by the output device. The non-real-time path image processing means includes a reconfigurable hardware FPGA and a reconfigurable hardware configuration. Changes,
That is, it has a rewriting control unit for executing rewriting, a work memory, and return switching means. The real-time path image processing means outputs the processed result at the speed requested by the output device, and therefore performs processing in which the processing speed is synchronized with the output speed of the output means. The configuration has a function in which the return switching means is omitted from the non-real-time path image processing means.

The data sent from the arithmetic unit includes image data to be processed, processing path order information which determines in advance whether processing is performed in a non-real-time path or in a real-time path, processing logic data for sequentially rewriting an FPGA, and , As necessary. The rewriting control has a function of receiving a signal for operating in synchronization with image data. Hereinafter, embodiments of a drawing processing apparatus according to the present invention will be described in detail with reference to the drawings.

[0024]

FIG. 1 shows an example of a configuration of a system using a drawing processing apparatus according to the present invention. In FIG. 1, an arithmetic unit 1 is, for example, an arithmetic unit 1 such as a computer.
A display format including characters, graphics, raster data, and the like such as a document and GDI is created in a PDL such as a script. The data created by the arithmetic unit 1 is input to the integrated drawing processing unit 2. The integrated drawing processing device 2 executes a process of converting the data into bitmap data that can be output by a display device to which data is output or an output device 3 such as a printer. The output device 3 is a display or a printer for displaying or printing data processed by the processing device 2 for the integration seconds.

FIG. 2 is a block diagram showing in detail a configuration centering on the integrated drawing process 2 in the system configuration of FIG. As shown in FIG. 2, the drawing processing device in the present system includes an arithmetic device I / F 23 for connecting to the arithmetic device 1.
And an output device I / for connecting to the output device 3
F24 and a real-time path processing means 21 for processing the image data received from the arithmetic unit at a required speed of the output device or at a speed required for visualizing the image data.
And a non-real-time path processing means 22 for processing at a speed lower than the requested speed.

Here, the real-time path processing means and the non-real-time path means will be briefly described. The processing executed by the drawing processing apparatus includes various processing such as data compression processing, data expansion processing, enlargement processing, filter processing, rotation processing, and color conversion processing.
These processes take time depending on the content of the process,
There are various types, such as those that can be done in a short time. These multiple processes are executed and finally output to the output device. An output speed at an output device, for example, a print speed is generally a constant speed, and among the above various processes, a process capable of performing a process at a speed synchronized with the print speed is performed in the above-described real-time path. Even though the printing speed is not delayed, it is necessary to perform processing using a non-real-time path to generate processing data in advance for processing having a long processing time. The real-time path processing means and the non-real-time path means are processing paths for executing these processes, respectively.

Image data such as PDL created by the arithmetic unit 1 is temporarily stored in an image data buffer (not shown) attached to the arithmetic unit I / F 23. The control information for the smooth operation of the drawing processing device of the present invention is calculated by the arithmetic unit I.
/ F, via the rewrite control data generating means 12
Sent to The path determination unit 11 determines which of the real-time path unit 21 and the non-real-time path unit 22 should perform each process based on the processing content of the drawing processing apparatus and the size of the image data to be processed. Input from the arithmetic unit 1 and the arithmetic unit I
The image data stored in the image data buffer attached to / F, 23 is sent from the image data buffer to the non-real-time path processing means 21. The non-real-time path processing means 21 executes the processing determined by the path determining means 11, and the processing data is temporarily returned to the image data buffer. Non real-time path processing means 21
Is completed, and the data returned to the image data buffer is further sent to the real-time path processing means 22 to execute the processing in the real-time path processing means determined by the path determination means 11, The processed data is sent to the output device 3 via the output device I / F 24, and is printed out or displayed on the display.

FIG. 3 is a diagram for explaining the flow of processing in the arithmetic unit 1 in FIG. As shown in FIG. 3, a document created based on various applications is converted into PDL and input to the PDL input unit 101. The elements required for drawing by the lexical analysis unit 102 are PD
L, and rearrangement is performed for each processing area. In the case of the page unit processing, the page is divided into a plurality of band areas and the page is rearranged when the processing is executed in a unit of a band, and when the processing is executed in a band unit.

In the case of processing in units of bands, the drawing element in each band division area is determined by the character / raster processing division unit 103 whether the drawing element is vector information mainly composed of a character figure or a photograph or bitmap. Recognize whether it is raster information. If the recognized information is vector information, it is sent to a vector information processing unit (not shown).

When the recognized information is raster information, image information and processing information on what processing is to be applied to the raster image information are attached. The drawing processing apparatus of the present invention performs the following processing based on the information.

The calculation load database 112 previously stores data of the CPU processing speed per unit when processing is performed by the CPU and the hardware processing speed per unit processed by reconfigurable hardware in the drawing processing apparatus. ing. The raster processing load calculation unit 111 determines a raster processing path from the information in the calculation load database 112 and the amount of image data calculated per calculation unit.
The unit of calculation depends on the processing method. For example, when processing is performed in a unit of one page, in the case of JPEG decompression, 8 × 8
Is the calculation unit, and the processing time can be calculated based on the number of calculation units in one page unit. When one page is divided and processed in a certain area size, in the case of JPEG decompression, the processing time that must be guaranteed by the area size in addition to the 8 × 8 matrix size is a unit of calculation.

The processing of the raster processing path determination unit 113 will be described. There are three types of raster processing paths: a path that uses the CPU of the arithmetic device, a real-time path that uses reconfigurable hardware, and a non-real-time path. The real-time path is followed by the real-time path.

A raster processing path is determined based on information from the raster processing load calculation unit 111. The calculation load database 112 includes an output request speed when outputting to an output device such as a printer, a maximum time necessary for one-band processing so that a bottleneck such as a failure to output to an output device in time during processing or the like occurs. Is stored in advance. Also stored are an overhead time required for rewriting control, an image data read time required for processing, and the like.

Here, as a specific processing example, 90-degree rotation, enlargement processing, digital filter processing,
And a case of performing color conversion processing. In the case of a process requiring a large amount of work memory, such as a 90-degree rotation process, or a very simple process, the process is basically performed by the CPU. When the contents of such CPU processing are determined, next, the raster processing path determination unit 113 determines whether to execute the remaining processing in the non-real-time path or the real-time path.

As described above, since the 90-degree rotation is performed by the arithmetic unit, the remaining three operations are the enlargement process, the color conversion process, and the digital filter process. For these processes, the raster processing path determination unit 113 determines a processing path. In addition to the processing load calculated by the raster processing load calculation unit 111, the processing order is determined based on the content of the processing. In this case, the processing is optimally performed in the order of enlargement, digital filter, and color conversion. When determining the processing path, first determine what can be done with the real-time path, and then make the remaining processing the processing with the non-real-time path. Here, the color conversion processing is a real-time pass. The rest is processed on the non-real-time path. When the processing path is determined in this way by the raster processing path determining unit 113, the raster processing path determining unit 113 transmits the rewriting control data necessary for generating the rewriting control data for performing the processing according to the determined processing procedure. Read from the rewrite database 114.

The arithmetic unit I / F 23 in FIG.
A storage device capable of storing an image of a page is built in.
It is more efficient to store the compressed image in order to reduce the size of the storage device. The image transfer means 13 is provided with an arithmetic unit I /
F, The capacity of the storage device for storing image data in 23 is detected through the communication line. The image data size to be transferred is compared with the capacity of the storage device, and the image data is compressed by the image transfer means 13 if necessary, and the compressed image data is transferred to the arithmetic unit I / F 23. The compression algorithm information used in the image transfer means 13 is held and added to the rewrite control data separately from the image processing command attached to the PDL as input image data and transmitted to the drawing processing device. The drawing processing device can perform appropriate decompression processing based on this information.

The rewrite control information necessary for operating the reconfigurable hardware in the drawing processing apparatus is read from the rewrite database 114 and rearranged according to the processing order determined by the raster path determination unit 113. The data is loaded from the arithmetic unit I / F 23 to the rewrite control data generating means 12.

Hereinafter, as a specific processing example, image data to be drawn is subjected to a compression process, the compressed image data is subjected to a decompression process by a non-real-time path, and further, an enlargement process and a digital filter process are performed. An example will be described with reference to FIG. In FIG. 4, the reconfigurable hardware is FPGA (field programmable gate array) 212, 222.
And rewrite control means 213 and 223 for rewriting hardware. Work memories 211 and 221 and FPGAs 212 and 222,
Although the rewrite controllers 213 and 223 are shown as two different configurations in the figure, the non-real-time paths (the work memories 221 and F
The PGA 222 and the rewrite control unit 223) and the real-time path (the work memory 211 and the FPGA 212 and the rewrite control unit 213) are shown separately, and the same physical configuration may be commonly used in an actual device. It is possible.

First, a part of the image data generated in the arithmetic unit or the like and input to the drawing processing unit is transferred to the work memory 221 via the arithmetic unit I / F 23 shown in FIG.

FP constituting reconfigurable hardware
The GA 222 is first rewritten by the rewriting control means 223 to a configuration for executing the decompression process.

The FPGA 222 which has been rewritten by the rewriting control means 223 to execute the decompression process executes the decompression process of the image data. The image data undergoing the decompression processing is judged by the return switching means 224 based on a signal (not shown) from the rewriting control that the non-real-time path processing has not been completed yet.

The result of the image data decompression processing performed by the FPGA 222 is stored in the work memory 221. F
When the decompression processing by the PGA 222 is completed, the FPGA
222 is rewritten as enlargement processing means under the control of the rewriting control means 223. The expanded data is sent from the work memory 221 to the rewritten FPGA 222 as the enlargement processing means, and the enlargement processing is performed. The result of the execution of the enlargement processing is further sent to the return switching means 224. Return switching means 22
4 stores the processing data in the work memory 221 again.

Next, the FPGA 222 is rewritten as digital filter processing means under the control of the rewriting control means 223. The enlarged data is sent from the work memory 221 to the rewritten FPGA 222 as digital filter processing means, and the FPGA 222 performs digital filter processing. If there is not enough size due to the size of the storage device of the arithmetic unit I / F 23, and there is not enough capacity to accumulate the processing result, the compression
This is performed by the PGA 222. The return switching unit 224 determines that the processing of the non-real-time path has been completed, and accumulates the processing data in the storage unit of the arithmetic unit I / F, 23.

The storage capacity of the storage device of the arithmetic unit I / F 23 can be recognized in advance by inquiring from the arithmetic unit to the arithmetic unit I / F, and it can be determined from the image data size to be processed whether compression / expansion processing is necessary. When a series of non-real-time processing for one image data area is completed, the next area of the image data is stored in the work memory 2.
21, the work memory 221, the FPGA 222,
The same non-real-time path processing is repeated in the rewrite control means 223 and the return switch 224, and the processing data is accumulated in the storage device of the arithmetic unit I / F 23.

When the processing of the non-real-time path is completed, the processing shifts to the processing of the real-time path. In FIG. 4, the real-time paths are the work memory 211, the FPGA 212,
It is constituted by rewriting control means 213. As described above, in FIG. 4, the work memory, the FPGA, and the rewrite control unit have different numbers in the real-time path and the non-real-time path. The same can be used. In a configuration in which the non-real-time path and the real-time path are operated in a pipeline manner, different hardware may be used. In the real-time path, the data is sequentially read out from the storage device of the arithmetic unit I / F 23 into the work memory 211 for each predetermined area such as a processing band, and if the data is compressed, first, the FP
The GA 212 is rewritten by the rewriting control means 213 as decompression processing means, and decompression processing is executed. Further, the FPGA 212 is rewritten by the rewriting control means 213 as color conversion processing means, color conversion processing is executed, and the processed data is output. Output to the device I / F, 24. By repeating these series of processes, all the image data are processed and output to the output device 3 via the output device I / F 24.

The image sent from the arithmetic unit is divided into processing units of the drawing processing unit and the processing is executed. If the processing unit is one page, compression processing in page units is performed. If the processing unit is a band unit divided by a certain area, compression is performed in band units and stored in the storage device of the arithmetic unit I / F 23. The non-real-time or real-time path processing is performed in the same processing unit. When the processing is performed in band units, the work memory needs at least one band of storage capacity. If there is a storage capacity of two or more bands, reading and processing of a plurality of bands are performed in parallel, so that the operation speed of the processing is improved.

Next, the rewriting control means will be described with reference to FIG. The rewriting control means has a start / switch control unit 2131, a rewriting control unit 2132, and a rewriting wiring data unit 2133. Start / switch control unit 2131
Outputs the timing at which processing is started or changed in the FPGA and the processing content to the rewrite control unit 2132, and the rewrite control unit 2132 outputs necessary change data according to the processing content to the rewrite control wiring data unit 2133, The rewrite control wiring data unit 2133 outputs necessary wiring data to the FPGA according to the processing content.

FP constituting reconfigurable hardware
Elements represented by a GA (field programmable gate array) are electrically determined by wiring data in which internal wiring is externally loaded. As long as the determined state is maintained electrically, the wiring is kept constant. This FPGA is capable of rewriting a part of the open wiring even when a part of the wiring is used, and has a characteristic that the entire rewriting and the partial rewriting are performed at high speed.

The FPGA has a built-in SRAM memory element, which differs depending on the FPGA element. The FPGA has a parallel interface and loads wiring data from an external memory to the internal SRAM, so that the FPGA can be rewritten as an element for executing enlargement processing. , It is possible to rewrite the element to perform the expansion processing. In some processes, a portion for generating a register is included in the wiring data. In a process requiring a parameter, the parameter is also loaded into the register. Assuming that the processing capacity of the entire FPGA is 100,
When only 50 is used in a certain process, the remaining 50 unused FPGs are executed when the process is executed at 50.
The following processing configuration can be written to A.

The rewriting control means 213 and 223
It is necessary to consider the gate conversion size of the GA element, rewrite data necessary for image processing, related parameters, rewrite timing, the number of bands, the number of target image data, and the like in control. FPGA depending on the content of processing
There is a case where the gate conversion size required for image processing is larger than the gate conversion size of the above. In such a case, one image processing is divided into two or more and written to the FPGA, and in the case of two, the first half processing and the second half processing are divided. Is processed.

When processing is performed in band units in the FPGA, the same processing is repeated for the number of bands. In many cases, the same processing is repeated to perform rewriting and operation. Therefore, by adding repetitive control, a memory for storing rewriting wiring data is reduced. FIG. 6 shows an example of a table as a result of generating the rewrite control data.

FIG. 6 shows an example of an FPGA rewrite data table for executing the processing on the non-real-time path (NR) and the real-time path (R) by rewriting the FPGA according to the processing. The example shown in FIG.
Two types of image data (image 1 and image 2) are sent to a page as processed image data (PDL), and different processing is performed on these two images between a non-real-time path (NR) and a real-time path (R). This is an example of output.

The tables are arranged in an order in which they can be sequentially loaded into the FPGA. First, processing for the first image data (image 1) from the table is described.
The number of repetitions NR indicates the number of repetitions in the non-real-time path. The number of repetitions indicates the number when the raster image is divided into bands. Regarding the repetition number NR, the decompression process executed first is divided into the first half and the second half, and recorded in the rewrite data table. Further, enlargement processing as processing A and rewriting data of a filter as processing B are described. Further, the second image data and processing data for image 2 follow. Similarly, the number of repetitions in the non-real-time path is written, and processing E follows. The configuration of the FPGA constituting the non-real-time path is rewritten in the order in which it is written in this table, the configuration is changed to a configuration corresponding to each process, and each process is executed.

In the rewrite data table, a table in the real-time path is recorded following the first half of the FPGA configuration of the image 1 and the image 2 in the non-real-time path. First, the repetition number R of the image 1 in the real-time path is written. Further, there are written the color conversion and its parameters, which are expansion processing executed in the real-time path, processing C, and rewriting data of expansion processing, which is processing D that is not described in PDL but is required from the memory size. Further, the repetition number R of the real-time pass and the expansion processing for the image 2 are described. The number of repetitions of the table is used by the rewrite control as information on whether it is non-real-time or real-time and timing information for switching control. In the rewrite control section, the rewrite control data is used as rewrite wiring data, start / switch control, and rewrite control information.

Referring to FIG. 7, the processing flow of the drawing processing apparatus of the present invention will be described. The image data compressed by the arithmetic unit (FIGS. 1 and 1) is accumulated for one page in the drawing processing unit (step 701). One page may include a plurality of different images. The rewrite control data generated by the rewrite control data generation means (FIGS. 3 and 12) in the arithmetic unit is set from the image transfer means (FIGS. 3 and 12) to the rewrite control unit (FIGS. 4, 213 and 223) in the drawing apparatus. (Step 702), and the process starts.

The band generated on the computing device side is, for example, 1
Divide the page into 32. A4 size 297mm long
Is evenly divided into 32, the width of one division is about 9.3 mm. In the case of processing two 100 mm × 100 mm images, the image is divided into 11 bands, depending on the start position of the image. Since the compressed image data is compressed and stored in band units, a total of 22 bands of compressed image data are stored.

Here, processing is performed by a non-real-time path. Work memory for the first band (Fig. 4, 221)
(Step 703). The size of the work memory 221 has a capacity capable of storing an uncompressed one-band image size. The rewrite control 223 loads the decompression processing into the FPGA 222 (step 704), and
A is configured to execute decompression processing, and the work memory 22
1 is expanded (step 705). If the entire decompression algorithm cannot be accommodated in the FPGA 222, the data in the work memory 221 is divided into a first half processing unit and a second half processing unit, and the decompression processing in the FPGA 222 is repeated twice.
The result of executing each process is stored again in the work memory (step 707). When the processing is completed, the next processing (enlargement) is loaded (steps 706 and 70).
7) Execute the processing and store the result in the work memory. Next, a process (digital filter) is loaded, the process is executed, and the result is stored in the work memory. Next, the processing (compression) is loaded, the processing is executed, and the result is loaded not into the work memory but into the storage device in the arithmetic unit I / F.

In the rewriting control data, a series of processing within one band is delimited until a new repetition number appears after the repetition number. The appearance of this data determines the delimitation. One band ends (step 7)
When the determination is Y in step 06), the next band data is loaded into the work memory (steps 708, 709, and 703). Then, the same operation is repeated. When the number of bands 11 indicated by the number of repetitions ends, the processing shifts to non-real-time processing of the second image data. Processing is performed in the same manner as the first image data, all 22 bands are completed, and the compressed data is stored in the storage device.

Next, the processing shifts to a real-time path. FIG. 8 shows the processing flow of this real-time path. The operation of the real-time path is basically the same as that of the non-real-time path, and the detailed processing procedure is the same as the procedure described in FIG. The difference from the flow in the non-real-time path of FIG. 7 is that, when the real-time processing of one band is completed, the data is sent not to the storage device but to the output device I / F (FIG. 4, 24).

The output device I / F 24 has a built-in timing absorption buffer memory for connecting data output from the drawing processing device to the device, and has a function of converting the data into a format required by the output device 3. Output device 3
May be xerographic color printers or high resolution color displays.

When the processing shifts from the non-real-time processing to the real-time path, the image data accumulation and rewriting control set has already been completed. Therefore, one band of the first processed image is loaded into the work memory, and the decompression process is loaded by rewriting control. The processing is executed and stored in the work memory, then the color conversion processing and its parameters are loaded, and the result is transferred to the output device I / F. When the eleventh band processing of the first image is completed, the processing of the second image data is performed in the same manner, transferred to the output device I / F, and the processing ends.

FIG. 9 shows the positions of images 1 and 2 included in the PDL constituting the image processing data of one page, and for image 1, the band boundaries appearing in the description of the text are indicated by virtual lines. , The direction of processing when outputting to a device. In the example shown in FIG. 9, two images, image 1,
Image 2 does not fall on the same band boundary, but images may overlap in various documents. In that case, two types of processing will occur in one band, but the rewrite control data and the number of repetitions should be described separately for the case of processing one type of image in one band and two types of images in one band. Allows processing in the same manner. Also, the calculation of the raster processing load performed by the arithmetic unit can be performed by the same method by summing the loads of two processes per band.

FIG. 10 shows an example of the configuration of the drawing processing apparatus according to the present invention, mainly using hardware. The storage device 301 is composed of a semiconductor memory DRAM. 400 dpi,
For a color image represented in A4 size, 8 bits for each color of RGB, 16 Mbytes or 3 in consideration of the compression ratio, etc.
It has a capacity of 2 Mbytes. There are two band buffers, a band buffer 1 302 and a band buffer 303, each having 2 Mbytes of capacity based on the expanded band data amount.

The operation will be described using a processing example of a real-time path. The first band is read from the storage device 301 to the band buffers 1 and 302, and the rewrite control 304
The data is sent from the band buffers 1 and 302 to a certain image processing function based on the internal wiring data written in A305. The wiring circuit of the FPGA 305 has an image processing operation parallel / pipeline 3051 configuration having parallel processing and pipeline processing functions in order to realize high-speed raster processing. The FPGA 305 processes the image data one after another and writes the result to the band buffers 3 and 307.
In the meantime, the band to be processed next is read from the storage device 301 to the band buffers 2 and 303 as temporal parallel processing.

The data processed by the FPGA 305 is written to the band buffers 3 and 307, and at the same time, the data of the band buffers 2 and 303 is sent to the FPGA 305, and the data of the band buffers 3 and 307 processed in the same manner as the band buffers 1 and 302 are The signal is returned to the band buffers 1 and 302 through the multiplexer 308. When processed, the data in the band buffers 2 and 303 is stored in the band buffers 3 and 307. The wiring data of the FPGA 305 is changed by the rewriting control 304 to wiring data corresponding to the next processing. The data in the band buffers 3 and 307 is returned to the band buffers 2 and 303. Next, data is input from the band buffers 1 and 302 to the FPGA 305, and predetermined processing is executed.
To be accumulated. When the processing of band 1 is completed, the data of band buffers 3 and 307 are output from multiplexer 308 through output device I / F 309.

The data in the band buffers 2 and 303 is FP
The image data is input to the GA 305, a predetermined image processing is executed, and the image data is stored in the band buffers 3 and 307. In parallel, the information of the third band is written from the storage device 301 to the band buffers 1 and 302. When the processing of the band buffers 3 and 307 is completed, the data is output through the multiplexer 308 and the output device I / F 309. FPG
The wiring data of A305 is changed by the rewrite control, and the process is repeated.

The non-real-time processing will be described with reference to FIG. In the real-time processing, when the processing is completed, the data is sent to the output device via the multiplexer 308. In the non-real-time processing, when the processing is completed, the band buffer 1, 302 or the band buffer 2,
The band data is returned to 303, subjected to compression processing by the FPGA 305, and stored in the band buffers 3, 307, and transferred to the storage device 301 from the multiplexer 308.

The internal register 3052 has a function of temporarily holding parameters and the like formed by internal wiring data. A work memory 306 connected to the FPGA 305 is a memory for securing a work area required in an image processing operation process.
It is also possible to realize it inside A.

In the first embodiment, the wiring information to the FPGA has been described in units of image processing. However, a series of processes using the FPGA need not always be performed in image processing units.
FIG. 11 shows a description of the entire process at the block level.
Each process consists of a plurality of detailed processes. For example, compression can be decomposed into Huffman coding, discrete cosine transform, raster conversion, etc. in the JPEG system, and enlargement can be decomposed into affine transformation and coordinate interpolation.
The decomposed process is called a module. It can be converted into the number of hardware gates for each module, and rewrite control data can be created for each module. In this process, the order of the modules cannot be changed.

The FPGA is, for example, 200 k gate-converted hardware. In processing units, enlargement is equivalent to 50 k gates, and digital filter is equivalent to 70 k gates. It is possible to load the processing until a total value of a plurality of modules reaches close to 200 k gates into one FPGA and execute the processing of the plurality of modules at the same timing as a unit in a module. The optimal gate-converted size of the FPGA can be determined from the combination of the modules for processing performed by the FPGA. If this idea is applied, in the example of FIG. 11, if the non-real-time path is rewritten in processing units and the processing is executed, half of the rewriting processing is required, compared to four rewritings. As a result, by performing the rewrite control data on a module basis, the use efficiency of the FPGA is increased, and the number of times of read / write of the work memory and the number of rewrite controls are reduced, thereby improving the overall processing speed.

[0071]

As described above, according to the drawing processing apparatus of the present invention, in the processing of input image data, a large number of processing logics operating on reconfigurable hardware constituting a non-real-time path and a real-time path are prepared. By performing the rewriting optimally according to the hardware configuration of the hardware that can reconfigure these processing logics by the rewriting control means, it is possible to perform many raster image processes at a smaller hardware scale and at a higher speed than software. .

Further, according to the drawing processing apparatus of the present invention,
Both the non-real-time path and the real-time path share the common reconfigurable hardware, and the processing logic required for a series of image processing is rewritten as table data combining the non-real-time path and the real-time path. The control means can execute the rewriting of the FPGA based on this table, and the efficiency of the rewriting process is achieved.

Further, according to the drawing processing apparatus of the present invention,
The rewriting control unit recognizes a series of image processing as a module and, based on the gate conversion number of the FPGA, appropriately combines the modules to rewrite the FPGA and executes the processing, thereby realizing an efficient processing flow using the FPGA. This makes it possible to speed up processing and use hardware resources efficiently.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an example of a system to which a drawing processing apparatus according to the present invention is applied.

FIG. 2 is a diagram showing main functional blocks of the drawing processing apparatus of the present invention.

FIG. 3 is a block diagram showing a configuration of an arithmetic unit in a system to which the drawing processing apparatus of the present invention shown in FIG. 1 is applied.

FIG. 4 is a configuration block diagram of a drawing processing apparatus of the present invention.

FIG. 5 is an internal block diagram of a rewriting control unit in the drawing processing apparatus of the present invention.

FIG. 6 is a structural example of a rewrite data table in the drawing processing apparatus of the present invention.

FIG. 7 is a diagram showing a processing flow of a non-real-time path in the drawing processing apparatus of the present invention.

FIG. 8 is a diagram showing a processing flow of a real-time path in the drawing processing apparatus of the present invention.

FIG. 9 is a diagram showing an example of band division in the drawing processing apparatus of the present invention.

FIG. 10 is a diagram illustrating an example of a hardware configuration of a drawing processing apparatus according to the present invention.

FIG. 11 is a diagram illustrating an example of a module configuration of reconfigurable hardware in the drawing processing apparatus of the present invention.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 arithmetic unit 2 integrated drawing processing unit 3 output device 11 path determination unit 12 rewrite control data generation unit 13 image transfer unit 21 real-time path unit 22 real-time path unit 23 arithmetic unit I / F 24 output device I / F 101 PDL input unit 102 lexical analysis unit 103 character / graphic / raster processing division unit 111 raster processing load calculation unit 112 calculation load database 113 raster processing path determination unit 114 rewrite database 211, 221 work memory 212, 222 FPGA 213, 223 rewrite control unit 224 return switching unit

Claims (11)

[Claims] 1. A drawing processing apparatus configured by reconfigurable hardware whose processing function is determined by the connection relation of internal elements, processes input image data including raster image data, and drives an output device. A real-time path means for making the configurable hardware a component and performing processing in synchronization with the image processing speed of the output device; and a non-processing device for making the reconfigurable hardware a component and performing processing at a speed lower than the synchronization speed Real-time path means; path determination means for determining whether to execute the processing of the image data by the real-time path means or the non-real-time path means based on the image processing size and processing content of the input image data Rewriting control means for changing the processing function of the reconfigurable hardware; Drawing processing apparatus characterized by having a. 2. The drawing processing apparatus according to claim 1, wherein the reconfigurable hardware performs processing in units of bands obtained by dividing image data in a processing page. 3. The reconfigurable hardware is an FPG
2. The drawing processing apparatus according to claim 1, wherein A (field programmable gate array) is a constituent element. 4. A storage capacity detecting means for detecting a capacity of a storage device incorporated in the drawing processing apparatus; a compression means for compressing raster image data as required based on the detection of the storage capacity detecting means; Decompression means for executing decompression processing corresponding to the algorithm used by the compression means, wherein at least a part of the function of any one of the compression means and the decompression means is constituted by the reconfigurable hardware. The drawing processing apparatus according to claim 1, wherein: 5. The non-real-time path means reads the raster image data from the storage device in band units, and processes the read raster image data in band units in a reconfigurable hardware which constitutes the non-real-time path means. 5. The drawing processing apparatus according to claim 4, wherein the drawing processing apparatus is configured to execute the processing in hardware and re-store processing data in the storage device. 6. The real-time path means reads raster image data from the storage device in band units,
The system according to claim 1, wherein the processing of the read raster image data in band units is executed in reconfigurable hardware constituting the real-time path means, and the processed data is sequentially output to the output device. 5. The drawing processing apparatus according to 4. 7. The processing logic for determining a mode of connection of internal elements of reconfigurable hardware of the non-real-time path means and the real-time path means required for processing at least one page of input image data. The non-real-time path means required for the one-page processing, the processing procedure data in the real-time path means, and processing parameters attached to the processing logic data as necessary. Performing real-time path means or reconfiguration of reconfigurable hardware constituting the real-time path means; the reconfigurable hardware is reconfigured based on the control data; 2. The drawing process according to claim 1, wherein the process is executed. Location. 8. The non-real-time path means executes processing of an image in one page with respect to input image data, stores the processed data in a memory, and stores the non-real-time data stored in the memory. 2. The drawing processing apparatus according to claim 1, further comprising a configuration for processing the processing data in the path unit by the real-time path. 9. When the processing logic data includes a plurality of raster data in an area of a processing unit in the non-real-time path means or the real-time path means, the processing logic for each raster data included in the area is provided. 8. The drawing processing apparatus according to claim 7, wherein the drawing processing apparatus is configured by a series of tables in which data is linked. 10. The rewrite control means configures rewrite control data in units of processing modules obtained by decomposing a series of image processing for the input image data into a plurality of processing modules, and the rewrite control means is configured to be capable of performing the reconfiguration. The rewriting of the FPGA is controlled based on a combination of the processing modules corresponding to a value obtained by converting an FPGA constituting a hardware into a gate size, and the rewriting-controlled FPGA is a combination of the processing modules based on the rewriting. 8. The drawing processing apparatus according to claim 7, wherein the processing is performed collectively. 11. The reconfigurable hardware has a configuration for sequentially reading out image data stored in a storage device in the drawing processing apparatus and executing a process, and the reconfigurable hardware includes the storage device and the reconfigurable hardware. 2 between wears
2. The drawing process according to claim 1, further comprising the band buffer described above, wherein the data transfer from the storage device to the reconfigurable hardware is executed via the two or more band buffers. apparatus.