JP2000089672A - Enciphering circuit and random password generation circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve a system security level by appropriately controlling appearance probabilities of '1' and '0' in a cryptographic key or a password generated at random, and creating a very difficult cryptograph to decipher. SOLUTION: A resistance R12 and a capacitor C5 compose a stabilizing integrator which integrates the reversing signal of a cryptographic key output of D flip flop F1, and the integrated signal is adjusted in the gain by an operational amplifier A4, and inputted to a Schmitt-trigger circuit which discriminates the white noise by level. While adjusting the gain of the voltage integrated by the stabilizing integrator by the operational amplifier A4, the appearance probabilities of '1' and '0' are equalized by controlling an operational amplifier A3 by feeding back, and controlling the reference level voltage of the Schmitt- trigger circuit. The appearance probability of '1' or '0' which may continuously appears is limited by the time constant of the stabilizing integrator composed of the resistance R12 and the capacitor C5.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an encryption technique used for information security in computer systems, communications and databases, and more particularly to an encryption circuit suitable for an information security IC (integrated circuit) card and the like. The present invention relates to a random password generation circuit.

[0002]

2. Description of the Related Art As means for ensuring information security in computer systems, communications and databases, information is encrypted and stored or transmitted. In this encryption, encryption is performed by using a random encryption key while sequentially changing the encryption key, thereby improving security.

Conventionally, in an encryption circuit for performing this type of encryption, white noise due to an avalanche effect based on reverse bias of a PN junction, that is, avalanche noise, is used to generate a random encryption key. In other words, a random encryption key can be obtained by discriminating such white noise at a reference level and binarizing the same, and extracting the binary signal in synchronization with a predetermined timing.

By the way, in a conventional encryption circuit,
The control of the encryption key pattern was not performed by simply obtaining the random encryption key from the white noise and by adding a specific restriction to the pattern of the random encryption key itself. For this reason, the appearance probabilities of “1” and “0” in the encryption key are not uniform, and a large number of “1” or “0” may appear continuously.

[0005]

As described above, if a large number of "0" s or "1s" appear continuously in an encryption key generated from white noise, if the encryption algorithm is simple, The output may be in a state that can be easily decrypted or partially not substantially encrypted.

For example, an input plaintext (data in an unencrypted state before or after encryption is referred to as “plaintext”) is encrypted by a simple algorithm that is simply inverted with an encryption key. However, if the encryption key changes frequently between "0" and "1", it is not easy to decrypt the contents unless the encryption key itself is known.

However, when the input plaintext is encrypted by simply inverting it with the encryption key, if "0" or "1" appears continuously in the encryption key, the plaintext is included in a part of the data. As a result, there is a portion that is output as it is or as it is inverted. In such a case,
For example, even if the communication content is encrypted, a part of it is easily read.

The present invention has been made in view of the above-mentioned circumstances, and appropriately controls the appearance probabilities of “1” and “0” in a randomly generated encryption key or password. The present invention provides an encryption circuit and a random password generation circuit that cannot be decrypted using any decryption method other than that, can create a very difficult decryption code, and can improve the system security level. The purpose is to:

[0009]

In order to achieve the above object, an encryption circuit according to a first aspect of the present invention obtains a random encryption key output, and encrypts a serial plaintext input using the encryption key output. In an encryption circuit for obtaining an encryption output, a level of white noise is discriminated from a reference level, an encryption key generating means for obtaining the encryption key output, and an inverted signal of the encryption key output are integrated. And integrating means for feeding back to the key generation means as a reference level for the level discrimination and adjusting the appearance probabilities of "1" and "0" in the cryptographic key output so as to be equal.

Here, the white noise does not need to be perfect white noise, but may be any substantial white noise that can be used to obtain a random encryption key output.

The encryption key generating means may include avalanche noise generating means for generating avalanche noise by reverse bias of a PN junction and using the generated avalanche noise as white noise.

The encryption key generating means may include a synchronous latch means for sequentially latching a result of the level discrimination of the white noise at a predetermined timing and synchronizing the result with a predetermined data timing.

[0013] The integration means may include means for appropriately setting an integration time constant to limit the probability of occurrence of successive equivalent values in the cryptographic key output.

An encryption circuit according to a second aspect of the present invention includes a white noise generation circuit for generating white noise, and a binary noise generation circuit that discriminates white noise generated by the white noise generation circuit with respect to a reference level. A level discrimination circuit for obtaining a signal, a synchronization latch circuit for sequentially latching the output of the level discrimination circuit at a predetermined timing to obtain a random encryption key output synchronized with a predetermined data timing, and an output from the synchronization latch circuit A polarity switching circuit for sequentially switching the polarity of the serial plaintext input by the encryption key output to obtain an encrypted output obtained by encrypting the serial plaintext input with the encryption key output, and an inverted signal of the encryption key output output from the synchronous latch circuit. And the integrated value is fed back to the level discrimination circuit as the reference level, and the Includes a "1" in the key output an integrating circuit for adjusting so as to equalize the probability of occurrence of "0", the.

[0015] The white noise generating circuit may include an avalanche noise generating circuit for generating avalanche noise by a reverse bias of a PN junction.

[0016] The integration circuit may include a circuit for limiting the appearance probability of successive equivalent values in the encryption key output by appropriately setting an integration time constant.

An encryption circuit according to the present invention obtains a random encryption key output and encrypts a serial plaintext input with the encryption key output to obtain an encryption output. Level discrimination against
In order to obtain the cryptographic key output, integrate the inverted signal of the cryptographic key output, feed back the integrated value as a reference level for level discrimination, and equalize the appearance probabilities of “1” and “0” in the cryptographic key output. adjust. In this encryption circuit,
Appropriately controlling the appearance probabilities of “1” and “0” in a randomly generated encryption key, and cannot be decrypted using any decryption method other than the so-called “brute force method”
It is possible to create encryption that is very difficult to decipher, thereby improving the system security level.

According to a third aspect of the present invention, there is provided a random password generating circuit comprising: a white noise generating circuit for generating white noise; and a binary signal for level-discriminating white noise generated by the white noise generating circuit with respect to a reference level. , A latch circuit for sequentially latching the output of the level discrimination circuit at a predetermined timing to obtain a randomly changing binary output synchronized with a predetermined data timing, and an output from the synchronization latch circuit. A password output means for dividing the binary output by a predetermined number of bits to obtain a random character code and outputting it as a password; and integrating an inverted binary output signal output from the synchronous latch circuit, and Feedback to the level discrimination circuit as the reference level
An integration circuit that adjusts the appearance probabilities of “1” and “0” in the value output so as to be equal, and appropriately sets an integration time constant to limit the appearance probabilities of successive equivalent values in the cryptographic key output; Is provided.

[0019] The white noise generating circuit may include an avalanche noise generating circuit for generating avalanche noise by a reverse bias of a PN junction.

In the random password generation circuit according to the present invention, the level of white noise generated by the white noise generation circuit is discriminated by the level discrimination circuit, and the white noise is sequentially latched at a predetermined timing by the synchronization latch circuit and synchronized with the predetermined data timing. In addition, a binary output that changes at random is obtained, an inverted signal of the binary output output from the synchronous latch circuit is integrated by an integration circuit, and the integrated value is fed back to a level discrimination circuit as a discrimination reference level. By adjusting the appearance probabilities of “1” and “0” in the value output to be equal, and by appropriately setting the integration time constant so as to limit the appearance probabilities of successive equivalent values in the cryptographic key output, Binary output is separated by a predetermined number of bits to obtain a random character code and output as a password. To. In this random password generation circuit, it is possible to appropriately control the appearance probabilities and continuous appearance probabilities of “1” and “0” in a randomly generated password, and to create an encryption that is extremely difficult to decipher.
The system security level can be improved.

[0021]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 schematically shows a configuration of an encryption circuit according to an embodiment of the present invention.

The encryption circuit shown in FIG.
1, A2, A3, A4, transistor Q1, diodes D1, D2, D flip-flop F1, exclusive OR gate EX1, resistors R1, R2, R3, R4, R
5, R6, R7, R8, R9, R10, R11, R1
2, R13, R14, R15, R16, R17, capacitors C1, C2, C3, C4, C5, input terminal JP1,
JP2, output terminals JP3 and JP4 are provided.

The transistor Q1 is an npn transistor, and generates avalanche noise as white noise by applying a reverse bias of a voltage higher than the emitter-base maximum voltage V _EB using a PN junction between the base and the emitter. Avalanche noise generating section for this purpose.

The emitter of the transistor Q1 is connected to a resistor R1
Is connected to a power supply of a voltage Vcc (for example, +12 V). The base of transistor Q1 is connected to resistors R2 and R2.
3 are sequentially connected in series to a power supply having a voltage of -Vcc (for example, -12 V). The base of the transistor Q1 is
It is connected to the non-inverting input terminal of the operational amplifier A1 via the capacitor C1. The non-inverting input terminal of the operational amplifier A1 is
It is connected to a common potential (ground) via a resistor R4. The emitter of the transistor Q1 is connected to the capacitor C2.
To a common potential. Resistance R2 and resistance R
3 is connected to a common potential via a capacitor C3.

The inverting input terminal of the operational amplifier A1 is connected to a common potential via a resistor R5. The output terminal of the operational amplifier A1 is connected to the inverting input terminal of the operational amplifier A1 through a variable resistor VR1 and a resistor R8 in series.

The operational amplifier A1 amplifies the avalanche noise generated by the transistor Q1, and amplifies the variable resistor VR.
The gain can be adjusted by changing the resistance value of the feedback resistor formed of a series circuit of the resistor 1 and the resistor R8 by the variable resistor VR1. The output terminal of the operational amplifier A1 is connected to the inverting input terminal of the operational amplifier A3 via the capacitor C4.

For example, a series circuit of a resistor R6 and a resistor R7 is connected between a power supply of +5 V and a common potential.
6 and the resistor R7 are connected to the non-inverting input terminal of the operational amplifier A2. The output terminal of the operational amplifier A2 is directly connected to the inverting input terminal, and constitutes a so-called voltage follower. The output terminal of the operational amplifier A2 is connected to the inverting input terminal of the operational amplifier A3 via a resistor R10.
The output terminal of the operational amplifier A2 is also connected to the inverting input terminal of the operational amplifier A4 via the resistor R13. The output terminal of the operational amplifier A3 is connected via a resistor R11 to the non-inverting input terminal of the operational amplifier A3. Operational amplifier A
Reference numeral 3 forms a Schmitt trigger circuit that discriminates the level of white noise given from the operational amplifier A1 and outputs a binary signal.

The cathode of the diode D1 is, for example, + 5V
And the anode of the diode D1 is connected to the cathode of the diode D2. Diode D
The two anodes are connected to a common potential. The output terminal of the operational amplifier A3 is connected to a connection point between the diode D1 and the diode D2 via the resistor R14. The connection point between the diode D1 and the diode D2 is connected to the input terminal D of the D flip-flop F1 via the resistor R15. That is, the series circuit of the diode D1 and the diode D2 constitutes a limiter for the input to the input terminal D of the D flip-flop F1.

A clock input terminal CK of the D flip-flop F1 is connected to a common potential via a resistor R16 and to an input terminal JP1 to which a data strobe input for synchronizing data is applied. The non-inverting output terminal Q of the D flip-flop F1 is connected to one input terminal of the exclusive OR gate EX1. D
The non-inverting output terminal Q of the flip-flop F1 is connected to an output terminal JP3 for outputting an encryption key. The clear end CLR of the D flip-flop F1 is connected to, for example, a power supply of +5 V, and the preset end PR of the D flip-flop F1 is
Is connected to a power supply of + Vcc, for example.

The output of (the non-inverting output terminal Q of) the D flip-flop F1 is obtained by inputting the data strobe input from the input terminal JP1 to the clock input terminal CK of the D flip-flop F1.
The data is sequentially latched in synchronization with the data strobe input.

The other input terminal of the exclusive OR gate EX1 is connected to a common potential via a resistor R17 and connected to a serial plaintext input, that is, an input terminal JP2 to which plaintext to be encrypted is given in the form of serial data. ing. An output terminal of the exclusive OR gate EX1 is an output terminal J for encrypted output.
Connected to P4.

The inverted output terminal / Q of the D flip-flop F1
(Cuber) is connected to a common potential via a resistor R12 and a capacitor C5 in series in order.
The connection point of the capacitor C5 is connected to the non-inverting input terminal of the operational amplifier A4. The output terminal of the operational amplifier A4 is connected to the inverting input terminal of the operational amplifier A4 via a variable resistor VR2 as a feedback resistor. The gain of the operational amplifier A4 can be adjusted by the variable resistor VR2. The output terminal of the operational amplifier A4 is connected to a resistor R9.
Is connected to the non-inverting input terminal of the operational amplifier A3.

The resistor R12 and the capacitor C5 constitute a stabilizing integrator for integrating the cryptographic key output fed back from the inverted output terminal / Q of the D flip-flop F1. The output of this stabilizing integrator, that is, the signal at the connection point between the resistor R12 and the capacitor C5, is gain-adjusted by the operational amplifier A4, and the operational amplifier A3 of the Schmitt trigger circuit is
To the non-inverting input. The voltage follower including the operational amplifier A2 supplies a DC voltage to the inverting input terminal of the operational amplifier A3 and the inverting input terminal of the operational amplifier A4.

The stabilizing integrator composed of the resistor R12 and the capacitor C5 is an integrator for stabilizing so that the appearance probabilities of "1" and "0" are equal. The values of the resistor R12 and the capacitor C5 are as follows. Resistor R10 and capacitor C
The value of 4 is set so as to satisfy C4 * R10 << C5 * R12. That is, if the encryption key output is "1", the output of the stabilized integrator is C5 * at the output level of "0" at the inverted output terminal / Q of the D flip-flop F1.
Asymptotically with the time constant of R12, if the encryption key output is "0",
It approaches the output level of "1" at the inverted output terminal / Q of the D flip-flop with the time constant of C5 * R12.

The operational amplifier A4 adjusts the gain of the output of the stabilizing integrator and feeds back the feedback to the non-inverting input terminal of the operational amplifier A3. Lower the voltage at the end,
If the output of the encryption key is "0", the voltage at the non-inverting input terminal of the operational amplifier A3 is increased to make the appearance probabilities of "1" and "0" equal. Further, by adjusting the time constant of C5 * R12 of the stabilizing integrator composed of the resistor R12 and the capacitor C5 to control the speed at which the voltage at the non-inverting input terminal of the operational amplifier A3 changes, "0" is continuously obtained. "Or" 1 "is restricted.

Next, the operation of the circuit shown in FIG. 1 will be described.
First, the resistance values of the resistors R6 and R7 are substantially the same, and the output voltage of the operational amplifier A2 is approximately VDD / 2 (= 5
/2=2.5V). On the other hand, a reverse bias voltage is applied to the PN junction between the emitter and the base of the transistor Q1, and the transistor Q1 generates avalanche noise. This avalanche noise is amplified by an amplifier circuit including the operational amplifier A1. The DC component of the avalanche noise output from the operational amplifier A1 is cut by the capacitor C4. The AC component Snoise of the avalanche noise and the voltage VDD supplied from the operational amplifier A2
/ Sound + VDD / 2 is added to the operational amplifier A
3 is supplied to the inverting input terminal.

The operational amplifier A3 is a positive feedback amplifier.
Therefore, assuming that the output voltage of the operational amplifier A4 is VDD / 2, the output signal of the operational amplifier A3 falls to "1" (VDD) or "0" (0V) depending on the level of the avalanche noise Snoise. You. This output signal is supplied to the input terminal D of the D flip-flop F1, and is sequentially latched and output by the D flip-flop F1 in response to the data strobe signal.

The exclusive OR gate EX1 has a D
An exclusive OR of an output signal of the flip-flop F1 and a serial signal supplied as a plaintext input serially is calculated and output as an encrypted output. The output of the D flip-flop F1 is output as an encryption key. The level of avalanche noise is determined randomly. Therefore,
The combination of "1" and "0" output from the Schmitt trigger circuit is also determined at random. By using this signal as an encryption key, "1" and "0" are randomly generated,
Moreover, since the appearance probabilities are almost equal, it is possible to create a cipher which is very difficult to decipher.

Here, it is assumed that "0" is accidentally continuously output from the output terminal Q of the D flip-flop F1. In this case, the output of the inverted output terminal / Q of the D flip-flop F1 becomes "1" continuously, and the output voltage of the stabilized integrator increases. Therefore, the output voltage of the operational amplifier A4 becomes VDD.
/ 2, the voltage at the non-inverting input terminal of the operational amplifier A3 increases, and "1" is easily output. When "1" is output from the output terminal Q of the D flip-flop F1 by chance, the inverted output terminal /
The output of Q continuously becomes "0", and the output voltage of the stabilized integrator decreases. Therefore, the output voltage of the operational amplifier A4 decreases from VDD / 2, the voltage of the non-inverting input terminal of the operational amplifier A3 decreases, and "0" is easily output.

Therefore, as described above, the stabilizing integrator C
By appropriately adjusting the time constant of 5 * R12, the speed at which the reference level voltage of the Schmitt trigger circuit changes can be manipulated to limit the probability that "0" or "1" appears continuously.

As described above, according to this embodiment, random data of infinite length is generated using avalanche noise, and the appearance probabilities of "1" and "0" are made the same by the stabilizing integrator. In this case, a practical cipher can be generated by limiting the continuous appearance probability of "0" or "1" by the time constant of the stabilizing integrator. Therefore, since the appearance probabilities of “0” and “1” are equal, it is possible to create a cipher that is very difficult to decipher, and it is possible to improve the security level of the system.

By doing so, it is possible to provide a practical cryptographic generation circuit that can sequentially decrypt all data by using any decryption method by sequentially supplying all data as a cryptographic key. , And data security by complete encryption generation can be realized.

In the above description, an encryption circuit for encrypting and outputting a serial plaintext input using random data obtained by level-discriminating avalanche noise as an encryption key is configured. As a result of controlling the appearance probability, a random character code can be generated as a 7 / 8-bit character code, and a random password generation circuit that generates a random password can also be configured. In this case, the random password generation circuit includes the exclusive OR gate EX1 in FIG.
The resistor R17, the input terminal JP2, and the output terminal JP4 are omitted, and the time constant of the stabilized integrator and the operational amplifier A4
The output of the output terminal JP3 obtained by appropriately adjusting the gain is used as a random password.

The present invention is not limited to the above embodiment,
Various modifications and applications are possible. For example, in the above embodiment, in order to generate substantial white noise, the PN between the emitter and the base of the transistor is used.
Although the avalanche noise due to the avalanche breakdown of the junction was used, any other PN junction avalanche breakdown may be used.

Further, as substantial white noise,
Not only avalanche noise, but any other random noise having high randomness can be used.

Also, a configuration for extracting and amplifying noise,
As a configuration for comparing the noise with a reference value (threshold) and converting the noise into a signal of “1” or “0”, any generally known configuration can be used. Further, the circuit configuration for preventing the occurrence of “1” or “0” continuously is also arbitrary, and the configuration of the feedback circuit, the configuration of the stabilizing integrator, and the like can be arbitrarily changed. For example, the output Q of the D flip-flop may be inverted through an inverter and supplied to a stabilized integrator, or a more complicated integration circuit may be used.

In the above embodiment, the operational amplifier A
2 has been described as approximately VDD / 2,
It is sufficient that a certain constant voltage is obtained, not limited to / 2. By appropriately adjusting the gain of the operational amplifier A4 and operating the reference level voltage of the Schmitt trigger circuit, the appearance probabilities of “1” and “0” can be made equal. can do.

The means for limiting the continuous occurrence probability of "1" or "0" is not limited to adjusting the time constant of the stabilized integrator. For example, by adjusting the variable resistor VR1, the ratio between the DC component and the noise component of the inverting input terminal voltage of the operational amplifier A3 is adjusted, and the sensitivity of the Schmitt trigger circuit to the reference level voltage with respect to noise is controlled. You may.

[0050]

As described above, according to the present invention, the occurrence probability of "1" and "0" in a randomly generated encryption key or password is appropriately controlled, and the probability other than the so-called "brute force method" is controlled. To provide an encryption circuit and a random password generation circuit that cannot be decrypted using any of the decryption methods described above, can generate a very difficult decryption code, and can improve the system security level. Can be.

[Brief description of the drawings]

FIG. 1 is a circuit diagram schematically showing a configuration of an encryption circuit according to an embodiment of the present invention.

[Explanation of symbols]

 A1 to A4 Operational amplifier Q1 Transistor D1, D2 Diode F1 D flip-flop EX1 Exclusive OR gate R1 to R17 Resistance C1 to C5 Capacitor JP1 to JP4 Output terminal

Claims (9)

[Claims] An encryption circuit that obtains a random encryption key output and encrypts a serial plaintext input with the encryption key output to obtain an encryption output, wherein substantial white noise is level-discriminated from a reference level. A cryptographic key generating means for obtaining the cryptographic key output; integrating an inverted signal of the cryptographic key output; feeding back the integrated value to the cryptographic key generating means as a reference level for the level discrimination; "1" in output
And an integrating means for adjusting the appearance probability of "0" to be equal. 2. The encryption circuit according to claim 1, wherein said encryption key generation means includes avalanche noise generation means for generating avalanche noise by reverse bias of a PN junction and using the avalanche noise as white noise. 3. The apparatus according to claim 1, wherein said encryption key generation means further includes a synchronization latch means for sequentially latching a result of level discrimination of said white noise at a predetermined timing and synchronizing with a predetermined data timing. Or the encryption circuit according to 2. 4. An apparatus according to claim 1, wherein said integration means includes means for appropriately setting an integration time constant to limit a probability of occurrence of continuous equivalent values in said encryption key output. The encryption circuit according to claim 1. 5. A white noise generating circuit for generating substantial white noise; a level discriminating circuit for level-discriminating white noise generated by the white noise generating circuit with respect to a reference level to obtain a binary signal; A synchronous latch circuit for sequentially latching the output of the discrimination circuit at a predetermined timing to obtain a random encryption key output synchronized with a predetermined data timing; and a polarity of a serial plaintext input by the encryption key output output from the synchronization latch circuit. And a polarity switching circuit for obtaining an encrypted output obtained by encrypting the serial plaintext input with the encryption key output, and integrating an inverted signal of the encryption key output output from the synchronous latch circuit, and setting the integrated value to the level. Feedback to the discrimination circuit as the reference level, and appearance of “1” and “0” in the encryption key output An encryption circuit, comprising: an integration circuit that adjusts the probability to be equal. 6. The encryption circuit according to claim 5, wherein said white noise generation circuit includes an avalanche noise generation circuit for generating avalanche noise by a reverse bias of a PN junction. 7. The circuit according to claim 5, wherein the integration circuit includes a circuit for appropriately setting an integration time constant so as to limit a probability of occurrence of successive equivalent values in the cryptographic key output. Encryption circuit. 8. A white noise generating circuit for generating substantial white noise, a level discriminating circuit for obtaining a binary signal by level discriminating a white noise generated by the white noise generating circuit with respect to a reference level, A synchronous latch circuit for sequentially latching the output of the discrimination circuit at a predetermined timing to obtain a randomly changing binary output synchronized with a predetermined data timing; and a method for converting the binary output output from the synchronous latch circuit into a predetermined number of bits. A password output means for obtaining a random character code separated by the above and outputting as a password; and integrating a binary output inverted signal output from the synchronous latch circuit, and feeding back the integrated value to the level discriminating circuit as the reference level. Then, when the appearance probabilities of “1” and “0” in the binary output are adjusted to be equal, A random password generation circuit, comprising: an integration circuit for appropriately setting an integration time constant so as to limit the probability of occurrence of successive equivalent values in the encryption key output. 9. The random password generation circuit according to claim 8, wherein said white noise generation circuit includes an avalanche noise generation circuit for generating avalanche noise by a reverse bias of a PN junction.