JP2000082952A - Multi-bit counter device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize current up/down counting with a simple configuration. SOLUTION: A CPU 15 takes in an eight bits count value with a prescribed chip selection period from a counter IC 13 to which a two-phase pulse is inputted, which executes addition counting or subtraction counting in accordance with the progress/delay of a phase between input pulses and outputs the eight bits count value, collates it with a count value that is previously taken in, judges the presence or absence of overflow or underflow and carries or borrows the count value which is taken in this time in accordance with the judged result. Since carrying/borrowing are judged by software processing, device constitution is simplified and the manufacturing cost can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-bit counter device capable of accurately counting up and down with a simple configuration.

[0002]

2. Description of the Related Art In all on-vehicle control devices such as an anti-lock brake device and a four-wheel steering device, rotation measuring means such as a wheel rotational speed sensor and a steering wheel angle sensor are indispensable. In particular, in the case of a sensor such as a steering wheel angle sensor that measures a rotation pulse having directionality according to the forward rotation and the reverse rotation of the steering wheel, various measures are required. Conventional multi-bit counter device 1 shown in FIG.
Outputs the output of the encoder 2 that outputs a two-phase pulse of an A-phase pulse and a B-phase pulse as the steering angle pulse,
The counter counts up or down in accordance with the phase of the phase pulse.
4 and a CPU 5.

Specifically, the multi-bit counter device 1
Is an 8-bit counter IC3 for counting the lower byte connected to the encoder 2 via the A-phase pulse output line and the B-phase pulse output line, and a counter IC3 for counting the lower byte.
And a CPU 5 connected to both counters IC3, 4 via individual chip select signal lines and a common data bus. The lower byte counting counter IC3 receives the two-phase pulses of the A-phase and the B-phase, performs addition counting or subtraction counting according to the advance / delay of the phase between the input pulses, and outputs an 8-bit count value. The carry signal is supplied to the upper byte counting counter IC4 via the carry signal output line. That is, the lower byte counting counter IC3 performs an addition count if the A-phase pulse is earlier than the B-phase pulse, and performs a subtraction count if the A-phase pulse is later than the B-phase pulse. When a carry due to a carry or a subtraction occurs, a corresponding carry signal is supplied to the upper byte counting counter IC4.

[0004]

In the conventional multi-bit counter device 1, the lower byte counting counter IC3 and the upper byte counting counter IC4 are connected to the CPU 5 via a common data bus, so that the counted value When taking in the data, the CPU 5 first sets the lower byte counting counter I
A chip select signal is supplied to C3, and a lower byte count value is taken in via a common data bus. Next, CP
U5 supplies a chip select signal to the upper byte counting counter IC4 and takes in the upper byte count value via the common data bus. That is, the CPU 5 needs to sequentially take in the lower byte count value and the upper byte count value via the 8-bit data bus. If the lower byte counting counter IC3 has previously updated the count, it is not possible to maintain the synchronism, that is, the same, as the data of the upper byte count value and the lower byte count value. There was a problem that the numerical values would be extremely inaccurate.

Also, the carry signal transmitted from the lower byte counting counter IC3 to the upper byte counting counter IC4 requires an appropriate time for signal propagation. When data is fetched from the IC 4, the carry signal that is actually occurring due to the propagation delay of the carry signal cannot be fetched, and there is a problem that the correct count value may not be fetched. Was something. Furthermore, the device configuration requires a pair of counter ICs 3 and 4 for counting the lower byte and counting the upper byte, and therefore has the problems that the circuit configuration is easily complicated and the manufacturing cost is high. there were.

The present invention has solved the above-mentioned problem, and has a simple configuration using a single counter and a CPU.
It is an object of the present invention to accurately count phase pulses.

[0007]

In order to achieve the above-mentioned object, the present invention provides a multi-bit multi-bit counter in which a two-phase pulse is input and an addition count or a subtraction count is performed in accordance with the advance or delay of the phase between the input pulses. A counter that outputs a numerical value, supplies a chip select signal to the counter at a predetermined cycle, captures the count value of the plurality of bits, compares the count value with the previously captured count value, and determines whether an overflow or underflow has occurred. And an arithmetic processing means for carrying up or down the currently read count value in accordance with the result of the determination.

The arithmetic processing means compares and compares the currently acquired count value from the counter with the previously acquired count value, the last count value is within a predetermined range near the upper limit value, and the current count value is within a predetermined range near the initial value. If it is within the range, it is determined that an overflow has occurred once, and carry is performed. If the previous count value is in the predetermined range near the initial value and the current count value is in the predetermined range near the lower limit value, 1 underflow
It is characterized in that it is determined that the number of occurrences has occurred and a carry-down is performed.

Further, the counter receives two-phase pulses of an A-phase pulse and a B-phase pulse which are different from each other by a predetermined phase, and if the A-phase pulse is more advanced than the B-phase pulse, adds and counts. If the pulse is later than the B-phase pulse, it is an up-down counter that performs subtraction counting.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a schematic configuration diagram showing an embodiment of a multi-bit counter device according to the present invention.
FIG. 3 is an operation principle diagram for explaining a counting operation of the multi-bit counter device shown in FIG. 1, and FIG. 3 is a CPU shown in FIG.
5 is a flowchart for explaining the operation of FIG.

The multi-bit counter device 11 shown in FIG.
It comprises an 8-bit counter IC 13 connected to the encoder 12 via the A-phase pulse output line and the B-phase pulse output line, and a CPU 15 connected to the counter IC 13 via an 8-bit data bus and a chip select signal line. The counter IC 13 receives two-phase pulses of the A-phase and the B-phase, performs an addition count or a subtraction count in accordance with the advance or delay of the phase between the input pulses, and outputs an 8-bit count value. Specifically, an up-down counter is configured to perform an addition count if the A-phase pulse is earlier than the B-phase pulse, and perform a subtraction count if the A-phase pulse is later than the B-phase pulse. .

The CPU 15 has a predetermined period (for example, 5 m
In step s), a chip select signal is supplied to the counter IC 13, and an 8-bit count value is fetched via the data bus. In addition, the previously captured count value is compared with the currently captured count value to determine whether an overflow or underflow has occurred within the chip select cycle, and carry or decrement the currently captured count value according to the determination result. I do. Specifically, when the previous count value is between C0h and FFh and the current count value is between 00h and 40h, it is determined that one overflow has occurred, and the upper byte value is carried. . Also, the last count value is 00h to 4
If the count value is between 0h and the current count value is between C0h and FFh, it is determined that one underflow has occurred, and the upper byte value is lowered.

As shown in FIG. 2, the output data of the counter IC 13 travels within a counting range (area A) having a width of positive and negative 8 bits (80h to 7Fh). CPU15
Stores the count value of the previous time and the count value of the present time every 5 ms in order to determine whether the upper byte count value carries or decrements, and compares the two values to check for overflow or underflow of the counter IC 13. However, since the count value output by the counter IC 13 does not always change continuously and there is a possibility that data skipping occurs, even if data skipping occurs, an overflow and an underflow can be reliably detected so that the vicinity of the upper limit and the initial value can be captured. The determination width provided in the vicinity is set to C0h to 40h shown with a satin pattern in FIG.

In measuring the steering angle, the CPU 15 first takes in the current count value from the counter IC 13 in step (101) in FIG. 3, and compares it with the previous count value in the following steps. Here, for example, if the previous count value is between C0h and FFh (area B) and the current count value is between 00h and 40h (area C), the determination result of the determination step (102) is affirmed. In a step (104) following the received judgment step (103), it is determined that one overflow has occurred, and the upper byte value is carried. Also, the last count value is 00h to 40h
(Area d), and the current count value is C0h to FFh
(Area E), the judgment step (10)
In the step (107) following the judgment step (106) receiving the judgment positive result of the step 5), the underflow is 1
Is determined to have occurred once, and the upper byte value is lowered.
The change in the count value other than the above is determined by the counter IC.
It is considered that neither overflow nor underflow has occurred in the count value of 13, and the previous value is continuously adopted as the upper byte value. Thus, the upper byte value determined by the software processing by the CPU 15 is combined with the count value of the counter IC 13 in step (108).

As described above, the above multi-bit counter device 1
According to No. 1, the counter 4 provided for counting the carry signal in the related art is not required, so that the device configuration is simplified, the manufacturing cost can be reduced, and the carry and the carry can be determined by software processing. Therefore, by setting the cycle of the chip select signal to a sufficiently short cycle, it is possible to reliably detect the carry of the counter IC 13 without missing the carry. Therefore, unlike the related art, it is not affected by the propagation time of the carry signal supplied from the lower byte counting counter 3 to the upper byte counting counter 4 or the data error caused by the difference in reading time between the lower byte and the upper byte. In addition, it is possible to always take in accurate count values.

Further, the CPU 15 compares and compares the count value currently received from the counter IC 13 with the count value previously captured, and the previous count value is between C0h and FFh and the current count value is between 00h and 40h. In this case, it is determined that an overflow has occurred once, the upper byte value is carried, and if the previous count value is between 00h and 40h and the current count value is between C0h and FFh, , It is determined that an underflow has occurred once and the upper byte value is shifted down, so that overflow and underflow can be reliably detected by comparing the currently acquired count value with the previously acquired count value. In addition, the judgment of overflow or underflow is not a simple line-crossing boundary judgment, but rather an area with a certain width. To perform the judgment, jump data to the counter output can be reliably determined carry or borrow be generated.

If a two-phase pulse of an A-phase pulse and a B-phase pulse which are different from each other by a predetermined phase is input to the counter IC 13 and the A-phase pulse is earlier than the B-phase pulse, the counter IC 13 performs addition counting. If the pulse is later than the B-phase pulse, the encoder is constituted by an up-down counter that performs subtraction counting. For example, a steering angle detection encoder 12 that outputs an A-phase pulse and a B-phase pulse whose phases are shifted from each other by 90 degrees. By connecting the steering wheel and the like, it is possible to detect that the advance / delay relationship between the A-phase pulse and the B-phase pulse is reversed between when the steering wheel is rotated forward and when the steering wheel is rotated reversely, and the steering angle can be accurately detected. . In addition, since the cycle of the chip select signal can be set to a sufficiently short cycle, it is possible to reliably detect the carry or borrow of the counter IC 13 without overlooking it. With this, the steering angle can be accurately detected.

In the above-described embodiment, the case where the multi-bit counter device 11 is used for a steering angle sensor is taken as an example. However, the multi-bit counter device of the present invention is used for measuring a rotating body that rotates normally and reversely. It can be applied to applications other than the steering angle sensor.

[0019]

As described above, according to the present invention,
A two-phase pulse is input, an addition count or a subtraction count is performed in accordance with the advance / delay of the phase between the input pulses, and a counter that outputs a count value of a plurality of bits is used by the arithmetic processing unit to generate a plurality of bits with a predetermined chip select cycle. Capture the count value,
Compared to the previously captured count value, the presence or absence of overflow or underflow is determined, and the carry value or carry-down of the currently captured count value is performed according to the determination result. The counter provided in the above is unnecessary, which simplifies the device configuration, reduces the manufacturing cost, and furthermore, since the carry and the carry are determined by software processing, the cycle of the chip select signal can be sufficiently increased. By setting the period to be short, it is possible to reliably detect the carry or borrow of the counter without overlooking it. Therefore, unlike the related art, the counter is supplied from the lower byte counter to the upper byte counter. It is not affected by data error caused by carry signal propagation time or reading time difference between lower byte and upper byte. Ku, excellent effects etc. are possible always accurate count uptake.

In addition, the arithmetic processing means compares and compares the currently acquired count value from the counter with the previously acquired count value, the last count value is within a predetermined range near the upper limit value, and the current count value is near the initial value. If it is within the predetermined range, it is determined that an overflow has occurred once and carry is performed, and the previous count value is within the predetermined range near the initial value, and the current count value is within the predetermined range near the lower limit value. , The underflow is determined to have occurred once, and the carry is performed. For example, when an 8-bit counter is used, the previous count value is C0h.
If the current count value is between 00h and 40h, it is determined that one overflow has occurred, the upper byte value is carried, and the previous count value is between 00h and 40h. And the current count value is C0h ~
If it is between FFh, it is determined that an underflow has occurred once, and the overflow and underflow are performed by comparing the count value captured this time with the count value captured last time, such as lowering the upper byte value. Can be reliably detected, and the determination of overflow or underflow is not a simple line-crossing boundary determination,
Since the determination is made by crossing the boundary from a region having a certain width to the region, there is an effect that, even if data skipping occurs in the counter output, carry-up or carry-down can be reliably determined.

The counter receives two-phase pulses of an A-phase pulse and a B-phase pulse which are different from each other by a predetermined phase.
If the A-phase pulse is more advanced than the B-phase pulse, an up-down counter that performs addition counting is performed, and if the A-phase pulse is later than the B-phase pulse, a down-counting counter is performed. If connected to a steering angle detection encoder that outputs A-phase and B-phase pulses with shifted phases,
It captures that the forward and backward relations of the A-phase pulse and the B-phase pulse are reversed when the steering wheel is rotated forward and reverse, and the steering angle can be detected accurately, and the cycle of the chip select signal can be detected. Can be set to a sufficiently short cycle, so that it is possible to reliably detect the carry or borrow of the counter without overlooking it, and even if there is a sudden steering operation, the steering angle can be accurately detected with sufficient responsiveness And so on.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram showing one embodiment of a multi-bit counter device of the present invention.

FIG. 2 is an operation principle diagram for explaining a counting operation of the multi-bit counter device shown in FIG. 1;

FIG. 3 is a flowchart for explaining the operation of the CPU shown in FIG. 1;

FIG. 4 is a schematic configuration diagram illustrating an example of a conventional multi-bit counter device.

[Explanation of symbols]

 11 Multi-bit counter device 12 Encoder 13 Counter IC (Counter) 15 CPU (Operation processing means)

Claims (3)

[Claims] 1. A counter for receiving a two-phase pulse, performing an addition count or a subtraction count in accordance with the advance / delay of the phase between the input pulses, and outputting a count value of a plurality of bits. The count value of the plurality of bits is supplied to the counter, the count value of the plurality of bits is captured, the presence or absence of occurrence of overflow or underflow is determined by comparing with the previously captured count value, and the carry or digit of the currently captured count value is determined according to the determination result. A multi-bit counter device, comprising: an arithmetic processing unit for performing a reduction. 2. The arithmetic processing means compares and compares the currently acquired count value from the counter with a previously acquired count value, the previous count value is within a predetermined range near an upper limit value, and the current count value is an initial value. If it is within the predetermined range, it is determined that an overflow has occurred once, and carry is performed. The previous count value was within the predetermined range near the initial value, and the current count value was within the predetermined range near the lower limit value. 2. The multi-bit counter device according to claim 1, wherein in the case, the underflow is determined to have occurred once and the carry is performed. 3. The counter receives a two-phase pulse of an A-phase pulse and a B-phase pulse that differ from each other by a predetermined phase,
2. An up-down counter which performs an addition count when the A-phase pulse is earlier than the B-phase pulse and performs a subtraction count when the A-phase pulse is later than the B-phase pulse. A multi-bit counter device as described.