JP2000082948A - Input device and output device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize high-speed data input with a high clock frequency in an input device inputting the data signal by preventing skew caused by a difference between the shift time of a data signal from 'H' to 'L' and shift time from 'L' to 'H'. SOLUTION: A comparator 5 compares the rise/fall edges of an input data signal D1' outputted from an input buffer 11 with the data take-in edge of a clock signal CLK. A delay circuit 31 delays the clock signal CLK by a prescribed time in accordance with the compared result. A delay circuit 32 delays the clock signal CLK by the other prescribed time. A selector 4 selects a delay clock signal CLK-LH from the delay circuit 31 when the data signal D1' is a logic value 'H' and selects a delay clock signal CLK-HL from the delay circuit 32 when the data signal D1' is a logic value 'L'. A holding circuit 21 latches the data signal D1' based on the delay clock signal selected by the selector 4.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a data input device and an output device for performing high-speed data transfer in a semiconductor integrated circuit.

[0002]

2. Description of the Related Art With the spread of multimedia in recent years, the performance required for semiconductor devices has become stricter every day.
The trend toward higher speeds and lower power consumption is increasing. In particular, in a system such as image processing that handles a large amount of data at a high speed, a semiconductor device operating at an extremely high speed is required. In such a device, data transfer needs to be performed at high speed, and a technique for high-speed data transfer is essential. Techniques related to high-speed transfer include increasing the speed of input / output circuits and adopting high-speed standards for data buses. In recent years, as an input circuit, a voltage of a received signal is compared with a reference voltage, and a differential input circuit that amplifies the received signal in accordance with the difference, or a differential signal (complementary signal) is input to generate one signal Is generally adopted.

[0003]

However, when the output circuit of the data signal is of the push-pull type, the output between the time when each driver transistor outputs "H" data and the time when each driver transistor outputs "L" data is determined. It is extremely difficult to make the impedance (current) equal to each other. When the data signal output circuit is of a pull-up type that performs resistance termination, it is difficult to make a current flowing through a resistor equal to a current flowing through a transistor for outputting a data signal.

[0004] From the above technical background, the transition period from "L" to "H" of a data signal is not equal to the transition period from "H" to "L". "H" logical value and "L" logical value are not symmetrical with respect to the reference voltage. If data signals transferred at such irregular (variable) intervals are held by a regular reference clock signal, skew is likely to occur, causing malfunctions, and hindering high-speed operation at the system level. This skew appears more remarkably at the time of high-speed operation, and hinders further high-speed operation. Since the data transition period is generally several hundred ps to several ns, for example, at the time of high-speed operation using a clock signal of several hundred MHz, that is, in a situation where one cycle of the clock signal is several ns, the data transition period is It occupies several 10% of one cycle of the clock signal, and skew easily occurs.

The present invention has been made in view of the above problems, and has as its object:
Transition time of the input data signal from "H" to "L" and "L"
It is an object of the present invention to provide an input device and an output device which prevent a skew caused by a difference from a transition time from "H" to "H" and realize a high-speed operation.

[0006]

In order to solve this problem, an input device according to the present invention uses "H" of an input data signal.
In order to correct the difference between the transition time from "L" to "L" and the transition time from "L" to "H", the clock signal is delayed according to one or both transition times of the data signal. Alternatively, the input data signal is latched using two types of delayed clock signals and / or the original clock signal.

Further, in the output device of the present invention, the difference between the transition time from "H" to "L" and the transition time from "L" to "H" of the output data signal is corrected. A configuration for adjusting the driving capability of a driving element that outputs a data signal to be output is employed.

More specifically, the input device according to the first aspect of the present invention sets a delay time according to a logical value of a data signal, and delays a clock signal by the delay time; And a holding circuit for holding the data signal based on a clock signal.

According to a second aspect of the present invention, in the input device according to the first aspect, the delay unit is configured to output the clock signal when an edge for capturing data of the clock signal is within a transition period of the data signal. The delay time is set such that the data capturing edge is located after the end of the transition period of the data signal.

According to a third aspect of the present invention, in the input device according to the first or second aspect, the delay means includes at least one of a data fetch edge of the clock signal and a rising and falling edge of the data signal. And a delay circuit for setting the delay time according to the comparison result of the comparator.

According to a fourth aspect of the present invention, in the input device according to the first or second aspect, the delay means includes a data capturing edge of the clock signal and both rising and falling edges of the data signal. And a first delay circuit for setting the delay time according to the "H" logical value of the data signal in accordance with the result of the comparison of the rising edge of the data signal by the comparator. A second delay circuit for setting the delay time according to the logical value "L" of the data signal in accordance with a result of the comparison of the falling edge of the data signal by the comparator; A selection circuit for selecting the delay time of the first delay circuit when the logic value is "H", and selecting the delay time of the second delay circuit when the data signal is "L" logic value. Features.

According to a fifth aspect of the present invention, in the input device according to the third or fourth aspect, the delay circuit responds to a comparison result of the comparator and a setup time for guaranteeing the capture of the data signal. , The delay time is set.

According to a sixth aspect of the present invention, there is provided an output device having a drive element for outputting a data signal, an output circuit capable of adjusting the drive capability of the drive element, and a signal indicating the length of a transition period of the data signal. And a control circuit for controlling the driving capability of the output circuit to be higher or lower based on this signal.

According to a seventh aspect of the present invention, in the output device according to the sixth aspect, the control circuit inputs a signal indicating a length of a transition period of the data signal to a data signal output from the output device. It is characterized by receiving from a device.

With the above arrangement, in the input device according to the first to fifth aspects of the present invention, for example, "H" of the data signal is output.
In the case where the transition period from "L" to "L" is long, the data capture edge of the original clock signal is positioned within the transition period, but a long delay time is set according to the "L" logical value of the data signal. Since the clock signal is delayed by this delay time, the data fetch timing of the clock signal is positioned after the data signal has transitioned to the "L" state. Therefore, it is possible to reliably take in the data signal of "L" logical value, and to prevent mislatch.

In the output device according to the sixth and seventh aspects of the present invention, when the transition period of the data signal from "H" to "L" is long, the data capture edge of the clock signal is Although located within the transition period, the drive period of the output circuit is adjusted to be high, so that the transition period is shortened.
Therefore, the data fetch edge of the clock signal is located after the end of the shortened transition period, so that the "L" logical value of the data signal can be correctly fetched and no mislatch occurs.

[0017]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIGS. 1 to 4 show a first embodiment of the present invention. FIG. 3 is a configuration diagram of a data signal transmission / reception system including a transmission chip and a reception chip.

In FIG. 3, the transmission chip 10 has a plurality (n) of output buffers 301, 302,.
And an internal circuit 35. The internal circuit 35 outputs a switching signal Con for switching between a test mode and a normal operation mode, which will be described in detail later, and a data signal D via the output buffers.
1 ... Dn is transmitted to the receiving chip 20.

As shown in FIG. 4, inside the receiving chip 20, input circuits 401 to 40n for holding data signals D1 to Dn, respectively, and a data signal D1 '' held for each of the input circuits 401 to 40n. , D2 "... Dn", and a clock signal CLK in response to a reference clock signal.
And a power supply circuit 52 that supplies a power supply voltage to the internal circuit 50 and supplies a reference voltage Vref (described later) to each of the input circuits 401... 40n.

FIG. 1 is an internal configuration diagram of the input circuit 401. The other input circuits 402 to 40n have the same configuration as the input circuit 401.

Referring to FIG. 1, an input circuit 401 includes an input buffer 11, a delay means 60, and a holding circuit 21 therein. The delay circuit 60 includes a comparator 5, two delay circuits 31, 32, and a selector 4.

The input buffer 11 is a differential amplifier (differential input circuit), and includes a reference voltage Vref and a data signal D.
1 and outputs the amplified data signal D1 'based on the difference between the data signal D1 and the reference voltage Vref. The reference voltage Vref is set to be lower than the power supply voltage and higher than the ground potential. When the input data signal D1 is at a higher potential than the reference voltage Vref, the input buffer 11
The power supply potential is output as the H "potential, and the input data signal D1
Is lower than the reference voltage Vref, the ground potential is output as the "L" potential.

The holding circuit 21 is constituted by a D latch, and at the up edge (data fetch timing) of the delayed clock signal CLK2 delayed by the delay circuit 31 or 32, the amplified data signal from the input buffer 11 is output. D1 'is held and the latched data signal D1''is output.

The comparator 5 compares the phase of the data signal D1 'with the phase of the clock signal CLK. The result of the phase comparison between the up edge (rising transition point) of the data signal D1 'and the up edge of the clock signal CLK is the signal Cde1F, Cde1C.
Output as de1B. When the up edge of the data signal D1 'is located before the up edge of the clock signal CLK, a pulse corresponding to the phase shift is output as the signal Cde1F, and the up edge of the data signal D1' is the clock signal. If it is located behind the rising edge of CLK, a pulse corresponding to the phase shift is output as the signal Cde1B. Similarly, the result of the phase comparison between the falling edge (falling point) of the data signal D1 'and the rising edge of the clock signal CLK is output as signals Cde2F and Cde2B. Data signal D
When the down edge of 1 'is located before the up edge of the clock signal CLK, a pulse corresponding to the phase shift is output as the signal Cde2F, and the down edge of the data signal D1' is If it is located behind the up edge, the signal Cde2B
As a result, a pulse corresponding to the phase shift is output.

The delay amounts of the delay circuits 31 and 32 are variable, and the delay amounts are determined by the phase comparison results Cde1F and Cde1B and Cde2F and Cde2B of the comparator 5, respectively. The first delay circuit 31 outputs a delayed clock signal CLK_LH generated by delaying the clock signal CLK by the determined delay amount.
2 outputs a delayed clock signal CLK_HL generated by delaying the clock signal CLK by the determined delay amount. Further, the delay circuits 31 and 32 and the comparator 5
Becomes active when the mode switching signal Con is "H", and becomes inactive when the mode switching signal Con is "L".

The selector 4 outputs the signal CLK_L output from the delay circuit 31 when the data signal D 1 ′ is in the “H” state.
H when the data signal D1 'is in the "L" state.
2 is selected and output to the holding circuit 21 as the clock signal CLK2.

Next, the operation of the input device according to the present embodiment will be described separately for a test mode and a normal operation mode.

FIG. 2 shows an operation timing chart. FIG. 2A shows a test mode period, and FIG. 2B shows a normal operation period. (Test Mode) First, a test mode period (initialization period) is provided in order to determine a delay amount for delaying the clock signal CLK.

When the mode switching signal Con becomes "H", an initialization period is started. When the initialization period starts, a data signal Data that repeats “H”, “L”, “H”, and “L” is output from the transmitting chip 10 to the receiving chip 20 as test data. As shown in FIG. 2A, the data signal D1 has a transition time difference between the transition from “L” to “H” and the transition from “H” to “L”. In the data signal D1 ', the lengths of the "H" state and the "L" state are not the same.

In the present embodiment, when the data signal D1 'is held using a clock signal, the setup time T1 is determined in advance in order to guarantee a sufficient setup time. This setup time T1 is set to a period of about 30 to 50% of one cycle of the clock signal. This set-up time T1 is determined by phase differences T2, T
This is a long period exceeding three. As a result of the comparator 5 comparing the phase of the data signal D1 'with the phase of the clock signal CLK, the rising edge of the data signal D1'
If the phase difference between the rising edge of the data signal D1 'and the rising edge of the clock signal CLK is T2, the delay circuit 3
1 determines the time T1-T2 as the delay value de1, while the rising edge of the data signal D1 'is the clock signal C1.
When the delay circuit 31 is located behind the rising edge of LK, the delay circuit 31 determines the time T1 + T2 as the delay value de1. When the down edge of the data signal D1 'is located after the up edge of the clock signal CLK, the down edge of the data signal D1' and the clock signal C
Assuming that the phase difference between the rising edge of the clock signal CLK and the rising edge of the clock signal CLK is T3, the delay circuit 32 determines the time T1 + T3 as the delay value de2. If it is located before, the delay circuit 32 sets the time T1-T as the delay value de2.
3 is determined. As a result, the rising edge of the delayed clock signal CLK2 is always at the timing delayed by the setup time T1 with respect to the rising and falling edges of the data signal D1.

As described above, when the delay amounts of the delay circuits 31 and 32 are determined, the delay circuits 31 and 32 respectively delay the clock signal CLK by the determined delay amount, and delay the clock signals CLK_LH, CLK_HL is output. One delay clock signal CLK_LH is a signal delayed by the first delay circuit 31, and the amount of delay is
This is a delay amount determined by a phase difference between an up edge when the data signal D1 ′ transitions from the “L” state to the “H” state and the up edge of the clock signal CLK. The other delayed clock signal CLK_HL is a signal delayed by the second delay circuit 32, and its delay amount is determined by the down edge when the data signal transitions from the “H” state to the “L” state and the clock signal. This is the delay amount determined by the phase difference from the rising edge of CLK.

Thus, the initialization period ends.

(Operation Mode) Next, the mode switching signal Con
Becomes "L", the normal operation mode is entered. In this normal operation mode, data signals are transferred in the same manner as normal data transfer. However, as a clock signal when the data signal is held by the holding circuit 21, two types of delayed clock signals CLK_LH and C_LH set during the initialization period are used.
The delayed clock signal CLK2 selected from LK_HL is used. The selector 4 outputs the delayed clock signal CLK_LH or CLK_HL based on the logical value of the data signal D1 '.
Make a selection. That is, the selector 4 outputs the data signal D1 '.
Currently selects the delayed clock signal CLK_LH when it is in the "H" state, and selects the delayed clock signal CLK_HL when the data signal D1 'is in the "L" state. The signal selected by the selector 4 is used as the delayed clock signal CLK2 as the holding circuit 21.
, And the holding circuit 21 holds the data signal D1 ′ at the rising edge of the delayed clock signal CLK2.

As can be seen from the above description, the data signal D
Since the phase difference between the up and down edges of 1 'and the up edge of the delayed clock signal CLK2 is reduced,
A reliable holding operation of the data signal D1 'can be performed,
Mislatch can be prevented.

Next, FIG. 2 showing the operation of the input circuit of the present embodiment, and FIG. 6 showing the operation when a data signal is taken in at the rising edge of the input clock signal CLK without using the selector 4 as in the past. Compare. 2 and 6, the first rising timing t0 of the clock signal CLK.
In this case, the data signal D1 'from the differential amplifier 11 has a voltage value exceeding the reference voltage Vref and is in the "H" state. Accordingly, in FIG. 6, the data signal D1 'is
When the data is taken in at the first rising edge of LK, the holding circuit 21
The data signal D1 '' latched at the time becomes a normal "H" state. In FIG. 2, the clock signal CLK is applied for a time T1-
Although the data signal D1 'is taken in at the rising edge of the delayed clock signal CLK_LH delayed by T2, FIG.
Even when the data signal D1 'is taken in at the first rising edge of the input clock signal CLK, the data signal D1' in the "H" state can be taken in normally. Therefore, in the present invention, it is not necessary to calculate two types of delay values according to both the "H" and "L" logical values of the data signal D1. That is, in the present invention, the delayed clock signal CLK_LH or C
LK_HL is generated, the delayed clock signal takes in the data signal D1 'at one logical value, the delay value is not calculated for the other logical value, and the original clock signal CLK
And the data signal D1 'having the other logical value is taken into account. In this configuration, selector 4 receives the delayed clock signal of one delay circuit (for example, 31) and the original clock signal CLK. In the present invention, the setup time T1 is not essential, but it is desirable to provide the setup time T1 in order to capture the data signal D1 'in a stable period (a period in which the voltage is constant) after the transition period of the data signal D1'. .

On the other hand, in FIGS. 2 and 6, at the next rising timing t1 of the clock signal CLK, the data signal D1 'from the differential amplifier 11 has a voltage value which is in the transition period but still exceeds the reference voltage Vref. Is in the "H" state. As a result, in FIG. 6, when the data signal D1 'is latched at the next rising timing t1 of the clock signal CLK, the holding circuit 21 holds the data signal D1' in the "H" state, and is indicated by a broken line in FIG. As described above, the data signal D1 'in the normal "L" state is not held, and a mislatch occurs. On the other hand, in the present embodiment, as shown in FIG. 2, the rising edge of delayed clock signal CLK_HL obtained by delaying clock signal CLK by predetermined delay value de2 (= T1 + T3), that is, the voltage of data signal D1 'is the reference voltage. At the timing t2 when the voltage becomes lower than Vref, the data signal D1 ′ in the “L” state is latched by the holding circuit 21. Therefore, in this embodiment, there is no mislatch.

In this embodiment, the clock signal 1
The case where the data signal D1 'holds the same value in the cycle period (that is, the frequency of the data signal is half of the clock signal) has been described. However, the present invention is not limited to this case. It is not subject to frequency restrictions.

In this embodiment, the data signal D
Although the rising edge of the clock signal is used to capture 1 ', the use of the falling edge of the clock signal or the use of both the rising and falling edges of the clock signal can be changed as appropriate.

Further, in the present embodiment, the delay clock signal delayed by the first delay circuit 31 when the data signal is in the "H" state is selected by using the two delay circuits 31 and 32, If the delayed clock signal delayed by the second delay circuit 32 is selected when the signal is in the “L” state, but it is clear that only the up edge of the data signal is located after the clock signal, Only the phase adjustment at the up edge of the data signal D1 'may be performed using only one delay circuit 31. When it is clear that only the down edge of the data signal is located after the clock signal, only the phase adjustment at the down edge of the data signal D1 'is performed using only the second delay circuit 32. In any of these cases, the selector 4 is unnecessary. Also, the setup time T1 has been described as being fixed at a value sufficient for data retention. However, if the setup time T1 is made variable by a new external control signal, a configuration effective for higher speed operation can be obtained.

(Second Embodiment) Next, a second embodiment of the present invention will be described.
The embodiment will be described with reference to FIG.

In FIG. 5, reference numeral 70 denotes a plurality of data signals (only one data signal D1 is shown in FIG. 5).
Is a transmitting chip (output circuit) for transmitting the data signals, and 80 is a receiving chip for receiving the plurality of data signals. Receiving chip 8
0 has an internal circuit 50, a PLL circuit 51, and a power supply circuit 52 similar to those in FIG. Further, the receiving chip 80
Has a plurality of input circuits (only one input circuit 81 is shown in FIG. 1). These input circuits are not specifically shown, but are internal components of the input circuit 401 shown in FIG. Among them, it has only the differential amplifier 11, the comparator 5, and the holding circuit 21, and does not have the two delay circuits 31, 32 and the selector 4. The holding circuit 21 outputs a data signal D based on a clock signal CLK output from the PLL circuit 51.
Latch 1 '.

On the other hand, the transmission chip 70 has a plurality of output buffers for transmitting a plurality of data signals, respectively (only the output buffer 71 for outputting the data signal D1 is shown in the figure). Each output buffer has the same internal configuration. The output buffer 71 is connected to a power supply and has three P-channel transistors (driving elements) TP1, TP2, and TP3 for setting the data signal D1 to the "H" state, and is grounded to set the data signal D1 to the "L" state. Three N to make
It has channel transistors (drive elements) TN1, TN2, and TN3. Further, the transmission chip 70 includes a first control circuit 72 for controlling the P-channel transistors TP1 to TP3.
And a second control circuit 73 for controlling the N-channel transistors TN1 to TN3. The first control circuit 72 includes:
A comparison result signal (a signal obtained by comparing the timing of the rising edge of the data signal D1 'with the rising edge of the clock signal CLK) Cde1 from the comparator 5 in the input circuit 81.
F, Cde1B, that is, a signal indicating the length of the transition period of the data signal, and the second control circuit 73 outputs the comparison result signal (data signal D) from the comparator 5 in the input circuit 81.
1) Cde2F, Cde
Enter 2B. These comparison result signals are shown in FIG. The first control circuit 72 outputs the comparison result signal Cd
When e1B is input, that is, when the data signal D1 '
If the time when the voltage of the data signal D1 'rises to the reference voltage Vref at the time of transition from L "to" H "is later than the rising point of the clock signal CLK, in other words, if the transition period is long, the ON operation is performed. On the other hand, the second control circuit 73 receives the comparison result signal Cde2B, that is, outputs the data signal D1 'when the comparison result signal Cde2B is input. When the voltage of the data signal D1 'falls to the reference voltage Vref at the time of transition from "H" to "L" is later than the rising point of the clock signal CLK, in other words, in a situation where the transition period is long, the ON operation is performed. The number of N-channel transistors to be increased to increase the transistor capability,
Reduce the transition time.

A data signal D1 'is fed back to the first and second control circuits 72 and 73. Therefore, even when the comparison result signal from the comparator 5 is not received, the transistor capability of the output buffer 71 is grasped based on the feedback signal. Can be increased.

Therefore, in this embodiment, the transmission chip 7
On the 0 side, the transistor capacity of the output buffer 71 is adjusted so that the transition period of the data signal D1 ′ from “H” to “L” and “
The transition period from L "to" H "can be adjusted to an appropriate period.
Therefore, similarly to the first embodiment, skew can be hardly generated, and high-speed operation in a frequency band with a clock frequency of several hundred MHz or more can be normally secured.

In the above description, one data signal D
Although the present invention is applied to an input circuit for inputting 1, the present invention can also be applied to an input circuit for inputting a differential signal. In this case,
The differential signal is input to the differential amplifier 11.

[0047]

As described above, according to the input device and the output device of the present invention, the transition time of the input data signal from "H" to "L" and the transition from "L" to "H". It is possible to prevent a skew generated due to a difference from time and realize a high-speed data input operation under a high clock frequency.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an internal configuration of an input circuit according to a first embodiment of the present invention.

FIG. 2 shows an operation of the input circuit according to the embodiment, in which (a) is a timing chart showing an operation in a test mode;
(b) is a timing chart showing the operation in the normal operation mode.

FIG. 3 is a schematic configuration diagram of a data signal input / output system including a transmission chip and a reception chip.

FIG. 4 is a diagram showing an internal configuration of a receiving chip.

FIG. 5 is a diagram illustrating an internal schematic configuration of an output circuit according to a second embodiment of the present invention.

FIG. 6 is a diagram showing that when a transition time from “H” to “L” of a data signal is long, mislatching of the data signal occurs.

[Explanation of symbols]

Reference Signs List 4 selector 5 comparator 10, 70 transmission chip 11 differential amplifier 20 reception chip 21 holding circuit 31, 32 delay circuit 401 to 40n input circuit 50 internal circuit 71 output buffer 72 first control circuit 73 second control circuit Tp1 to Tp3 P-channel transistor (drive element) Tn1 to Tn3 N-channel transistor (drive element)

Claims (7)

[Claims] A delay circuit for setting a delay time according to a logical value of a data signal and delaying a clock signal by the delay time; and a holding circuit for holding the data signal based on the delayed clock signal. An input device comprising: 2. The data processing apparatus according to claim 2, wherein the data capturing edge of the clock signal is in a transition period of the data signal, and the data capturing edge of the clock signal is in a transition period of the data signal. The input device according to claim 1, wherein the delay time is set so as to be located after the end. 3. The comparator according to claim 1, wherein the delay unit comprises: a comparator for comparing a timing at a data capturing edge of the clock signal with at least one of a rising edge and a falling edge of the data signal; 3. The input device according to claim 1, further comprising a delay circuit that sets the delay time. 4. A delay comparator comprising: a comparator for comparing a timing of a data capture edge of the clock signal with both rising and falling edges of the data signal; and a comparator for comparing a rising edge of the data signal. A first delay circuit for setting the delay time according to the "H" logical value of the data signal in accordance with the comparison result of the data signal; A second delay circuit for setting the delay time according to the "L" logical value of the data signal; and selecting the delay time of the first delay circuit when the data signal is at the "H" logical value. 3. The input device according to claim 1, further comprising: a selection circuit that selects a delay time of the second delay circuit when the data signal has an “L” logical value. 5. The delay circuit according to claim 3, wherein the delay circuit sets the delay time according to a comparison result of the comparator and a set-up time that guarantees the capture of the data signal. Input device. 6. A driving element for outputting a data signal,
An output circuit capable of adjusting the drive capability of the drive element; and a control circuit receiving a signal indicating the length of the transition period of the data signal, and controlling the drive capability of the output circuit to be higher or lower based on the signal. An output device, characterized in that: 7. The output device according to claim 6, wherein the control circuit receives a signal indicating a length of a transition period of the data signal from an input device that inputs a data signal output from the output device.