JP2000081930A - Reset circuit and resetting method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a reset circuit and a resetting method simplified as compared with conventional circuit and method and capable of reducing a circuit packaging area. SOLUTION: A function for outputting a reset signal is added to a communication controlling LSI 104 in a card and a reset instruction is applied from a processor 101 in the card. Since a reset signal is outputted from the LSI 104 receiving the reset instruction to a device to be reset, a cassette port or the like essential for a conventional card can be reduced from the card and the simplified reset circuit can be provided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a reset circuit and a reset method for resetting a device mounted on the same card or a different card on a card on which a processor and a device are mounted.

[0002]

2. Description of the Related Art A reset circuit of this kind is disclosed in Japanese Utility Model Laid-Open Publication No.
No. 124 publication.

FIG. 4 is a block diagram of a conventional reset circuit. In the reset circuit shown in FIG. 4, a control signal is supplied from the processor 401 to the bus controller 402, and the bus controller 402 controls the processor bus 403. The processor 401 gives instructions and the like necessary to execute reset to the address decoder 404 and the reset port 405 via the processor bus 403.

For example, when resetting the communication control LSI 406, the processor 401 supplies a control signal to the bus controller 402 to
03 for controlling communication with the address decoder 404.
The assigned address area designation data is given to the SI 406, and the condition of the reset signal output is given to the reset port 405.

[0005] The address decoder 404 decodes the encoded address area designation data so that it can be read by the reset port 405 and resets the reset port 4.
Output to 05. On the other hand, the reset port 405 determines an applied reset signal output condition by an internal determination circuit. As a result, when the reset signal output condition is satisfied, the reset signal is output to the communication control LSI 406 specified by the address decoder 404.

Here, the condition of the reset signal output means a specific access from the processor 401, a write access of a specific bit pattern, a series of write access sequence by a specific bit pattern, and the like.

[0007]

However, in the conventional reset circuit, an instruction or the like from the processor 401 is transmitted to the address decoder 404 and the reset port 405.
Since the reset is executed by performing the above processing, the address decoder 404 and the reset port 405 are indispensable, and there is a problem that the circuit board mounting area cannot be reduced.

Further, in a configuration in which a plurality of cards are mounted via a system bus, when resetting is performed by a plurality of cards, an address decoder 404 and a reset port 405 are required on each card. Is more difficult to reduce.

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and has a function of outputting a reset signal to an existing device such as a communication control LSI, thereby reducing an address decoder and a reset port from a card. It is another object of the present invention to provide a reset circuit and a reset method which can be simplified and a circuit mounting area can be reduced as compared with the related art.

[0010]

According to the present invention, a reset command is given to a specific device having a function of outputting a reset signal in addition to the original function of the specific device provided in the card, and this specific device is provided. Sends a reset signal.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A reset circuit according to a first aspect of the present invention adds a function of outputting a reset signal to a specific device provided in a card in addition to a function inherent in the device, and A configuration is adopted in which a reset command is given from the processor to the specific device, and a reset signal is transmitted from the specific device to a device to be reset.

According to this configuration, since the reset signal is transmitted from the specific device to the device to be reset, the number of address decoders and the like can be reduced from the card, and the reset can be performed by a simplified reset circuit. Can be performed.

The reset circuit according to a second aspect of the present invention is the reset circuit according to the first aspect, wherein when resetting the specific device, delaying a reset signal to the own device in consideration of a time required for resetting another device. A configuration having means is adopted.

According to this configuration, since the reset signal is sent to the specific device itself after the time required for resetting the other device has elapsed, the reset is performed without making the operation of the specific device indefinite. be able to.

A reset circuit according to a third aspect of the present invention adds a function of outputting a reset signal to a specific device provided in a master card in addition to a function inherent in the device. A reset command for a device in the slave card is given to the specific device, a reset signal is sent from the specific device to a specific device in the slave card via the system bus, and a reset signal is sent from the specific device to the device to be reset. Is sent.

According to this configuration, a reset signal is sent from a specific device in the slave card in accordance with a reset command from the master card. The reset can be performed without providing a processor in the card.

According to a fourth aspect of the present invention, in the third aspect, the reset circuit according to the third aspect is configured such that, when resetting a specific device in the slave card, the time required for resetting another device in the slave card is taken into consideration. And a delay means for delaying the reset signal to the controller.

According to this configuration, the reset signal is sent to the specific device in the slave card after the time required for resetting the other device in the slave card has elapsed. Reset can be executed without making the operation of the circuit indefinite.

A reset circuit according to a fifth aspect of the present invention is the communication circuit according to any one of the first to fourth aspects, wherein the specific device is a communication control circuit for performing communication control on a card provided in a communication device. And

In the reset circuits according to the first to fourth aspects, the reset can be executed by a simplified reset circuit by applying the communication control circuit which is the specific device.

In the reset method according to a sixth aspect of the present invention, a reset command is supplied from a processor in the same card to a specific device having a function of outputting a reset signal in addition to a function inherent in the device. A reset signal is sent to the reset target device.

According to this method, since the reset signal is sent from the specific device to the device to be reset, the number of address decoders and the like can be reduced from the card, and the reset can be performed by a simplified reset circuit. Can be performed.

The reset method according to a seventh aspect of the present invention is directed to a specific device having a function of outputting a reset signal in addition to an original function of a device provided in a master card, which is provided from a processor in the same master card to a slave device. A specific device that is provided in a slave card via a system bus from a specific device in a master card and that has a function of outputting a reset signal in addition to the original function of the device, by giving a reset instruction for a device in the card And a reset signal is sent from the specific device to the device to be reset.

According to this method, a reset signal is transmitted from a specific device in the slave card in accordance with a reset command from the master card. The reset can be performed without providing a processor in the card.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment 1) FIG. 1 is a block diagram showing a configuration of a reset circuit according to Embodiment 1 of the present invention. In the first embodiment of the present invention, in a communication device in which a plurality of cards are mounted via a system bus, a reset circuit is built on a specific card.

In the reset circuit shown in FIG. 1, a processor 101 is connected to a bus controller 102 and a processor bus 103, and a communication control LSI 104 is connected to the processor bus 103. LS for communication control
The I104 has a communication control function, which is an original function, for example, a function of discriminating various kinds of information in a card constituting the exchange, and a function of outputting a reset signal.

A delay circuit 105 and an extension circuit 106 are connected to the communication control LSI 104. When resetting the communication control LSI itself, the delay circuit 105 delays the reset signal by that time in anticipation of the time required for resetting each device on the card. The extension circuit 106 extends the reset signal until the reset of each device is completed when resetting another device on the card.

Next, the operation of the reset circuit configured as described above will be described with reference to the timing chart shown in FIG. FIG. 2 is a timing chart when the communication control LSI 104 receives a reset command issued by the processor 101 and outputs a reset signal to each device in the card.

First, the processor 101 gives a control signal to the bus controller 102 so that the bus controller 102
To control the processor bus 103. A reset instruction and device designation data are supplied from the processor 101 to the communication control LSI 104 via the processor bus 103. In response to these, the communication control LSI 104
Outputs a reset signal to a specified device.

Since the target device to which the reset signal is output includes the communication control LSI 104, the communication control LSI 104 itself may be reset. At this time, the reset signal for the communication control LSI 104 itself is output before the reset signal for the other device is completely output.
When fed back to itself, the communication control LSI 10
Operation 4 may be undefined.

Therefore, a delay circuit 105 for delaying the pulse signal is provided between the reset output of the communication control LSI 104 and the reset input, and the reset signal is delayed by the time in consideration of the time required for resetting the other devices.
The reset signal is fed back to the communication control LSI 104 itself.

When a reset is performed on each device, there is a slight time difference before the reset is performed depending on each device.
An extension circuit 106 is provided to output a reset signal until reset of all devices is completed.

As described above, according to the reset circuit of the first embodiment, the communication control LSI 104 has a function of designating an address area of a device and outputting a reset signal. Since there is no need to allocate an address area exclusively for the reset port, the circuit size of the address decoder can be reduced. As a result, it is possible to provide a reset circuit that is simpler than the conventional one and can reduce the circuit board mounting area.

(Embodiment 2) FIG. 3 is a block diagram showing a configuration of a reset circuit according to Embodiment 2 of the present invention. Note that the reset circuit according to the second embodiment of the present invention is an example in which a reset circuit is constructed on a plurality of cards in a communication device in which a plurality of cards connected via a system bus are mounted.

In the reset circuit shown in FIG. 3, the configuration inside the master card 301 is the same as that of the first embodiment, except that the communication control LSI 302 outputs a reset signal to the slave card 303. However, the communication control LSI 302 in the master card 301 has the original communication control function as in the first embodiment, and also has a signal conversion function for sharing the difference between the data format in the card and the data format of the system bus 304. have.

The master card 301 can also output a reset signal to devices on the master card 301 by providing the communication control LSI 302 with a function of outputting a reset signal.

Further, a communication control LSI 305 is provided in the slave card 303 as in the master card 301, and a delay circuit 105 and an extension circuit 106 are provided in the slave card 303, which are connected in the same manner as in the first embodiment. However,
Like the communication control LSI 302 of the master card 301, the communication control LSI 305 of the slave card 303 has a function of outputting a reset signal, in addition to having a signal conversion function for sharing the original communication control function and data format. ing.

Next, with respect to the operation of the reset circuit having the above configuration, a process of executing reset will be described.

First, the processor 1 of the master card 301
01 gives a control signal to the bus controller 102 to cause the bus controller 102 to control the processor bus 103. The processor 101 includes a processor bus 103
, The address of the communication control LSI 305 of the slave card 303 to be reset is designated,
A reset instruction is given to the communication control LSI 302 of the master card 301. Further, the communication control LSI 302 that has received the reset command gives the reset command to the communication control LSI 305 of the slave card 303 via the system bus 304. Then, the slave card 303
The communication control LSI 305 outputs a reset signal to each device in the slave card 303.

The processing for resetting the communication control LSI 305 itself in the slave card 303 and the processing for resetting other devices on the slave card 303 are the same as those in the first embodiment. Therefore, the description is omitted.

As described above, according to the reset circuit of the second embodiment, the communication control LSI 305 receives the reset instruction of the processor 101 of the master card 301 and specifies the address area of the device on the slave card 303. And a function of outputting a reset signal.

Thus, when designing a reset circuit composed of a plurality of cards mounted via the system bus 304, the number of reset ports on each card can be reduced from that on the card. Since it is not necessary to allocate an address area to the address card, not only the circuit scale of the address decoder can be reduced, but also the construction of the processor on the slave card can be reduced. As a result, it is possible to provide a reset circuit having a configuration that is more simplified than before, and to reduce the circuit mounting area.

[0044]

As described above, according to the present invention,
Using a specific device with the function of outputting a reset signal when designing a reset circuit, a reset signal is output from this specific device that has received a reset instruction given by the processor, and each device in the card is reset. By designing such a reset circuit, it is possible to provide a reset circuit and a reset method that can be simplified and a circuit mounting area can be reduced as compared with the related art.

The specific device having the function of outputting the reset signal described above can be applied to the case where a reset circuit composed of a plurality of cards mounted via a system bus is designed. Also in this case, it is possible to provide a reset circuit and a reset method that can be simplified on a plurality of cards and can reduce the circuit mounting area.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a reset circuit according to a first embodiment of the present invention;

FIG. 2 is a timing chart of output of a reset signal to each device in a card in the reset circuit according to the first embodiment;

FIG. 3 is a configuration diagram of a reset circuit according to a second embodiment of the present invention;

FIG. 4 is a configuration diagram of a conventional reset circuit.

[Explanation of symbols]

Reference Signs List 101 processor 102 bus controller 103 processor bus 104 communication control LSI 105 delay circuit 106 extension circuit 301 master card in a configuration in which a plurality of cards are mounted on system bus 302 LSI for controlling communication of master card 303 mounting a plurality of cards on system bus Slave card 304 System bus between cards 305 LSI for controlling communication of slave card 404 Address decoder 405 Reset port

Claims (7)

[Claims] 1. A specific device provided in a card is provided with a function of outputting a reset signal in addition to a function inherent in the device, and a processor in the card gives a reset command to the specific device to provide the specific device. A reset signal transmitted from the device to a device to be reset. 2. When resetting the specific device,
2. The reset circuit according to claim 1, further comprising delay means for delaying a reset signal to the own device in anticipation of a time required for resetting another device. 3. A specific device provided in the master card is provided with a function of outputting a reset signal in addition to a function inherent in the device, and a processor in the card is connected to the specific device for a device in the slave card. And a reset signal is sent from the specific device to a specific device in the slave card via the system bus, and a reset signal is transmitted from the specific device to a device to be reset. Reset circuit. 4. When resetting a specific device in the slave card, there is provided delay means for delaying a reset signal to the own device in anticipation of a time required for resetting another device in the slave card. The reset circuit according to claim 3, wherein 5. The reset circuit according to claim 1, wherein the specific device is a communication control circuit that executes communication control on a card provided in a communication device. 6. A reset command is given from a processor in the same card to a specific device having a function of outputting a reset signal in addition to a function inherent in the device, and the reset signal is transmitted from the specific device to a device to be reset. A reset method characterized by doing so. 7. A reset instruction for a device in the same master card from a processor in the same master card to a specific device to which a function of outputting a reset signal is added in addition to the original function of the device provided in the master card From a specific device in the master card to a specific device provided in the slave card via the system bus and added with a function of outputting a reset signal in addition to the original function of the device, and from the specific device, A reset method, wherein a reset signal is transmitted to a device to be reset.