JP2000078047A - Receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a receiver which can suitably incorporate an IC by inputting and delaying a high frequency signal to be received, adding the delay output to the high frequency signal, converting the addition output into an intermediate frequency signal and inputting the conversion output to a demodulation circuit. SOLUTION: The signal inputted to a high frequency signal input terminal 1 is inputted to a 1st delay means 2 whose delay time is set at 5 μ sec. The output of the means 2 is added to the signal inputted to the terminal 1 via an addition circuit 3. Under such conditions, both components of frequency 100 kHz and 300 kHz are canceled with each other since the phase is shifted by 180 deg. between the output signals of the means 2 and the input signal of the terminal 1. Thus, the output of the circuit 3 is set at zero. Meanwhile, the components of frequency OHz, 200 kHz and 400 kHz are strengthened with each other and the output of the circuit 3 is increased. An image elimination filter 10 consists of simple circuit elements such as the means 2 and the circuit 3 and accordingly its circuit is significantly simplified.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a receiver mainly used for a wireless communication device such as a cordless remote controller, a pager, a cordless telephone, and a portable telephone.

[0002]

2. Description of the Related Art FIG. 13 is a block diagram showing a configuration of a conventional receiver. 13, 1 is a high-frequency signal input terminal, 4 is a mixer, 5 is a local signal source, 9 is a demodulation circuit, 1
01 is a crystal filter, and 102 is a ceramic filter. The operation of the conventional receiver will be described. A high-frequency signal input terminal 1 receives a high-frequency signal. Here, as the high-frequency signal, a high-frequency signal received by an antenna may be directly input.
Since the frequency is as high as Hz to several GHz, a signal that is frequency-converted to a fraction of a frequency, that is, several tens of MHz to several hundred kHz, is normally input to the high-frequency signal input terminal 1. Such a configuration in which the demodulation operation is performed after the frequency is lowered by frequency conversion is called a superheterodyne system.

[0006] In FIG. 13, a high-frequency signal input to a high-frequency signal input terminal 1 is input to a crystal filter 101. The role of the crystal filter 101 is to remove the image frequency component of the mixer 4 that follows. The output of the crystal filter 101 is input to the mixer 4 and is frequency-converted by being mixed with the signal of the local signal source 5 to obtain an intermediate frequency signal as the output of the mixer 4.
Here, among the high-frequency signals input to the high-frequency signal input terminal 1, components corresponding to the frequency of the difference between the frequency of the local signal source 5 and the frequency of the intermediate frequency signal and the sum frequency are converted as intermediate frequency signals of the same frequency. Therefore, in order to avoid interference in reception, it is necessary to remove one of the sum frequency component and the difference frequency component among the components of the high-frequency signal in a stage preceding the mixer. The frequency to be removed is called an image frequency, and the filter used for removal is called an image removal filter.

Next, an intermediate frequency signal as an output of the mixer 4 is input to a ceramic filter 102. Here, the role of the ceramic filter 102 is to pass only the components of the reception channel and remove unnecessary channel components. Such a filter used for channel selection is called a channel selection filter. Then, the output of the ceramic filter 102 is input to the demodulation circuit 9 to perform a demodulation operation.

[0005]

However, the problem with the conventional receiver shown in the above-mentioned conventional example is that an image removing filter composed of a crystal filter and the like and a channel selection filter composed of a ceramic filter and the like are separate components. Therefore, it is difficult to form an IC together with other active components.

In recent years, with the development of semiconductor technology, it has become possible to integrate a mixer, a demodulation circuit, and the like into an integrated circuit. The use of ICs can significantly reduce the size and cost of the device. However, it is difficult to make the above-mentioned filters into an IC, which has been a factor restricting miniaturization and cost reduction. SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to provide a receiver provided with an image removal filter suitable for incorporating an IC.

[0007]

According to the present invention, a high-frequency signal to be received is delayed by a first delay means, and the delayed signal and the high-frequency signal before being delayed are added by an adder circuit. After removing the image frequency component, the signal is converted into an intermediate frequency signal by a mixer, and the intermediate frequency signal is demodulated by a demodulation circuit. The operation of the image elimination filter can be performed by the delay means and the adder circuit instead of the individual filter components as in the conventional receiver, so that the circuit configuration of the receiver can be simplified. Further, the above-described configuration is suitable for the built-in IC, so that downsizing and cost reduction can be realized.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention relates to a first delay means for inputting a high-frequency signal to be received, an addition circuit for adding the output of the first delay means and the high-frequency signal, and an output of the addition circuit. A mixer for converting the signal into an intermediate frequency signal,
A demodulation circuit for inputting the output of the mixer.

Also, a first delay means for inputting a high-frequency signal to be received, a subtraction circuit for subtracting the output of the first delay means and the high-frequency signal, and a conversion of the output of the subtraction circuit to an intermediate frequency signal And a demodulation circuit for inputting the output of the mixer. And
Since the function of the image removing filter can be constituted by the delay means and the adding circuit or the subtracting circuit, the circuit of the receiver can be simplified.

A first delay means for inputting a high-frequency signal to be received, a first addition circuit for adding the output of the first delay means and the high-frequency signal, and an output of the first addition circuit A second delay means for inputting the output of the second delay means and a second delay means for adding an output of the second delay means and an output of the first addition circuit.
, A mixer for converting the output of the second addition circuit into an intermediate frequency signal, and a demodulation circuit for inputting the output of the mixer.

Also, a first delay means for inputting a high frequency signal to be received, a first subtraction circuit for subtracting the output of the first delay means from the high frequency signal, and an output of the first subtraction circuit And a second delay unit for subtracting an output of the second delay unit and an output of the first subtraction circuit.
, A mixer for converting the output of the second subtraction circuit into an intermediate frequency signal, and a demodulation circuit for inputting the output of the mixer. Since the delay means and the addition circuit or the subtraction circuit have a two-stage configuration, the amount of attenuation of the image frequency component is increased, and the image interference characteristic can be improved.

Further, one of the first and second delay means is configured such that one delay time T3 is set to be larger than Ta and the other delay time T4 is set to be smaller than Ta. Since the bandwidth of the attenuation of the image frequency component can be widened, image disturbance can be reliably prevented even with a modulated signal having a large band. An amplifier for amplifying the intermediate frequency signal; third delay means for inputting the output of the amplifier; and feedback means for feeding back the output of the third delay means to the input of the amplifier. A channel is selected by feeding back to the input of the amplifier so that negative feedback occurs at a frequency outside the desired band of the intermediate frequency signal. Since the channel selection filter can be constituted by the delay means and the feedback means in addition to the image removal filter, the circuit of the receiver can be further simplified.

The delay means is constituted by a delay element. In addition, since the delay element can be configured on a semiconductor substrate, the size and cost of the device can be reduced by using an IC. The delay means comprises sample-and-hold means and output means for outputting a signal held by the sample-and-hold means after a lapse of a predetermined time, wherein the sample-and-hold means and the output means are operated by a clock signal. Then, the delay means can be constituted by a simple circuit on the semiconductor substrate, and furthermore, it operates with a clock signal, so that the delay time can be set with high accuracy.

[0014] Further, a reference signal source is provided, and the operation timing of the delay element is determined by a clock signal obtained by dividing the output of the reference signal source. A reference signal source is provided, and the operation timing of the sample and hold means and the output means is determined by a clock signal obtained by dividing the output of the reference signal source.

Further, since the delay elements of the image removal filter and the channel selection filter or the clock signals of the sample and hold means and the output means can be obtained from one reference signal source, the circuit can be further simplified. Further, the mixer is configured by an image reduction mixer that attenuates the image frequency of a high-frequency signal. Then, the amount of attenuation of the image frequency component can be further increased.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. (Embodiment 1) FIG. 1 is a block diagram showing a configuration of an embodiment of a receiver according to the present invention. In FIG. 1, 1 is a high-frequency signal input terminal, 2 is first delay means, 3 is an addition circuit,
Is a mixer, 5 is a local signal source, 6 is an amplifier, 7 is third delay means, 8 is feedback means, 9 is a demodulation circuit, 10 is an image removal filter, and 11 is a channel selection filter.

The operation of the receiver according to this embodiment will be described. A high-frequency signal input terminal 1 receives a high-frequency signal. Here, as the high-frequency signal, a high-frequency signal received by an antenna may be directly input, but the high-frequency signal received by the antenna has a high frequency of several hundred MHz to several GHz. That is, a signal whose frequency has been converted to tens of MHz to hundreds of kHz is input to the high-frequency signal input terminal 1.

In this embodiment, 400M received by the antenna
Consider a case where a high frequency signal of 1 Hz is converted into a frequency of 400 kHz and then input to the high frequency signal input terminal 1. Now,
In FIG. 1, a signal input to a high-frequency signal input terminal 1 is input to a first delay unit 2. Here, the delay time of the first delay means 2 is set to 5 μsec. Then, the output of the first delay means 2 and the signal input to the high frequency signal input terminal 1 are added by an adding circuit 3. At this time, the components having frequencies of 100 kHz and 300 kHz are out of phase by 180 degrees between the output signal of the first delay means 2 and the input signal of the high-frequency signal input terminal 1, and cancel each other, so that the output of the adding circuit 3 becomes zero. Become. Also,
The components of 0 Hz, 200 kHz and 400 kHz are reciprocally strengthened, and the output of the adding circuit 3 increases. That is,
The component at 400 kHz among the components of the output of the adder circuit 3 is large, and the component at 300 kHz is zero. Here, the amplitude of each output is based on AC amplitude. Thus, the image removing filter 10 is configured. Next, the output of the addition circuit 3 is input to the mixer 4 and the frequency 3
The signal is mixed with the output of the local signal source 5 set to 50 kHz and converted to a frequency of 50 kHz, which is an intermediate frequency signal. At this time, the necessary frequency component is 400 kHz and the image frequency component is 300 kHz. However, since the 300 kHz component has been removed as described above, no image disturbance occurs.

In the above arrangement, the delay time of the first delay means 2 is T0, the period of the high-frequency signal input to the high-frequency signal input terminal 1 is T1, and the period of the intermediate frequency signal output from the mixer 4 is T1. Is defined as T2, T0 = 5 μs
c, T1 = 2.5 μsec and T2 = 20 μsec, so T0 = Ta = nxT1 (1), T2 = 4 × nxT1
It can be seen that (2) is satisfied, which corresponds to the case where n = 2. T0 and T are set to satisfy the above equations (1) and (2).
1. By selecting T2, it is possible to remove the image frequency component by passing through the component of the receiving channel. In the above formula, n is a positive integer. When T1 is determined in advance, n can be any value equal to or greater than 1. If n is selected to be large, the frequency of the intermediate frequency signal can be lowered, so that the demodulation operation is facilitated. However, since the filter characteristic becomes sharp and the frequency band in which the image can be removed becomes narrow, n may be determined in consideration of the modulation band to be used.

Next, after the output of the mixer 4 is input to the channel selection filter 11 to remove frequency components other than the reception channel, the demodulation circuit 9 performs a demodulation operation. Here, the channel selection filter 11 can use individual components such as a ceramic filter, but can be realized by the following configuration. The intermediate frequency signal output from the mixer 4 is input to the amplifier 6. After the output of the amplifier 6 is time-delayed by the third delay means 7, the output is fed back to the input of the amplifier 6 by the feedback means 8. Here, the delay time of the third delay means is set to 10 μsec, and the amplifier 6 is a gain-one amplifier that outputs a voltage difference between two input signals (the output of the mixer 4 and the output of the feedback means 8). The feedback means 8 attenuates the amplitude of the input signal by 0.9 times and outputs the signal. The 50 kHz component which is the intermediate frequency signal at the output of the mixer 4 is the third component.
Since the phase of the output of the delay means 7 is shifted by exactly 180 degrees, the amplitude is reinforced by the feedback to the amplifier 6 by the feedback means 8 to increase the amplitude. However, no oscillation occurs because the amplitude is limited to 0.9 times by the feedback means 8. On the other hand, the component of the output of the mixer 4 having a frequency apart from the frequency of 50 kHz becomes negative feedback, and the output amplitude of the amplifier 6 and the third delay means 7 decreases. Accordingly, a filter characteristic is obtained in which a component of 50 kHz, which is a frequency corresponding to the reception channel, is passed and other components are attenuated. Thus, the channel selection filter 11 is configured.

The image elimination filter 10 constructed in this embodiment can be composed of simple circuit elements such as the first delay means 2 and the addition circuit 2, so that the circuit can be greatly simplified. Here, the first delay means 2 can be easily constituted by, for example, a capacitor, a resistor or a coil, and the adder circuit 3 can be easily realized by an operational amplifier or the like. Therefore, downsizing and cost reduction can be realized as compared with the case where individual components such as a conventional quartz filter are used.

The channel selection filter 11 constructed in this embodiment can be composed of simple circuit elements such as the third delay means 7, the feedback circuit 8 and the amplifier 6, so that the circuit can be greatly simplified. Here, the third delay means 7 can be constituted by a capacitor, a resistor, a coil, or the like, like the first delay means 2, and the feedback means 8 can be easily set by setting the output amplitude by resistance division using, for example, two resistors. Can be configured. Also, the amplifier 6 can be easily realized by an operational amplifier or the like. Therefore, size reduction and cost reduction can be realized as compared with the case where individual components such as a conventional ceramic filter are used.

In this embodiment, the channel selection filter 1
Although the amplifier 6 is used as one component, a similar effect can be obtained by using a subtraction circuit. Also, the feedback amplitude of the feedback means 8 is set to 0.9 times, but by making this value closer to 1 time, the out-of-band attenuation of the channel selection filter can be increased.

(Embodiment 2) FIG. 2 is a block diagram showing the configuration of a receiver according to Embodiment 2 of the present invention. In FIG. 2, reference numeral 12 denotes a subtraction circuit. The same components as those in FIG. 1 are denoted by the same reference numerals. The difference between the present embodiment and the first embodiment is that a subtraction circuit 12 is used instead of the addition circuit.

The operation of this embodiment is basically the same as that of the first embodiment, except that the delay time of the first delay means and the frequency of the intermediate frequency signal are different. The delay time of the first delay circuit 2 of this embodiment is set to 6.25 μsec. The frequency of the receiving channel input to the high-frequency signal input terminal is 400 kHz, which is the same as that in the first embodiment, but the local signal source 5 is set to 360 kHz, and the frequency of the intermediate frequency signal output from the mixer 4 is 40 kHz. .

In the above arrangement, the delay time of the first delay means 2 is T0, the period of the high-frequency signal input to the high-frequency signal input terminal 1 is T1, and the period of the intermediate frequency signal output from the mixer 4 is T1. Is defined as T2, T0 = 6.25
Since μsec, T1 = 2.5 μsec, and T2 = 25 μsec, T0 = Ta = (2 × n−1) × T1 / 2-(1),
T2 = (4 × n−2) × T1 --- (2) is satisfied, and n =
It turns out that it corresponds to the case of 3. By selecting T0, T1, and T2 so as to satisfy the above equations (1) and (2), it is possible to pass the components of the reception channel and remove the image frequency components. In the above formula, n is a positive integer.

In this embodiment, the configuration of the image removing filter can be simplified in substantially the same manner as in the first embodiment, so that the receiver can be reduced in size and cost. Further, the image rejection filter having the configuration of the present embodiment cancels out and attenuates components near the frequency of 0 Hz, and thus has an advantage that it is less affected by DC voltage drift and low frequency noise.

(Embodiment 3) FIG. 3 is a block diagram showing the configuration of a receiver according to Embodiment 3 of the present invention. In FIG. 3, reference numeral 14 denotes a second delay unit. The same components as those in FIG. 1 are denoted by the same reference numerals. The difference between the present embodiment and the first embodiment is that the configuration of the image removal filter used in the first embodiment is configured in two stages in series. Example 1
In order to sufficiently attenuate the image frequency component in the adding circuit 3, the amplitudes of the two signals (the signal that has passed through the delay means and the signal that has not passed) are exactly the same. Need to be.

Further, the addition error of the addition circuit 3 needs to be sufficiently small. However, it may be difficult to completely satisfy the above conditions in an actual circuit. That is, it is conceivable that an error occurs due to variations in elements constituting the circuit, temperature characteristics, and the like. In the configuration of the present embodiment, in addition to the image removing filter constituted by the first delay means 2 and the adding circuit 3,
The second delay means 14 and the adding circuit 3 also constitute an image removing filter. First and second delay means 2, 1
4 are both set to 5 μsec.

According to this configuration, since the characteristic obtained by multiplying the attenuation of the image frequency component of the two image removing filters is obtained, the attenuation can be increased. As a result, necessary image removal characteristics can be ensured even if an error occurs in the circuit as described above. In this embodiment, the image removing filter has a two-stage configuration. However, the image removing filter may have three or more stages. In this case, the attenuation of the image frequency can be further increased.

In this embodiment, the delay times of the first and second delay means 2 and 14 are both set to Ta = 5 μsec. For example, the delay time T3 of the first delay means 2 is set to 5
To 5.2 μsec larger than μsec, the delay time T4 of the second delay means 14 is set to 4.8 μsec smaller than 5 μsec.
By setting to c, the frequency bandwidth for performing image removal can be increased. As a result, even when the modulation signal has a large modulation band, the image frequency component can be reliably removed.

Further, although the addition circuit is used, it is also possible to use a subtraction circuit. (Embodiment 4) FIG. 4 is a block diagram showing a configuration of a receiver according to Embodiment 4 of the present invention. In FIG. 4, 15 is B
The BD delay element 16 is a clock signal source. The same components as those in FIG. 1 are denoted by the same reference numerals.

In the present embodiment, BBD (b
ucket brigade device) A delay element is used. BB
The D delay element 15 operates by a clock signal output from the clock signal source 16. The use of a BBD delay element as the delay means has the following advantages. Since the delay time of the BBD delay element 15 is determined by the clock frequency and the number of stages forming the BBD, an accurate delay can be realized by increasing the frequency accuracy of the clock signal source 16.
As a result, it is possible to obtain an image removal filter that accurately attenuates image frequency components. The accuracy of the clock signal source 16 can be improved by using a crystal oscillator or the like.

Further, the BBD delay element can be formed on a semiconductor substrate, so that it is suitable for use as an IC in a receiver. Further, by making the frequency of the clock signal source 16 variable, the frequency to be removed by the image removal filter can be changed. In this embodiment, a BBD delay element is used as a delay element. However, a so-called CTD (charge
A similar configuration can be obtained using a transfer device. Also, a SAW delay element can be used.

(Embodiment 5) FIG. 5 is a block diagram showing the configuration of an image removing filter which is a component of Embodiment 5 of the receiver according to the present invention. In FIG. 5, 3 is an adder, 17
Is an input terminal, 18 is an output terminal, 19 is a buffer amplifier with a gain of 1, 20 is a sample-and-hold circuit input switch, 2
1 is an output means switch, 22 is a main path switch, 23 is a capacitor, and 24 is a low pass filter.

The overall configuration of the receiver of this embodiment is the same as that of FIG. 1, and the internal configuration of the image removing filter 10 shown in FIG. 1 is shown in FIG. In FIG. 5, a high-frequency signal input to the input terminal 17 is 600 kHz in advance by a filter.
Components of z or more have been removed. This is to prevent aliasing distortion in a series of processes described below. Input terminal 1
The high frequency signal input to 7 is input to the main path switch 22 and the sample and hold circuit input switch 20 via the buffer amplifier 19. Here, a sample and hold circuit is constituted by the sample and hold circuit input switch 20 and the capacitor 23. When the sample-and-hold circuit input switch 20 is momentarily turned ON, the capacitor 23 is charged with electric charge, and the terminal voltage of the capacitor 23 becomes equal to the buffer amplifier output voltage. Next, when the output means switch 21 is momentarily turned ON, the voltage is transmitted to the addition circuit 3. At the same time, the main path switch 22
When it becomes N, the output voltage of the buffer amplifier 19 is transmitted to the addition circuit 3, and the addition result is output. In this embodiment, the image frequency filter is configured to have three stages connected in series to increase the attenuation of the image frequency component.
The low-pass filter 24 is for removing a harmonic component, and has a characteristic of attenuating a frequency component of 600 kHz or more.

In FIG. 5, C1 attached to each switch
Symbols such as 1 and C12 indicate the type of clock signal for operating the switch. Table 1 shows the periods and initial phases of these clock signals.

[0038]

[Table 1]

In Table 1, Td represents the initial phase in time. The pulse width of these clock signals is set sufficiently smaller than the period. FIG. 8 shows a passing amplitude characteristic of the image removing filter having this configuration. 400
The high-frequency signal component of kHz, that is, the reception channel component passes, and the image frequency of 300 kHz is attenuated.

Here, the characteristics when the configuration of the image removal filter is slightly changed will be described. FIG.
Compared to the above example, the amplitude of the clock signal of the three-stage image removing filter is slightly larger in one stage, slightly smaller in one stage, and shows a passing amplitude characteristic when one stage is not changed. This corresponds to the case where the delay time of each delay unit is set to a different value in the third embodiment. It can be seen that the attenuation band of the image frequency becomes large, and even a modulated signal having a large band can be removed.

As a method of setting the delay times to different values, the configuration shown in FIG. 7 can be used. FIG.
In the above, 27 is an auxiliary delay element. The same components as those in FIG. 5 are denoted by the same reference numerals. FIG.
Since the auxiliary delay element 27 is inserted into the path including the main path switch 22 of the second-stage image removing filter in (2), a part of the delay time on the delay path side (path including the output means switch 21) is partially canceled. Delay time is reduced. Further, by inserting the auxiliary delay element 27 on the delay path side of the third-stage image removing filter, a substantial delay time is increased. With such a configuration, characteristics similar to those in FIG. 12 can be obtained. The advantage of using the auxiliary delay element 27 is that the frequency of the clock signal can be made the same in each stage, so that the circuit configuration can be simplified.

FIG. 10 shows the passing amplitude characteristic when the subtraction circuit is used instead of the addition circuit in the configuration shown in FIG.
This corresponds to a case where the image removing filter has a three-stage configuration in the configuration shown in the second embodiment. However, unlike the case of the above example, the clock signal needs to be changed.
Now, the configuration of the channel selection filter will be described.

FIG. 6 is a block diagram showing a configuration of a channel selection filter which is a component of the fifth embodiment of the receiver according to the present invention. In FIG. 6, 12 is a subtraction circuit, 25 is a switch, and 26 is a resistor. The same components as those in FIG. 6 are denoted by the same reference numerals. In FIG. 6, the intermediate frequency signal input to the input terminal 17 has components of 75 kHz or higher removed in advance by a filter. This is to prevent aliasing distortion in a series of processes described below. Symbols such as C41 and C42 attached to each switch indicate the type of clock signal for operating the switch, and the cycle and initial phase are shown in FIG. The output of the output means switch 21 is output from the buffer amplifier 19 having a gain of 1. Here, the feedback means is 9 kΩ and 0.85 k
It consists of two resistance divisions of Ω, and the voltage determined by this division is fed back to the subtraction circuit 12. The channel selection filter of this configuration has a five-stage series connection, and the first and second stages, the third and fourth stages, and the fifth stage operate with clock signals having the same frequency. The three clock frequencies are used to increase the pass frequency band.
The center frequency of the receiving channel is 50 kHz. The low-pass filter 24 is for removing harmonic components and has a characteristic of attenuating components of 75 kHz or more.

FIG. 9 shows the passing amplitude characteristic of the channel selection filter having this configuration. It can be seen that the light passes components within 50 kHz ± 4 kHz and attenuates components of 50 kHz ± 12.5 kHz or more by 50 dB or more. Now, as shown in Table 1, clock signals for operating the image removal filter and the channel selection filter of the present configuration are all crystal oscillators Xtal (20 MHz) which are reference signal sources.
It is obtained by dividing the signal of z). First, Xta
Divide l by 2 to obtain C0 (10 MHz). The frequency is further divided by 10 to obtain clock signals C11 to C16, which are used for the operation of the image removing filter. After the C0 is divided by 50, the frequency is further divided by 3 to obtain clock signals C21 to C23, which are used for the operation of the fifth stage of the channel selection filter. Similarly, clock signals C31 to C33, which are obtained by dividing C0 by 53 and 47 and further dividing by three, and C3
41 to C43 are the third and fourth stages, and the first and second stages, respectively.
Used for stage operation.

As described above, the fact that the clock signals of all the circuits can be obtained by one reference signal source means that, for example, when the filter of this configuration is integrated into an IC, the circuit configuration for obtaining the clock signal can be easily configured, 1 external crystal oscillator
Since only a single unit is sufficient, it is advantageous for miniaturization and cost reduction of the receiver. (Embodiment 6) FIG. 12 shows a receiver according to Embodiment 5 of the present invention.
FIG. 3 is a block diagram showing the configuration of FIG. In FIG. 12, 28
Is an image reduction mixer. The same components as those in FIG. 1 are denoted by the same reference numerals. A feature of the receiver of the present embodiment is that an image reduction mixer 28 is provided in addition to the image removal filter 10 for removing an image.

In order to ensure sufficient attenuation of image frequency components in the image removing filter 10, there is a method of increasing the number of stages as described in the third embodiment. Where 1
The amount of attenuation that can be realized by the stage is approximately 30 dB, and in practice, an amount of attenuation of approximately 60 dB is often required. In this embodiment, an image reduction mixer 28 is used as another method. As the image reduction mixer 28, a general configuration including a quadrature mixer, a phase shifter, and an adder circuit can be used. Since the amount of attenuation of the image frequency component of the image reduction mixer 28 can be realized at about 30 dB, the attenuation amount of the image
Is obtained. This configuration has an advantage that the number of stages of the image removing filter 10 can be reduced, so that the circuit scale can be reduced.

[0047]

As apparent from the above description, the following effects can be obtained according to the receiver of the present invention. First delay means for inputting a high-frequency signal to be received, an adder circuit for adding the output of the first delay means and the high-frequency signal, a mixer for converting the output of the adder circuit to an intermediate frequency signal, Since a demodulation circuit for inputting an output is provided, the circuit configuration can be greatly simplified, and individual components such as a crystal filter need not be used. Therefore, downsizing and cost reduction of the receiver can be realized.

A first delay means for inputting a high-frequency signal to be received, a first addition circuit for adding the output of the first delay means and the high-frequency signal, and an output of the first addition circuit are input. Second delay means, an output of the second delay means and a first
A second adder for adding the outputs of the adders, a mixer for converting the output of the second adder to an intermediate frequency signal, and a demodulator for inputting the output of the mixer. The amount of attenuation of the image frequency component of the filter unit can be increased, and interference due to image interference can be prevented.

The delay time T0 of the first or second delay means is Ta = n × T1, with respect to the period T1 of the high-frequency signal.
(N is a positive integer), and the period T2 of the intermediate frequency signal is T2 = 4 × nxT1.
Therefore, the image frequency component can be surely removed and the component of the reception channel can be passed.

Further, since one of the first and second delay means, the delay time T3 is set to be longer than Ta and the other delay time T4 is set to be shorter than Ta, the frequency bandwidth for performing image removal is reduced. Even if the modulation signal has a large modulation band, the component of the image frequency can be reliably removed. An amplifier for amplifying the intermediate frequency signal;
Third delay means for inputting the output of the amplifier, and feedback means for feeding the output of the third delay means back to the input of the amplifier;
The feedback means selects the channel by feeding back to the input of the amplifier so that it becomes negative feedback at the frequency outside the desired band of the intermediate frequency signal, so that the function of the channel selection filter in addition to the image rejection filter is realized by the same delay means. Thus, the circuit configuration can be simplified, and downsizing and cost reduction can be realized as compared with the case where individual components such as ceramic filters are used.

Further, since the first, second or third delay means is constituted by a delay element, it can be formed on a semiconductor substrate, which is a structure suitable for integrating the receiver into an IC. Since the delay time is determined by the clock signal, the frequency accuracy can be improved. The first, second, or third delay means includes sample and hold means and output means for outputting a signal held by the sample and hold means after a predetermined time has elapsed. The sample and hold means and the output means are provided with a clock signal. , It can be configured with a simple circuit, and further can be configured on a semiconductor substrate, which is a configuration suitable for integration of a receiver into an IC. Since the delay time is determined by the clock signal, the frequency accuracy can be improved.

Further, since the reference signal source is provided and the operation timing of the delay element is determined by the clock signal obtained by dividing the output of the reference signal source, the circuit configuration of the receiver is simplified and Since only one attached crystal oscillator is required, the size and cost of the receiver can be reduced. Further, since the mixer is configured by an image reduction mixer that attenuates the image frequency of a high-frequency signal, the number of stages of the image removal filter unit can be reduced, and the circuit scale can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram of a receiver according to a first embodiment of the present invention.

FIG. 2 is a block diagram of a receiver according to a second embodiment of the present invention.

FIG. 3 is a block diagram of a receiver according to a third embodiment of the present invention.

FIG. 4 is a block diagram of a receiver according to a fourth embodiment of the present invention.

FIG. 5 is a circuit diagram of an image removing filter 1 which is a component of a receiver according to a fifth embodiment of the present invention.

FIG. 6 is a circuit diagram of a channel selection filter that is a component of the receiver.

FIG. 7 is a circuit diagram of an image removing filter 2 which is a component of the receiver.

FIG. 8 is a diagram showing a passing amplitude characteristic of an image removing filter 1 which is a component of the receiver.

FIG. 9 is a diagram showing a passing amplitude characteristic of a channel selection filter which is a component of the receiver.

FIG. 10 is another transmission amplitude characteristic diagram of the image rejection filter 1 that is a component of the receiver.

FIG. 11 is a diagram showing a transmission amplitude characteristic of an image removal filter 2 which is a component of the receiver.

FIG. 12 is a block diagram of a receiver according to a sixth embodiment of the present invention.

FIG. 13 is a block diagram of a conventional receiver.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 high-frequency signal input terminal 2 first delay means 3 addition circuit 4 mixer 5 local signal source 6 amplifier 7 third delay means 8 delay means 9 demodulation circuit 10 image removal filter 11 channel selection filter 12 subtraction circuit 14 second delay Means 15 BBD delay element 16 Clock signal source 20 Sample hold circuit input switch 21 Output means switch 23 Capacitor 24 Low pass filter 26 Resistance 27 Auxiliary delay element 28 Image reduction mixer

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5K020 DD01 DD02 EE01 EE04 EE05 EE16 FF00 HH13 5K052 AA01 BB02 BB20 DD04 FF01 GG12 GG19 GG32 GG33 GG42

Claims (13)

[Claims] 1. A first delay means for inputting a high-frequency signal to be received, an addition circuit for adding the output of the first delay means and the high-frequency signal, and converting the output of the addition circuit to an intermediate frequency signal. And a demodulation circuit for receiving an output of the mixer. 2. A first delay means for inputting a high-frequency signal to be received, a subtraction circuit for subtracting the output of the first delay means from the high-frequency signal, and converting the output of the subtraction circuit to an intermediate frequency signal. And a demodulation circuit for receiving an output of the mixer. 3. A first delay means for inputting a high-frequency signal to be received, a first addition circuit for adding the output of the first delay means and the high-frequency signal, and an output of the first addition circuit. , A second adder for adding the output of the second delay and the output of the first adder, and the output of the second adder as an intermediate frequency signal. A receiver comprising: a mixer for conversion; and a demodulation circuit for receiving an output of the mixer. 4. A first delay means for inputting a high-frequency signal to be received, a first subtraction circuit for subtracting the output of the first delay means from the high-frequency signal, and an output of the first subtraction circuit. , A second subtraction circuit for subtracting an output of the second delay means and an output of the first subtraction circuit, and an output of the second subtraction circuit to an intermediate frequency signal. A receiver comprising: a mixer for conversion; and a demodulation circuit for receiving an output of the mixer. 5. The delay time T0 of the first or second delay means.
Is set to be equal to Ta defined by Ta = n × T1, where n is a positive integer, with respect to the period T1 of the high-frequency signal, and the period T2 of the intermediate frequency signal is expressed by T2 = 4 × nxT1. The receiver according to claim 1 or 3, configured to satisfy. 6. The delay time T0 of the first or second delay means.
Is Ta = (2 × n−1) × with respect to the period T1 of the high-frequency signal.
It is configured to be the same as Ta defined by T1 / 2 (n is a positive integer), and the period T2 of the intermediate frequency signal is T2 =
The receiver according to claim 2, wherein the receiver is configured to satisfy (4 × n−2) × T1. 7. A delay time T3 of one of the first and second delay means is set to be longer than Ta, and the other delay time T3 is set to be longer than Ta.
7. The receiver according to claim 5, wherein 4 is set smaller than Ta. 8. An amplifier for amplifying an intermediate frequency signal, third delay means for inputting the output of the amplifier, and feedback means for feeding back the output of the third delay means to the input of the amplifier. 2. The channel selection means according to claim 1, wherein said feedback means feeds back to said input of said amplifier so that negative feedback occurs at a frequency outside a desired band of said intermediate frequency signal.
The receiver according to any one of claims 1 to 7. 9. The receiver according to claim 1, wherein the first, second, or third delay means comprises a delay element. 10. The first or second or third delay means comprises a sample and hold means and an output means for outputting a signal held by the sample and hold means after a lapse of a predetermined time, wherein the sample and hold means and the output are provided. 9. The receiver according to claim 1, wherein the means operates with a clock signal. 11. The receiver according to claim 9, further comprising a reference signal source, wherein the operation timing of the delay element is determined by a clock signal obtained by dividing the output of the reference signal source. 12. The receiver according to claim 10, further comprising a reference signal source, wherein the operation timing of the sample-and-hold means and the output means is determined by a clock signal obtained by dividing the output of the reference signal source. 13. The receiver according to claim 1, wherein the mixer comprises an image reduction mixer for attenuating an image frequency of a high-frequency signal.