JP2000077656A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device improved in such a manner that element characteristic can be improved by restraining the increase in a junction leakage current and junction capacitance. SOLUTION: In this semiconductor device, a first semiconductor layer 15 and a second semiconductor layer 15 are arranged on both sides of a gate electrode 11 on a semiconductor substrate 1, electrically isolated from the gate electrode 11. A source 17 and a drain 17 whose one ends intrude into the main surface of the semiconductor substrate 1 and are connected with the edge of a channel are formed on the surface layers of the first and second semiconductor layers 15, 15.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device.
The present invention relates to a transistor which is used for memory and logic with high performance. The invention also relates to a method for manufacturing such a transistor.

[0002]

2. Description of the Related Art FIGS. 9 to 13 show conventional documents (Paul J.
Tsang et al., IEEE Trans. Electron Devices, ED-29
Vol., P. 590 (1982)).
It is a figure showing the manufacturing method of ET.

Referring to FIG. 9, an element isolation region 2 for isolating an active region from other active regions is formed on a main surface of a p-type silicon substrate 1 whose main surface is a (100) plane.
A pad oxide film 3 is formed on a silicon substrate 1. Boron, which is a p-type impurity, is ion-implanted into the surface of the silicon substrate 1 through the pad oxide film 3 to form a well 7 and a punch-through stopper 8.

Referring to FIGS. 9 and 10, pad oxide film 3 is formed.
Is removed, a gate oxide film 9 is formed on the surface of the silicon substrate 1.
To form Thereafter, an n-type polysilicon layer is deposited, and thereafter, is patterned by a lithography technique to form an n-type polysilicon gate electrode 11.

[0005] Referring to FIG. 11, arsenic or phosphorus as an n-type impurity is obliquely rotated and ion-implanted into the surface of silicon substrate 1 to form LDD (lightly doped drain) 23.

Referring to FIG. 12, a side wall spacer 19 is formed on the side wall of gate electrode 11 with a dielectric such as a silicon oxide film or a silicon nitride film.

Referring to FIG. 13, arsenic, which is an n-type impurity, is implanted into the main surface of silicon substrate 1, and thereafter, thermal annealing is performed to form n ⁺ source / drain 20. Thereby, the main part of the device is completed.

[0008]

SUMMARY OF THE INVENTION Conventional NMOSFET
Was configured as described above. Therefore, when trying to improve the punch-through resistance for miniaturization,
Referring to FIG. 13, it is necessary to increase the impurity concentration of punch-through stopper 8 introduced over the entire surface of the substrate. The punch-through stopper 8 is formed so as to cover the LDD 23 and the source / drain 20 in order to suppress the depletion layer from extending from the LDD 23 and the source / drain 20 in the channel direction. Therefore, when the impurity concentration of the punch-through stopper 8 is increased, the p-type impurity concentration under the source / drain is increased, so that the junction leakage current and the junction capacitance are increased, and there is a problem that the element characteristics are deteriorated.

SUMMARY OF THE INVENTION An object of the present invention is to provide an improved semiconductor device capable of suppressing an increase in junction leak current and junction capacitance and improving element characteristics.

Another object of the present invention is to provide a method for manufacturing such a semiconductor device.

[0011]

According to a first aspect of the present invention, there is provided a semiconductor device having a channel near a main surface of a semiconductor substrate, and a source region and a drain region connected to both ends of the channel. The semiconductor device includes a semiconductor substrate. A gate electrode is provided on the semiconductor substrate with a gate oxide film interposed. A first semiconductor layer and a second semiconductor layer are provided on the semiconductor substrate and on both sides of the gate electrode so as to be electrically separated from the gate electrode. In the surface layer of the first semiconductor layer, a source region is provided, one end of which penetrates into the main surface of the semiconductor substrate and is connected to one edge of the channel. On the surface of the second semiconductor layer,
One end extends into the main surface of the semiconductor substrate, and a drain region connected to the other edge of the channel is provided.

According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device having a channel near a main surface of a semiconductor substrate and having a source region and a drain region connected to both ends of the channel. A gate electrode is formed on a semiconductor substrate. A sidewall spacer is formed on a side wall of the gate electrode. A first semiconductor layer and a second semiconductor layer are selectively grown on the semiconductor substrate and on both sides of the gate electrode, respectively. Impurity ions are implanted into the main surface of the semiconductor substrate and the surface layers of the first and second semiconductor layers, whereby impurity ions are provided on the surface layer of the first semiconductor layer, and one end of the impurity is provided on the main surface of the semiconductor substrate. Digging in,
A source region connected to one edge of the channel, and a source region provided on a surface of the second semiconductor layer, one end of which penetrates into a main surface of the semiconductor substrate and is connected to the other edge of the channel; And a drain region.

According to a third aspect of the present invention, in the method of manufacturing a semiconductor device, the width of the side wall spacer is set to 20 nm or less, and the implantation energy of the impurity ions is reduced by the first and second degrees. The thickness is selected to be equal to or greater than the thickness of the portion of the second semiconductor layer in contact with the sidewall spacer and equal to or less than a value obtained by adding 20 nm to the thickness.

According to a fourth aspect of the present invention, the method for selectively growing the first and second semiconductor layers is performed by an ultrahigh vacuum chemical vapor deposition method.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings.

Embodiment 1 In Embodiment 1, a CMOS comprising an NMOSFET and a PMOSFET will be described.

Referring to FIG. 1, an element isolation region 2 is formed on a (100) plane p-type silicon substrate 1. A pad oxide film 3 is formed on the surface of a silicon substrate 1.

Although not shown, phosphorus or arsenic as an n-type impurity is ion-implanted by masking the PMOS region to form an n-type well 4 and a punch-through stopper 5. Thereafter, a resist 6 is formed in the PMOS region,
Boron, which is a p-type impurity, is ion-implanted into the MOS region to form a p-type well 7 and a punch-through stopper 8. After that, the pad oxide film 3 is removed.

Referring to FIG. 2, a gate oxide film 9 is formed on the surface of silicon substrate 1, and p-type polysilicon gate electrode 10 and n-type polysilicon gate electrode 11, metal layer 12, silicon oxide film or silicon A nitride film 13 is deposited. Thereafter, although not shown, a resist having a gate pattern is formed by lithography, the oxide film 13 is etched using the resist as a mask, and the metal layer 12 and the polysilicon gate electrode 1 are further etched using the oxide film 13 as a mask.
Etch 0,11. Here, p-type polysilicon gate electrode 10 and n-type polysilicon gate electrode 11
Is formed by depositing non-doped polysilicon and then introducing impurities into it by ion implantation or the like.

Referring to FIG. 3, thin (about 3 to 20 nm) side wall spacers 14 are formed on the side walls of gate electrodes 10 and 11 with a silicon oxide film or a silicon nitride film. At this time, the gate oxide film other than the gate oxide film immediately below the gate electrodes 10 and 11 is removed. After that, in the source / drain regions where the silicon surface is exposed, an ultra-high vacuum chemical vapor deposition apparatus (UHV-
An n-type selective epitaxial layer (hereinafter, referred to as a semiconductor layer) 15 is selectively grown to a thickness of about 20 nm or more by CVD or the like.

Here, H. Hada et al., IEEE IDEM, p. 665 (1995), and Y. Nakahara et al., IEEE Symposium on VLSI T
echnology Digest of Technical Papers, p. 174 (199
As disclosed in 6) and the like, by appropriately controlling the growth conditions, isotropic growth, (111) and (311) can be achieved.
And the like, and a semiconductor layer having a trapezoidal cross section as shown in the figure can be grown.

FIG. 4 is an enlarged view of a portion A in FIG. Here, referring to FIG. 4, the thickness of a portion of semiconductor layer 15 in contact with sidewall spacer 14 is represented by t.

Referring to FIG. 5, an n-type source / drain 17 is formed by obliquely rotating ion implantation of phosphorus or arsenic, which is an n-type impurity, by covering the PMOS region with a resist 16. Here, the energy of the ion implantation is determined by the degree of projection flight (Rp) in the depth direction of the impurity, t>
It is set so that Rp> t + 20 nm. The optimum value of the implantation angle varies depending on the shape of the semiconductor layer 15 and the like, but is preferably about 0 to 45 degrees.

Similarly, referring to FIG. 6, the p-type source / drain 1 is formed by obliquely rotating ion implantation of boron or boron fluoride as a p-type impurity into the PMOS region.
8 is formed. Thereafter, the main part of the element is completed by thermal annealing.

According to the CMOS of the first embodiment, the source / drain 17 and 18 are formed in the silicon substrate 1 near the channel edge. However, other portions of the source / drain 17 and 18 are formed above the substrate surface. In order to effectively suppress punch-through, the source / drain 17 and 18 near the channel edge are in contact with the punch-through stoppers 5 and 8, but the other portions of the source / drain 17 and 18 are , 8 apart from each other. Therefore, even if the impurity concentration of the punch-through stoppers 5 and 8 is increased for miniaturization, increase in junction leak current and junction capacitance is suppressed, and element characteristics can be improved.

Referring to FIG. 6, source / drain 17 and 18 are formed in the surface layer portion of semiconductor layer 15. However, even if they are formed deeper, source / drain near the channel edge of silicon substrate 1 is formed. As long as it is formed shallower than (a portion embedded in the substrate), an increase in junction leak current and junction capacitance can be sufficiently suppressed.

Second Embodiment In the first embodiment, the impurity diffusion layers 17 and 18 formed on the surface of the semiconductor layer 15 are used as the source and the drain. 17 and 18 cannot be formed too deeply. for that reason,
There is a concern that device characteristics may be degraded due to an increase in parasitic resistance.

Therefore, in the second embodiment, as shown in FIG. 7, a second side wall spacer 19 is formed at the boundary between the side wall spacer 14 and the semiconductor layer 15.
Using the resist 16 as appropriate, an n-type impurity 20 is implanted into the NMOS region and a p-type impurity 21 is ion-implanted into the PMOS region. Further, referring to FIG. 8, silicide layer 22 is formed in a self-aligned manner only in a region where the surface of semiconductor layer 15 is exposed (salicide). As a result, a source / drain with a small parasitic resistance can be formed.

Third Embodiment In the first and second embodiments, a dual-gate CMOS in which n-type polysilicon is used for an NMOSFET and p-type polysilicon is used for a PMOSFET as a gate electrode has been described. The present invention is not limited to this, and the same effects can be obtained by applying the present invention to a single-gate CMOS in which both NMOS and PMOS have n-type polysilicon as gate electrodes (the PMOS becomes a buried channel type).

Further, in the first and second embodiments, the semiconductor layer is selectively grown in the region serving as the source / drain. However, the present invention is not limited to this, and the semiconductor layer is selectively deposited in the region where the silicon surface is exposed. Any material that can be used may be metal. In that case, it is desirable that the source / drain is formed even in the silicon substrate. If a metal is deposited, the resistance of the source / drain is reduced, so that the element characteristics are also improved.

[0031]

As described above, according to the present invention, the source / drain is formed in the silicon substrate near the channel edge, but is located above the substrate surface except near the channel edge. Also, the source / drain near the channel edge should be
It is in contact with the punch-through stopper, but is apart in other areas. Therefore, even if the impurity concentration of the punch-through stopper is increased for miniaturization, it is possible to suppress an increase in junction leakage current and junction capacitance, and to improve element characteristics. Furthermore, as a method of manufacturing,
Since a semiconductor layer was formed on the drain part and ion-implanted,
The impurity profile of the source / drain can be made deeper only at the channel edge in a self-aligned manner, and an increase in the number of steps can be suppressed.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a semiconductor device in a first step in a sequence of a method of manufacturing a semiconductor device according to a first embodiment.

FIG. 2 is a cross-sectional view of the semiconductor device in a second step in the order of the method of manufacturing the semiconductor device according to the first embodiment;

FIG. 3 is a cross-sectional view of the semiconductor device in a third step in the order of the method of manufacturing the semiconductor device according to the first embodiment;

FIG. 4 is an enlarged view of a portion A in FIG.

FIG. 5 is a sectional view of the semiconductor device in a fourth step in the order of the method of manufacturing the semiconductor device according to the first embodiment;

FIG. 6 is a sectional view of the semiconductor device in a fifth step in the order of the method of manufacturing the semiconductor device according to the first embodiment;

FIG. 7 is a cross-sectional view of the semiconductor device in a first step in the sequence of the method of manufacturing the semiconductor device according to the second embodiment.

FIG. 8 is a cross-sectional view of the semiconductor device in a second step in the sequence of the method for manufacturing the semiconductor device according to the second embodiment.

FIG. 9 is a cross-sectional view of a semiconductor device in a first step in a sequence of a conventional method of manufacturing a semiconductor device.

FIG. 10 shows a second example of the sequence of the conventional method for manufacturing a semiconductor device.
13 is a cross-sectional view of the semiconductor device in a step of FIG.

FIG. 11 shows a third example of a sequence of a conventional method of manufacturing a semiconductor device.
13 is a cross-sectional view of the semiconductor device in a step of FIG.

FIG. 12 shows a fourth example of the order of the conventional method of manufacturing a semiconductor device.
13 is a cross-sectional view of the semiconductor device in a step of FIG.

FIG. 13 shows a fifth example of the sequence of the conventional method for manufacturing a semiconductor device.
13 is a cross-sectional view of the semiconductor device in a step of FIG.

[Explanation of symbols]

1 Silicon substrate, 9 Gate oxide film, 10, 11 Gate electrode, 15 Semiconductor layer, 17, 18 Source / drain.

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Satoshi Yamakawa 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Mitsui Electric Co., Ltd. (72) Inventor Yasutaka Nishioka 2-3-2 Marunouchi, Chiyoda-ku, Tokyo F term in Ryo Denki Co., Ltd. (reference) 5F040 DA10 DA12 DA18 DB03 DC01 EC01 EC07 EC12 EF01 EH02 EH08 EM00 FA03 FA05 FA07 FA16 FA17 FA18 FA19 FC06 FC13

Claims (4)

[Claims] 1. A semiconductor device having a channel near a main surface of a semiconductor substrate and having a source region and a drain region connected to both ends of the channel, comprising: a semiconductor substrate; and a gate oxide on the semiconductor substrate. A gate electrode provided with a film interposed therebetween; and a first semiconductor layer provided on the semiconductor substrate and on both sides of the gate electrode so as to be electrically separated from the gate electrode. A second semiconductor layer, a source region provided on a surface layer of the first semiconductor layer, one end of which extends into a main surface of the semiconductor substrate and is connected to one edge of the channel; A semiconductor device provided on a surface layer of a semiconductor layer, one end of which penetrates into a main surface of the semiconductor substrate and is connected to the other edge of the channel; 2. A method of manufacturing a semiconductor device having a channel near a main surface of a semiconductor substrate and having a source region and a drain region connected to both ends of the channel, wherein a gate electrode is formed on the semiconductor substrate. Forming a sidewall spacer on the side wall of the gate electrode; and selecting a first semiconductor layer and a second semiconductor layer on the semiconductor substrate and on both sides of the gate electrode, respectively. Implanting impurity ions into the main surface of the semiconductor substrate and the surface layers of the first and second semiconductor layers, whereby
A source region provided at a surface layer of the first semiconductor layer, one end of which extends into a main surface of the semiconductor substrate and is connected to one edge of the channel; and a source region provided at a surface layer of the second semiconductor layer. Forming one end thereof into the main surface of the semiconductor substrate to form a drain region connected to the other edge of the channel. 3. The width of the sidewall spacer is set to 20.
nm or less, and the implantation energy of the impurity ions is adjusted so that the projection degree in the depth direction of the impurity is less than that of the first and second semiconductor layers.
3. The method according to claim 2, wherein the thickness is selected to be equal to or greater than a thickness of a portion in contact with the sidewall spacer and equal to or less than a value obtained by adding 20 nm to the thickness. 4. The semiconductor device according to claim 2, wherein the method for selectively growing the first and second semiconductor layers is performed by an ultrahigh vacuum chemical vapor deposition method. Production method.