JP2000077514A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent dishing by forming a trench element isolation region on the surface of a semiconductor substrate, forming a psuedo-active region on the surface or on an active region for forming a semiconductor element which are defined by the trench element isolation region, and constituting an element isolation region by the psuedo-active region and the trench element isolation region. SOLUTION: Active regions 13, 14, 23, and 24 and psuedo-active regions (a) to (j) defined by a trench element isolation region on the surface of a semiconductor substrate 1 are formed, and a resist pattern 6 is formed on the active regions 13, 14, 23, and 24 and psuedo-active regions (a) to (j). A silicon nitride film 5 and a silicon oxide film 4 in an opening are etched while using the resist pattern as a mask, so as to remove them and form a groove 7. Then, the surface of the silicon substrate 1 on the bottom and side of the groove 7 is oxidized to form a silicon oxide film 8, and the silicon oxide film 8 is ground/etched back in a manner so as to leave the inside of the groove 7, forming an element isolation region.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a method of forming an isolation region of an integrated circuit device.

[0002]

2. Description of the Related Art With the increase in the degree of integration of integrated circuit elements, not only the elements themselves but also the element isolation regions have been miniaturized. A trench element isolation technique has been developed instead of the LOCOS method. According to this trench element isolation technique, as shown in FIG. 6, grooves 42a and 42b are formed in a portion to be an element isolation region on the surface of a semiconductor substrate 41, and grooves 42a and 42b are formed.
2b is buried with an insulating film 43 such as a silicon oxide film,
This is a method of flattening the surface of the insulating film 43 by an MP (chemical mechanical polishing) method.

However, in the method of etching back by the CMP method, in a groove having a large width such as the groove 42b, a phenomenon called "dishing" occurs in which the polishing of the central portion of the groove 42b proceeds and the insulating film 43 becomes thin. Further, in the minute (for example, several μm width) active region 44 surrounded by the wide groove 42b,
Polishing cannot be stopped at the silicon nitride film 45 disposed on the semiconductor substrate 41 and functioning as an etching stopper, and a phenomenon called “erosion” occurs in which the surface of the semiconductor substrate 41 is polished.

On the other hand, there has been proposed a method of preventing dishing and erosion by disposing a pseudo active region in a wide element isolation region (for example, Japanese Patent Application Laid-Open Nos. 8-288380 and 9-98). 181159, JP-A-9-232417, etc.). One example is described below. First, as shown in FIG. 7A, a pad silicon oxide film 52, a silicon nitride film 53, and a resist pattern 54 are formed on a silicon substrate 51.
Here, the resist pattern 54 is a resist pattern that defines active regions 55a to 55e in which semiconductor elements are finally formed and pseudo active regions 65a to 65d formed in element isolation regions.

Next, as shown in FIG. 7B, grooves 56a to 56h are formed by anisotropically etching the silicon nitride film 53, the silicon oxide film 52 and the silicon substrate 51 using the resist pattern 54 as a mask. . In a narrow element isolation region such as 56a and 56b, element isolation is performed by a single narrow groove. In a wide element isolation region, the grooves 56c, 56d, and 56e and the pseudo active regions 65a and 65b are formed.
Or the trenches 56f, 56g, 56h and the pseudo active regions 65c, 65d perform element isolation.

Subsequently, as shown in FIG.
On the silicon substrate 51 including 6a to 56h, grooves 56a to 56h are formed.
A silicon oxide film 57 having a thickness greater than the depth of 56h is formed. Next, as shown in FIG. 7D, using the silicon nitride film 53 as an etching stopper, the silicon oxide film 57 is etched back by CMP until the silicon nitride film 53 is exposed. At this time, in the wide element isolation region, the pseudo active regions 65a, 65b and 65c, 65d
Thereby, CMP can be effectively stopped at the silicon nitride film 53 on these surfaces, and "dicing" and "erosion" can be prevented.

Next, as shown in FIG. 8E, the silicon nitride film 53 and the pad silicon oxide film 52 are removed with a heated phosphoric acid solution and dilute hydrofluoric acid solution, respectively, and the threshold voltages of the well and the transistor are determined. After the impurity implantation, a gate insulating film 58 and a gate electrode 59 are formed on the silicon substrate 51. Further, as shown in FIG. 8F, a resist pattern 60 having an opening at least on the active regions 55b and 55c where the NMOS is to be formed is formed according to a normal process, and using this as a mask, N-type impurities are increased. The source / drain regions 61 are formed by ion implantation at a concentration (1 × 10 ^{15 to} 5 × 10 ¹⁵ / cm ² ). At this time, the resist pattern 60 is partially covered with the pseudo active region 65.
a, 65d.
An N-type diffusion layer 62 is formed on the surface of a, 65d or the like. Since the resist pattern 60 is formed on some of the pseudo active regions 65b and 65c, no N-type diffusion layer is formed on the surface thereof.

[0008] Subsequently, as shown in FIG. 8 (g), an opening is formed on at least an active region (not shown) in which a PMOS is to be formed and an active region 55 f in which a P-type diffusion layer is to be formed according to a normal process. A resist pattern 63 having a P-type impurity is formed at a high concentration (1 × 10
^A source / drain region (not shown) and a P-type diffusion layer 64 are formed by ion implantation at ^{15 to} 5 × 10 ¹⁵ / cm ² ). At this time, since the resist pattern 63 has an opening also on a part of the pseudo active region 65b, the pseudo active region 65b
A P-type diffusion layer 64 is formed on the surface of the substrate. Note that the P-type diffusion layer 64 formed on the surface of the active region 55d functions as a contact connection portion to the silicon substrate 51 or the P-type well.

Next, as shown in FIG. 8 (h), after removing the resist pattern 63 according to a normal process, a heat treatment for activating the implanted impurities is performed, and the interlayer insulating film 6 is formed.
6, the formation of the contact plug 67, the formation of the metal wiring 68, and the like complete the semiconductor device. But,
In the region where the pseudo active region is arranged, the thickness of the insulating film between the metal wiring and the silicon substrate becomes thinner by the element isolation trench, and there is a problem that the parasitic capacitance between the metal wiring and the substrate increases. . In particular, when the pseudo active region is formed by the above method, a high-concentration diffusion layer of a conductivity type different from that of the silicon substrate or the well is not necessarily formed on the surface of the pseudo active region. A high-concentration diffusion layer of the same conductivity type as the substrate or the well is not formed, or the high-concentration diffusion layer itself is not formed. Therefore, regardless of the potential of the metal wiring, a depletion layer due to the PN junction does not occur on the surface of the pseudo active region. Therefore, the parasitic capacitance is determined only by the thickness of the interlayer insulating film between the metal wiring and the pseudo active region. The Rukoto.

For example, if the thickness T _imd of the interlayer insulating film is 800
nm, the depth D _sti of the isolation trench is 300 nm
At this time, the parasitic capacitance per unit area between the metal wiring and the substrate is, assuming a parallel plate type capacitance, in the trench portion and the pseudo active region portion, respectively.

[0011]

(Equation 1)

(Where ε is the relative dielectric constant of the silicon oxide film,
ε ₀ indicates the dielectric constant of a vacuum), and the parasitic capacitance of the pseudo active region is about 1.4 times that of the trench. However, in practice, a high concentration impurity is not added to the substrate surface in the trench, so that a depletion layer spreads on the substrate surface due to the metal wiring potential. Therefore, it is considered that the parasitic capacitance of the trench becomes smaller than the above calculated value, and the difference from the parasitic capacitance of the pseudo active region is further increased.

Therefore, from the viewpoint of reducing the parasitic capacitance, it is desirable that the occupation area of the pseudo active region in the element isolation region is as small as possible. On the other hand, as described above, in order to prevent "dicing" and "erosion", about 30%
The above occupation ratio of the pseudo active region is required. For example, the parasitic capacitance between the metal wiring arranged on the element isolation region and the substrate is as follows: if there is no pseudo active region, if the area of the metal wiring is A _metal , then C _para0 = A _metal × C _groove ( 3) When there is a 30% pseudo active region, C _para30 = 0.7 × A _metal × C _groove + 0.3 × A _metal × C _quasi (4)

Therefore, when 30% of the pseudo active region exists in the element isolation region, the increase rate of the parasitic capacitance is as follows:

[0015]

(Equation 2)

Approximately 12%. Moreover, it is a very simple assumption, but delays due to wiring of a semiconductor device is proportional to the CR product of the parasitic capacitance × the wiring resistance and the power consumption of the wiring portion is proportional to fCV ^2/2, the calculation Therefore, there is a problem that each of them increases by 10% or more, which greatly hinders speeding up and reducing power consumption of the semiconductor device.

[0017]

According to the present invention, there is provided a semiconductor substrate having a first conductivity type region, a trench isolation region formed on a surface of the semiconductor substrate, and a semiconductor device formation defined by the trench isolation region. A semiconductor device comprising a pseudo active region having a second conductivity type diffusion layer on a surface thereof and a trench element isolation region and the pseudo active region.

Further, according to the present invention, there is provided the semiconductor device according to the above, wherein the impurity diffusion layer is formed in the active region for forming the semiconductor element on the semiconductor substrate and the second conductivity type diffusion layer is formed on the surface of the pseudo active region. A manufacturing method is provided.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device according to the present invention mainly comprises a semiconductor substrate, an element isolation region and an active region formed on the surface of the semiconductor substrate, and a semiconductor element formed on the semiconductor substrate. The semiconductor substrate in the semiconductor device of the present invention has a first conductivity type region. The material of the semiconductor substrate is not particularly limited, and for example, a semiconductor such as silicon or germanium, or a compound semiconductor such as GaAs or InGaAs can be used. Among them, a silicon substrate is preferable. The first conductivity type region included in the semiconductor substrate may be formed by doping a P-type or N-type impurity, and the entire semiconductor substrate may be set to the first conductivity type. , At least one first conductivity type region may be formed as an impurity diffusion region (well). The concentration of the impurity at this time is not particularly limited as long as it is a concentration usually doped in the semiconductor substrate or the impurity diffusion region, and for example, is about 1 × 10 ^{16 to} 5 × 10 ¹⁸ ions / cm ^3. .

On the surface of the semiconductor substrate, a trench element isolation region is formed. The trench element isolation region means a region in which a trench is formed on the surface of a semiconductor substrate, an insulator is buried in the trench, and the surface is usually planarized. The depth of the trench can be adjusted so that sufficient device isolation is ensured by the performance of the semiconductor device formed on the semiconductor substrate and the like.
And a depth of about 1.0 μm. The trench element isolation region can be formed by a known trench element isolation method. For example, after forming an insulating film such as an oxide film and a nitride film on a semiconductor substrate, an opening is formed in the insulating film over the trench formation region by a photolithography and etching process, and a desired depth and A trench having a size is formed, and then an insulating film such as an oxide film is deposited on the semiconductor substrate including the trench, preferably as a thicker film than the trench depth, and is etched back by a CMP method or the like to insulate the trench. There is a method of burying the body.

On the surface of the semiconductor substrate, an active region for forming a semiconductor element defined by the above-described trench element isolation region is formed. The shape, size, arrangement, and the like of the active region are not particularly limited, and can be appropriately adjusted according to the function, application, and the like of the semiconductor device to be obtained. Examples of the semiconductor element formed in the active region include various elements such as a transistor, a capacitor, and a resistor. These may be formed alone or in combination. For example, in addition to a CMOS device, a DRAM, an SR
It may constitute a memory device such as an AM or FLASH memory.

Further, the semiconductor substrate in the semiconductor device of the present invention has a pseudo active region. The pseudo active region is not formed for forming a semiconductor device like an active region for forming a semiconductor device, or for connection with a wiring diffusion layer, a semiconductor substrate, an impurity diffusion region, or the like. It means a region formed to sufficiently secure the function of the separation region. Thus, the pseudo active region is
An element isolation region is formed together with the above-described trench element isolation region. The pseudo active region is almost the same as a normal active region where no element is formed, except that the pseudo active region has a second conductivity type diffusion layer on its surface. Here, the second conductivity type is
When the first conductivity type is P type, it means N type, and when the first conductivity type is N type, it means P type. Only one pseudo active region may be formed in one element isolation region, or a plurality of pseudo active regions may be formed. Also, its shape, size,
As described above, the arrangement can be appropriately adjusted in order to sufficiently secure the function of the trench element isolation region. The second conductivity type diffusion layer formed in the pseudo active region is preferably formed over the entire surface of the pseudo active region,
The impurity concentration is 5 × 10 ¹⁹ to 1 × 10 ²¹ ions / cm.
^{About 3} are mentioned. Further, the second conductivity type diffusion layer is preferably formed in a region shallower than the trench bottom in the trench isolation region, and when the depth of the trench isolation region is about 0.3 to 1.0 μm. The thickness of the second conductivity type diffusion layer is, for example, about 0.1 to 0.2 μm.

In the semiconductor device of the present invention, usually, a trench isolation region is formed in a semiconductor substrate, a first conductivity type region is formed in a semiconductor substrate, and a gate insulating film and a gate electrode are formed in an active region. / Drain region is formed to form a transistor, and an interlayer insulating film, a contact hole, a metal wiring, and the like are formed on the transistor, thereby completing the transistor. Each of these steps can be performed by a method usually used in a method of manufacturing a semiconductor device. Note that in such a step, a step of forming a trench element isolation region;
And the step of forming the first conductivity type region may be performed first. Further, when a transistor is formed in the active region, either an N-type transistor or a P-type transistor may be formed, or both N-type and P-type transistors may be formed. In this case, both the N-type and P-type transistors may be formed first. Also, the above ~
Before, during, and after the step, formation of different elements such as a capacitor, ion implantation for controlling a threshold voltage of a transistor, formation of a sidewall spacer on a side wall of a gate electrode, formation of an LDD region, formation of a diffusion layer Appropriate steps may be added according to the intended use, function, performance, etc. of the semiconductor device, such as formation of wiring.

In the present invention, the second conductivity type impurity diffusion layer is formed in the active region for forming the semiconductor element on the semiconductor substrate, and at the same time, the second conductivity type diffusion layer is formed on the surface of the pseudo active region. Preferably, specifically, in the above step, a second conductivity type diffusion layer is formed on the surface of the pseudo active region using an appropriate mask when forming source / drain regions in the active region of the semiconductor substrate. Is preferred. In the case where a diffusion layer wiring is formed in a part of the active region other than the above-described steps 1 to 3, the surface of the pseudo active region is formed by using an appropriate mask when forming the diffusion layer wiring. It is preferable to form a second conductivity type diffusion layer.

Hereinafter, embodiments of a semiconductor device and a method of manufacturing the same according to the present invention will be described with reference to the drawings. As shown in FIGS. 1 and 2A and 2B, a CMOS inverter as an embodiment of the semiconductor device of the present invention has an active region 13 in a P-type well 12 formed in a silicon substrate 1. NM on top
The OS has a PMOS on the active region 23 in the N-type well 22.
Are formed respectively.

The NMOS includes a gate electrode 15 formed on the active region 13 with a gate insulating film 17 interposed therebetween, and a source / drain region 16 formed in the silicon substrate 1 in self-alignment with the gate electrode 15. Is formed. The PMOS is formed by a gate electrode 25 formed on the active region 23 with the gate insulating film 17 interposed therebetween, and a source / drain region 26 formed in the silicon substrate 1 in self-alignment with the gate electrode 25. ing. In addition,
The gate electrodes 15 and 25 are formed by the same continuous pattern.

One source / drain region 16 of the NMOS is connected to a metal wiring 2a disposed on the NMOS via an interlayer insulating film 3, and is supplied with a first reference potential. The metal wiring 2a is formed on the P-type diffusion layer 1 formed on the surface of the active region 14 in the P-type well 12.
8 is also used to apply a first reference potential to the P-type well 12. Similarly, the PMOS source region 26
Is connected to a metal wiring 2c disposed on a PMOS via an interlayer insulating film 3, and is supplied with a second reference potential. The metal wiring 2c is used to apply a second reference potential to the N-type well 22 through the N-type diffusion layer 19 formed on the surface of the active region 24 in the N-type well 22.

Further, a metal wiring 2d functioning as an input line to the CMOS inverter is connected to the common gate electrodes 15 and 25 of the NMOS and the PMOS.
The MOS and PMOS drain regions 26 have CMOS
Metal wiring 2b functioning as an output line to the inverter is connected. Further, in the P-type well 12 and the N-type well 22 in the CMOS inverter, the region where the gate electrodes 15 and 25 are provided and the active region 13 are provided.
At regular intervals, rectangular pseudo-active regions a to j are formed in the element isolation regions other than the regions where 14, 23 and 24 are formed.
Are formed. Of these pseudo active regions, N type diffusion layers 19 are formed on the surfaces of the pseudo active regions a to e in the P type well 12, and are formed on the surfaces of the pseudo active regions f to j in the N type well 22. Has a P-type diffusion layer 18 formed therein. As a result, a PN junction is formed on the surfaces of the pseudo active regions a to j.

By having such a configuration, for example,
For example, in the pseudo active region b, as shown in FIG.
Thus, the parasitic capacitance between the metal wiring 2a and the silicon substrate 1
Quantity C _paraIs the capacitance C of the interlayer insulating film 3_imdAnd PN junction
Total capacity C_pnSeries capacitance with

[0030]

(Equation 3)

Is given by In addition, since C _imd / C _pn > 0 when there is a PN junction capacitance C _pn , C _para > C _pn . By forming a PN junction on the surface of the pseudo active region, the metal wiring 2a and the substrate 1 Parasitic capacitance C _para between
Can be reduced. In addition, pseudo active regions a, c to
Similarly, in the case of j, the wiring parasitic capacitance can be reduced by forming a PN junction on the surface.

More specifically, the interlayer insulating film 3
Interlayer capacitance C per unit area _imdIs the film thickness T
_imdIs 600 nm,

[0033]

(Equation 4)

(Where ε is the relative permittivity of the oxide film, and ε ₀ is the vacuum permittivity). On the other hand, the PN junction capacitance C _pn per unit area of the surface of the pseudo active region is

[0035]

(Equation 5)

Where ε _s is the dielectric constant of silicon, W _d is the width of the depletion layer of the PN junction, q is the elementary charge (here, the N-type well or P-type well concentration), V _bi is the built-in potential, Is the voltage applied to the PN junction), and N
^{= 3 × 10 17 / cm 3} , V = 0V, T = at room temperature, C _pn
≒ 130 nF / cm ² .

Therefore, the parasitic capacitance C _para is _calculated from the equation (6).

[0038]

(Equation 6)

The parasitic capacitance when there is no PN junction on the surface of the pseudo active region (for example, when the surface of the pseudo active region in the N-type well is an N-type conductive layer), C _para = C _imd = 5.75 nF / cm ^As compared with ² , the wiring parasitic capacitance can be reduced by about 4%. Hereinafter, a method of manufacturing the CMOS inverter will be described with reference to the drawings.

As shown in FIG. 3A, after a pad silicon oxide film 4 is deposited on the surface of a P-type silicon substrate 1 by a thermal oxidation method in a thickness of 10 to 30 nm, a silicon nitride film 5 is formed in a thickness of 100 to 250 nm by an LPCVD method. accumulate. next,
As shown in FIG. 3B, the active regions 13, 14, 2
A resist pattern 6 having an opening formed by a photolithography process is formed in regions 3 and 24 and regions to be pseudo active regions a to j in the element isolation region. Using the resist pattern 6 as a mask, the silicon nitride film 5 and the silicon oxide film 4 in the opening are removed by etching by RIE, and the silicon substrate 1
The trench 7 is formed by digging down by 00 nm.

Subsequently, as shown in FIG. 3C, after the resist pattern 6 is removed by ashing, the silicon substrate surface on the bottom and side surfaces of the groove 7 is thinly oxidized to about 10 to 50 nm to form a silicon oxide film. (Not shown). At this time, since the silicon nitride film 5, which is an oxidation-resistant film, exists on the surfaces of the active regions 13, 14, 23, and 24 and the pseudo active regions a to j, no silicon oxide film is formed on the surface of the silicon substrate 1. After that, the groove 7 is completely buried, and the silicon oxide film 8 is formed in a thickness of 400 to 8
Deposit 00 nm. It is preferable that the thickness of the silicon oxide film 8 be equal to or larger than the step of the groove 7, the silicon oxide film 4, and the silicon nitride film 5.

Next, as shown in FIG. 4D, the silicon oxide film 8 is polished and etched back by the CMP method until the surface of the silicon nitride film 5 is exposed. The film 8 is left. At this time, the silicon nitride film 5
Acts as a CMP stopper. Also, the pseudo active region a
Since ~ j are arranged in the element isolation region, dishing and erosion, which are problems specific to CMP, can be prevented, and a flat surface can be obtained.

Next, as shown in FIG. 4E, after the silicon nitride film 5 is removed by etching with a heated phosphoric acid solution, a resist pattern 9 processed into a desired shape by a photolithography process is formed. Using this as a mask, the implantation energy is changed into the silicon substrate 1 to
Four times ion implantation of phosphorus is performed to form an N-type well 22. At this time, the depth of the N-type well 22 needs to be deeper than the groove 7, and at least one ion implantation is 300 to 6 times.
It is preferable to carry out at 00 keV or more. Further, the ion implantation amount at each time is set to 1 × 10 ^{12 to} 5 × 10 ¹³ cm ⁻² in accordance with desired PMOS characteristics and N-type well resistance.

As shown in FIG. 4F, after the resist pattern 9 is removed by ashing, the resist pattern 10 is processed into a desired shape by a photolithography process.
Then, using this as a mask, boron ions are implanted into the silicon substrate 1 two to four times while changing the implantation energy, thereby forming a P-type well 12. At this time, the depth of the P-type well 12 needs to be deeper than the
The ion implantation is preferably performed at 200 to 400 keV or more. In addition, the ion implantation amount at each time is a desired NMO.
1 × 10 ^{12 to} 5 × according to S characteristics and P-type well resistance
Perform at 10 ¹³ cm ^-2 .

Next, as shown in FIG. 4G, after the resist pattern 10 is removed by ashing, the silicon oxide film 4 is removed by etching with a diluted hydrofluoric acid solution, and the gate insulating film 17 is formed on the surface of the silicon substrate 1 again. Is formed in a thickness of 3 to 10 nm. Subsequently, polysilicon (or a multi-layer film of polysilicon such as tungsten silicide and the like) is deposited by a CVD method for 150 hours.
After depositing a thickness of about 300 nm, gate electrodes 15 and 25 are formed on the active regions 13 and 23 by a photolithography and etching process. Next, ions are implanted into the surface of the silicon substrate 1 for LDD formation (not shown) using the gate electrodes 15 and 25 as a mask according to a normal process.
Thereafter, a silicon nitride film is formed on the entire surface of the silicon substrate 1 by CV.
After depositing 50 to 150 nm by the D method, the spacer insulating film 20 is formed on the side walls of the gate electrodes 15 and 25 in a self-aligned manner by etching back by the RIE method.

Thereafter, as shown in FIG. 5H, a resist pattern 31 is formed which covers the active region 24 in the N-type well 22 and further covers all regions except the active region 14 in the P-type well 12. Using this as a mask, BF ₂ ions are implanted at an implantation energy of 20 to 60 keV to 2 to 5 × 1.
Inject 0 ¹⁵ cm ^-2 . As a result, a P-type diffusion layer 18 is formed on the surface of the active region 14 and the pseudo active regions f to j.
In the active region 23, the source / drain regions 26 of the PMOS are formed in a self-aligned manner on the surface of the silicon substrate 1 using the gate electrode 25 and the spacer insulating film 20 as a mask. At this time, the polysilicon forming the gate electrode 25 is also doped with P-type.

As described above, the P-type diffusion layer 18 is formed simultaneously with the active region 14 and the source / drain region 26 on the surfaces of the pseudo active regions f to j without adding a new step, thereby forming a PN junction. Can be configured. Next, as shown in FIG. 5I, a resist pattern 32 is formed to cover the active region 14 in the P-type well 12 and further cover all regions except the active region 24 in the N-type well 22. Using this as a mask, As ions are 20 to 60 k
Inject 2 to 5 × 10 ¹⁵ cm ⁻² with eV implantation energy. As a result, an N-type diffusion layer 19 is formed on the surface of the active region 24 and the pseudo active regions a to e. Also, the active region 1
3, the gate electrode 15 and the spacer insulating film 20
NM on the surface of the silicon substrate 1 in a self-aligned manner
An OS source ^/ drain region 16 is formed. In addition,
At this time, the polysilicon forming the gate electrode 15 is also N
Doped into the mold.

As described above, the N-type diffusion layer 19 is formed simultaneously with the active region 24 and the source / drain region 16 on the surfaces of the pseudo active regions a to e without adding a new step, thereby forming a PN junction. Can be configured. Subsequently, as shown in FIG.
Is subjected to ashing heat treatment at 700 to 900 ° C. for several tens of minutes or rapid heat treatment at 1000 to 1100 ° C. for several seconds, or both heat treatments.
4, 23, 24 and the pseudo active regions a to j and the boron and arsenic implanted into the gate electrodes 15, 25 are activated.

Next, as shown in FIG. 2A, according to a normal process, an interlayer insulating film 3 having a thickness of about 600 to 900 nm is deposited, a contact opening is formed, and a contact plug is formed by burying tungsten or the like. The metal wirings 2a to 2d made of Al-Cu or the like are formed to complete the CMOS inverter according to the present embodiment.

[0050]

According to the present invention, since a pseudo active region having a second conductivity type diffusion layer on the surface thereof is provided in an element isolation region, dishing and erosion by CMP, which have conventionally been problems, can be prevented. In addition, the parasitic capacitance between the metal wiring and the silicon substrate in the pseudo active region can be reduced. Further, due to this, the wiring delay speed roughly given by the CR product is improved, the circuit speed can be reduced, the power consumption can be reduced, and the device characteristics can be improved.

Further, according to the present invention, it is not necessary to add a new process for forming a pseudo active region having a second conductivity type diffusion layer on the surface, and it is performed in a conventional semiconductor device manufacturing process. This makes it possible to manufacture a semiconductor device with improved characteristics as described above simply and without increasing the manufacturing cost.

[Brief description of the drawings]

FIG. 1 is a schematic plan view of a main part showing one embodiment of a semiconductor device of the present invention.

FIG. 2A is a sectional view taken along line AA ′ of FIG. 1,
FIG. 2B is an enlarged sectional view of a main part of FIG.

FIG. 3 is a manufacturing process sectional view for illustrating the method for manufacturing a semiconductor device of the present invention.

FIG. 4 is a manufacturing process sectional view for illustrating the method for manufacturing a semiconductor device of the present invention.

FIG. 5 is a manufacturing process sectional view for illustrating the method for manufacturing a semiconductor device of the present invention.

FIG. 6 is a schematic cross-sectional view of a main part for describing a conventional semiconductor device.

FIG. 7 is a cross-sectional view showing a manufacturing process for explaining another conventional method for manufacturing a semiconductor device.

FIG. 8 is a cross-sectional view showing a manufacturing process for explaining another conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Silicon substrate 2a-2d Metal wiring 3 Interlayer insulating film 4 Silicon oxide film 5 Silicon nitride film 6, 9, 10 Resist pattern 7 Groove 8 Silicon oxide film 12 P-type well 13, 14, 23, 24 Active region 15, 25 Gate Electrodes 16, 26 Source / drain region 17 Gate insulating film 18 P-type diffusion layer 19 N-type diffusion layer 20 Spacer insulating film 22 N-type well ae pseudo active region

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/336 F-term (Reference) 5F032 AA35 AA44 AA77 CA14 CA17 DA02 DA03 DA22 DA23 DA24 DA33 DA53 5F040 DA01 DA02 DB01 DB03 DB09 DB10 DC01 DC03 EA08 EK05 FC10 FC21 5F048 AA04 AB01 AC01 AC03 AC10 BA01 BA15 BB05 BG14

Claims (5)

[Claims] A semiconductor substrate having a first conductivity type region; a trench isolation region formed on a surface of the semiconductor substrate; and a semiconductor device defined by the trench isolation region.
Pseudo-type having active region for formation and diffusion layer of second conductivity type on surface
Consists of a similar active region,  By the trench element isolation region and the pseudo active region
A semiconductor device comprising an element isolation region. 2. The semiconductor device according to claim 1, wherein the second conductivity type diffusion layer on the surface of the pseudo active region is formed in a region shallower than the trench bottom in the trench isolation region. 3. The semiconductor device according to claim 1, wherein an impurity diffusion layer is formed in an active region for forming a semiconductor element on a semiconductor substrate, and a second conductivity type diffusion layer is formed on a surface of the pseudo active region. A method for manufacturing a semiconductor device. 4. When forming a MOS transistor comprising a gate insulating film, a gate electrode and a source / drain region in an active region for forming a semiconductor element on a semiconductor substrate, the surface of the pseudo active region is formed simultaneously with the formation of the source / drain region. 4. The method for manufacturing a semiconductor device according to claim 3, wherein a second conductivity type diffusion layer is formed on the semiconductor device. 5. A diffusion layer wiring is formed in a part of an active region for forming a semiconductor element on a semiconductor substrate, and simultaneously with forming the diffusion layer wiring, a second conductivity type diffusion layer is formed on a surface of the pseudo active region. The method for manufacturing a semiconductor device according to claim 3, wherein the forming is performed.