JP2000076864A - Memory circuit, microcomputer using it and its control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a memory circuit whose operating speed can be made variable by providing an external switch by which the number of memory transistors constituting a memory cell is made variable and by which the number of memory transistors is changed over to one piece or a plurality of pieces by using a signal. SOLUTION: At the rear of an address input A0 to an address input A2, pre-X-decoders, i.e., an address changeover circuit X9 to an address changeover circuit X12 which are composed of four-input AND-OR circuits and a memory- operating-speed changeover signal (MSP) line 37 which controls the circuits are installed. When a signal which is input to the MSP line 37 via an MSP switch is set at a high level, two each of word lines 1, 2 to 7, 8 are set to the high level by an address input A0 and an address input A1, and two out of the memory transistors 1, 2 to 7, 8 are selected simultaneously. Thereby, the number of memory transistors 32 which constitutes one memory cell can be set at two, and the operation of a memory circuit can be enhanced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory circuit incorporated in a semiconductor integrated circuit (hereinafter referred to as an LSI) such as a microcomputer.

[0002]

2. Description of the Related Art A microcomputer LSI has a CPU, a memory circuit, and a plurality of logic modules mounted on one chip.

The operation is performed by the CPU based on the data stored in the memory circuit, and the result is used to control other circuits outside the microcomputer through peripheral circuits.

On the other hand, with respect to the application of the microcomputer LSI, demand for various applications such as a notebook type personal computer and a cellular phone is increasing, and a reduction in current consumption and a change in an operation speed according to the application, particularly a high speed are required.

Therefore, it is very effective that the operation speed of each module mounted on the microcomputer LSI can be varied.

Various means for increasing the speed of LSI have been proposed. For example, JP-A-5-266670 discloses that
There is disclosed a semiconductor memory device configured to simultaneously select and drive two mutually adjacent word lines, and reduce the line resistance of the word lines to increase the speed.

Japanese Patent Application Laid-Open No. 3-105797 discloses a method of supplying a current supplied between decoding transistors in order to prevent a malfunction of a decoder circuit due to a parasitic capacitance without increasing access time and power consumption. There is disclosed a decoder circuit which is also charged from a circuit.

[0008] By the way, among the microcomputer LSIs, a memory circuit such as a ROM for writing a device control program of a customer and a RAM for temporarily storing a calculation result or storing information on the state of a device to be controlled are conventionally known. However, once the memory circuit is built on the microcomputer LSI, if the operating speed of the memory circuit on the microcomputer LSI is limited even if the operating speed of the device is to be improved, the speed of the device cannot be increased. there were. This point will be described with reference to a configuration diagram of a memory circuit.

FIG. 10 shows a configuration diagram of a conventional memory circuit. A memory circuit that stores information of 8 bits of the memory transistors 1 to 8 will be briefly described.

As a circuit configuration, address inputs A0 to A2 (3
0), word lines 1 to 8 (3
X decoder (33) which sets only one memory transistor (32) to a selected state by setting only one word line in 1) to high level, memory transistors 1 to 8 (32) for storing information, memory A data line (34) for extracting information from the transistor, a precharge transistor (35) for once raising the data line to the power supply voltage VD before reading from the memory transistor, a precharge signal PREN for controlling the same, and a potential change of the data line Amplifier that amplifies the data and outputs data to the outside of the memory circuit (3
6).

Further, since a plurality of memory transistors (32) are connected to the data line (34), a parasitic capacitance CD consisting of a wiring capacitance on the semiconductor chip and a diffusion capacitance on the drain side of the memory transistor is added.

Next, the reading operation of the memory circuit shown in FIG. 10 will be described. When the memory transistor 1 is selected, addresses A0, A1, and A2 are all connected to the ground voltage (hereinafter referred to as Lo).
w level). Thereby, word line 1
Becomes the power supply potential (hereinafter referred to as High level). The other word lines 2 to 8 are at the low level.
By setting the precharge signal PREN to Low level,
The precharge transistor becomes conductive. As a result, the data line goes high. At this time, the parasitic capacitance CD of the data line is also charged to the high level. At this time, assuming that the charge stored in the parasitic capacitance CD is Q, Q is represented by the following based on the parasitic capacitance CD and the power supply voltage VD.

Q = CD × VD (1) After the data line reaches the power supply voltage VD, the precharge signal PR
EN is returned to the high level, and the precharge transistor is turned off. When the precharge transistor is turned off, the data line capacitance CD is selected by the memory transistor 1 which is selected by the address signals A0 to A2 and is turned on.
Discharge begins.

The time required from the start of discharge to the output of data from the sense amplifier depends on the current drive capability of one memory transistor. Assuming that the current drive capability of one memory transistor is I, the time T2 from the end of precharge to the output of the sense amplifier data is shown below. However, the threshold voltage of the sense amplifier for data output is VD × 0.5.

T2 = VD × 0.5 × CD / I = VD × CD / (I × 2) Equation (2) The delay time T2 up to the data output is represented by an address input A0 to
Even if A2 is changed and a different memory transistor is selected,
Since the current drive capability of the memory transistor is constant, the operating speed of the memory circuit cannot be varied or increased.

Therefore, it has not been possible to meet the need to operate applications having different operation speeds on the same microcomputer LSI or memory circuit.

[0017]

As described above, in the conventional memory circuit, since the current drive capability of the selected memory transistor is constant, the operating speed of the memory circuit can be varied using the same memory circuit on the LSI. Or couldn't be faster.

Further, it has not been possible to meet the need to operate applications having different operation speeds on the same microcomputer LSI or memory circuit.

An object of the present invention is to provide a memory circuit on an LSI, which can change the operation speed.

It is another object of the present invention to provide a microcomputer capable of operating applications having different operation speeds and a control method thereof.

[0021]

A feature of the present invention to achieve the above object is a memory circuit mounted on a semiconductor integrated circuit, wherein each of the memory circuits includes a plurality of memory transistors. Wherein the number of memory transistors constituting each of the memory cells is variable, and an external switch for switching the number of memory transistors to one or more by a signal is provided.

Another feature of the present invention is a memory circuit having a plurality of memory cells and mounted on a semiconductor integrated circuit,
An address input unit, a plurality of memory transistors forming the memory cell, an X decoder for selecting one of the memory transistors via a specific word line according to an input address, and the selected memory transistor An address switching circuit provided between the address input unit and the X decoder, and an MSP line for providing a signal for controlling the address switching circuit. A memory operation switching signal for simultaneously selecting one or a plurality of the memory transistors is input to the MSP line via an MSP switch provided outside the memory circuit.

Another feature of the present invention resides in a microcomputer equipped with the memory circuit.

Another feature of the present invention is a microcomputer provided with a memory circuit, wherein the memory circuit has a plurality of memory cells each constituted by a memory transistor, and is provided outside the memory circuit. And controlling the microcomputer to change the operation speed of the memory circuit by switching the number of memory transistors to be selected simultaneously to one or more via a switch.

According to the present invention, in a memory circuit mounted on a microcomputer LSI, the number of memory transistors constituting one memory cell is made variable, and one, two or more memory transistors are selected at the same time. By simultaneously selecting a plurality of the above, the operating speed of the memory circuit can be varied or increased by apparently increasing the current driving capability of the memory transistor.

[0026]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, specific embodiments of the present invention will be described. FIG. 1 shows an embodiment of a microcomputer LSI having a memory circuit using the present invention. FIG. 2 is a diagram showing a detailed configuration example of a memory circuit of the microcomputer LSI of FIG.

In FIG. 1, a microcomputer LSI 1 has a CPU 2, a memory circuit 3, and a plurality of logic modules 4 mounted on one chip. 6 is for inputting the operating speed switching signal MSP from outside the microcomputer LSI,
MSP switch.

Based on the data stored in the memory circuit 3, C
The operation is performed by the PU 2, and the result is used to control other circuits outside the microcomputer LSI through the peripheral circuit 5. In addition, the number of memory transistors constituting one memory cell of the memory circuit 3 inside the microcomputer LSI can be switched by an external signal input via the MSP switch 6.

As shown in FIG. 2, the memory circuit 3 includes word lines 1 to 8 (31), memory transistors 1 to 8 (32) made of NMOS, a precharge transistor (35) made of PMOS, and three inputs. An X decoder (33) composed of NANDs X1 to X8, a data line (34), a precharge transistor (35) and a precharge signal PREN for controlling the same,
And a sense amplifier (36). After the address inputs A0, A1, A2 (30), a 4-input AND
A pre-X decoder (38) comprising an OR circuit, that is, address switching circuits X9, X10, X11, X12 and a memory operation switching signal MSP line (3
7) is provided.

When the signal input to the MSP line (37) via the MSP switch 6 is set to the high level, the word lines (31) which are set to the high level by the address input of A0 and A1 are changed to the word lines 1 and 2 , The word lines 3 and 4, the word lines 5 and 6, and the word lines 7 and 8 attain a high level. As a result, any two memory transistors 1 and 2, or 3 and 4, 5 and 6, or 7 and 8 of the memory transistors (32) are simultaneously selected. However, since two memory transistors (32) are simultaneously selected, the memory capacity is as shown in FIG.
In the conventional example shown in FIG.

Conversely, when the signal input to the MSP line (37) is at the low level, the memory transistor (3) selected by the address input of A0, A1, and A2
2) is that only one of the word lines 1 to 8 is Hig
Since the level becomes the h level, any one of the memory transistors 1 to 8 is selected. In this case, the memory capacity is 8 bits equivalent to the conventional circuit shown in FIG.

FIG. 3 shows an MSP from outside the microcomputer LSI.
A memory operation switching signal MSP is set to Hi at line (37).
gh level, and shows a state in which the number of memory transistors constituting one memory cell of the memory circuit inside the microcomputer LSI is switched. FIG. 4 shows the state of the memory circuit at this time.

In FIG. 3, the operating speed switching signal MSP
By inputting “High”, two memory transistors can be included in one memory cell, so that the operation speed of the memory circuit is reduced to, for example, 13 Mh.
z can be improved. However, the storage capacity of the memory circuit is 64 KB.

In FIG. 4, by setting MSP to High level, X9 and X1 of the pre-X decoder (38) are
The output of 0 is Low and High regardless of the input address. As a result, the word lines 1 and 2, the word lines 3 and 4, the word lines 5 and 6, and the word lines 7 and 8 each become High level by the address input of A0 and A1. Thereby, any one of the memory transistors 1 and 2 or 3 and 4 or 5 and 6 or 7 and 8
The memory transistors are simultaneously selected. That is,
When a unit for storing 1-bit information is a memory cell, M
By setting SP to High level, memory cell 1
The memory circuit has a capacity of 4 bits from 4 to 4. Since one memory cell is composed of two memory transistors, the operation speed of the memory circuit can be improved.

Next, the improvement of the operation speed will be described with reference to the circuit diagram of FIG. 4 and the operation timing diagram of FIG.

First, a case where the memory operation speed switching signal MSP is at a high level and all the addresses A0 to A2 are at a low level will be described. When MSP is set to the high level, the word lines 1 and 2 are simultaneously set to the high level by the pre-X decoder and the X decoder, and the selected memory transistors are the two memory transistors 1 and 2 in FIG. That is, the memory cell 1 is selected. As shown in FIG. 4, similar to the conventional circuit of FIG.
The data line is charged to VD. Therefore, the electric charge of VD × CD is accumulated in the data line parasitic capacitance CD as in the conventional circuit.

Here, the time T1 from the end of precharge to the output of sense amplifier data when two memory transistors are selected simultaneously is determined. As shown in FIG. 5, the threshold voltage of the sense amplifier for data output is VD × 0.5 as in the conventional circuit. However, the current drivability that contributes to the discharge of the memory transistor is I × 2 for two memory transistors of the conventional circuit because two memory transistors are simultaneously selected as shown in FIG. Therefore T1
Is represented below.

T1 = VD × 0.5 × CD / (I × 2) = VD × CD / (I × 4) Equation (3) Therefore, the time until data output in the conventional circuit shown in FIG. The relationship with T2 is as follows from the above equations (2) and (3).

T1 = T2 / 2 Equation (4) This is equivalent to the time T2 until data output in the conventional circuit.
This shows that the time T1 from the end of precharge of the memory circuit to the data output in the present invention can be reduced to half.

Thus, according to the present invention, the number of memory transistors constituting one memory cell can be switched by the operating speed switching signal MSP in the same memory circuit. Higher speed can be realized.

Also, Lo is applied to the operation speed switching signal MSP.
The operation of FIG. 6 in which the w level is input will be described with reference to FIG.

First, as shown in FIG. 3, when the operating speed switching signal MSP is "High", 64 KB
And the operating frequency is 13 MHz. When it is necessary to reduce the memory operation speed depending on the use of the microcomputer LSI, a low level is input to the operation speed switching signal MSP as shown in FIG. Thus, the upper limit of the operating frequency of the memory circuit is set to 10 MHz, and the memory circuit has a memory capacity of 128 KB.

As shown in FIG. 7, the operation speed switching signal M
By inputting the Low level to the SP, the outputs of the address switching circuits X9, X10, X11 and X12 are A
It is determined by the address input of 0, A1, and A2. At this time, the selected memory transistor is any one of the memory transistors 1 to 8. A0, A1, A2
The case where all are input Low will be described. In this case, only the word line 1 becomes High level, so that only the memory transistor 1 is selected. At this time, the discharge current is I for one memory transistor, and has the same value as that of the conventional circuit shown in FIG.

Therefore, as shown in the operation timing chart of FIG. 8, the time from when the precharge signal PREN goes high to when data is output is T2, and the operation speed of the memory circuit is as shown in FIG. It becomes the same as the conventional circuit. In this case, the memory capacity is 8 which is the same as the conventional circuit.
It becomes a bit memory circuit.

As described above, by making the number of memory transistors constituting a memory cell switchable,
It is possible to select the operation speed of the memory circuit according to the application.

In the embodiment shown in FIG. 2, the number of memory transistors constituting one memory cell is switched by one or two. However, the number of memory transistors can be simultaneously selected by changing the combination or system of the X decoder and the pre-X decoder. The number of memory transistors that can be obtained can be further increased than two. Also, by using a plurality of memory operation speed switching signals, a plurality of memory operation speeds can be selected.

FIG. 9 shows another embodiment of the present invention in which one memory transistor is constituted by a static memory transistor. As in the embodiment of FIG. 4, by inputting a High level to the memory operation speed switching signal MSP, one memory cell can be constituted by two memory transistors. Therefore, FIG.
As described above, the operation speed is set to the low
It is improved as compared with the case of input. As described above, according to the present invention, even when the types of the memory transistors are different, the number of memory transistors constituting one memory cell can be switched.

[0048]

According to the present invention, the number of memory transistors constituting one memory cell of a memory circuit mounted on a microcomputer LSI can be switched by an external signal, and the operation speed of the memory circuit can be switched. it can.
Thus, the same memory circuit and the same microcomputer LSI can cope with applications having different operation speeds.

[Brief description of the drawings]

FIG. 1 is a diagram showing a schematic configuration of a microcomputer LSI according to one embodiment of the present invention.

FIG. 2 is a configuration diagram of a memory circuit in the embodiment of FIG. 1;

FIG. 3 is a diagram showing a configuration of a microcomputer LSI when one memory cell of a memory circuit is configured by a plurality of memory transistors in the embodiment of the present invention.

FIG. 4 is a diagram showing a configuration of a memory circuit and input signals when one memory cell is formed by a plurality of memory transistors, corresponding to the state of FIG. 3;

FIG. 5 is a diagram showing operation timings of the memory circuit of FIG. 4;

FIG. 6 shows a configuration of a microcomputer LSI when one memory cell of a memory circuit is formed by one memory transistor in the embodiment of the present invention.

FIG. 7 is a diagram showing a configuration and input signals of a memory circuit according to the embodiment of FIG. 6;

FIG. 8 is a diagram showing operation timings of the memory circuit of FIG. 7;

FIG. 9 is a memory circuit diagram in the case where a memory transistor is constituted by a static memory transistor as another embodiment of the present invention.

FIG. 10 is a circuit diagram showing a conventional memory circuit.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Microcomputer LSI, 2 ... CPU, 3 ... Memory circuit, 4 ... Logic module, 6 ... MSP, 30 ... Address input, 3
1: Word lines 1 to 8, 32: Memory transistors 1
8, 33 X decoder, 34 data line, 35 precharge transistor, 36 sense amplifier, 37 MS
P line, 38 ... Pre-X decoder data line

Claims (5)

[Claims] 1. A memory circuit mounted on a semiconductor integrated circuit, wherein the memory circuit has a plurality of memory cells each constituted by a memory transistor, and the number of memory transistors constituting each memory cell is reduced. A memory circuit comprising an external switch which is variable and switches the number of said memory transistors to one or a plurality according to a signal. 2. A memory circuit having a plurality of memory cells and mounted on a semiconductor integrated circuit, comprising: an address input unit; a plurality of memory transistors forming the memory cells;
An X decoder for selecting one of the memory transistors via a specific word line in accordance with an input address, and a data line for extracting information from the selected memory transistor; And an MSP line for providing a signal for controlling the address switching circuit. The MSP line is provided through an MSP switch provided outside the memory circuit.
A memory circuit, wherein a memory operation switching signal for selecting one or a plurality of memory transistors at the same time is input to a P line. 3. A microcomputer comprising the memory circuit according to claim 1 or 2. 4. A memory circuit, comprising the memory circuit according to claim 1 and a microcomputer LSI having the memory circuit.
A microcomputer characterized in that the operating speed of the microcomputer is variable, and the same memory circuit can be used for applications having different operating speeds. 5. A microcomputer equipped with a memory circuit, wherein the memory circuit has a plurality of memory cells each constituted by a memory transistor, and simultaneously connected via a switch provided outside the memory circuit. A control method for a microcomputer, wherein the number of the memory transistors to be selected is switched to one or more, and an operation speed of the memory circuit is changed.