JP2000076224A - Vector operation method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the number of coping times between a memory and registers and the number of execution times of a vector operation instruction and to improve a processing speed by collectively copying arrays in the same set into a vector register and processing them with the same vector operation instruction. SOLUTION: When an addition expression in which the sum of elements with each other of arrays E and F is made and element for an array D is described while following an addition expression in which the sum of elements with each other of arrays B and C is made an element for an array A, respective elements of the arrays B and E are copied into a vector register B (Vb) from a continuous area on a memory (S1). Respective elements of the arrays C and F are copied into a vector register C (Vc) from the continuous area of the memory (C2). A vector operation instruction Va=Vb+Vc is carried out (S3). Each element of a vector register A (Va) is copied into the continuous area of the memory (S4). Thus, processing needing eight steps in the conventional practice comes to need only four steps.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for performing an operation on an array by a vector operation on a computer having a vector operation function, and more particularly to a vector operation method for simultaneously executing a plurality of vector operations of the same type.

[0002]

2. Description of the Related Art A computer having a vector operation function includes several vector registers and a vector operation unit for each operation type such as addition and multiplication. Can be executed at high speed.

For example, A (:) = B (:) + C (:) (1) (where the range of elements of arrays A, B, and C is 1 to n). If used, it can be executed in the following four steps. 1. Each element of the array B is copied from the memory to the vector register B (Vb). 2. Each element of the array C is copied from the memory to the vector register C (Vc). 3. Execute the vector operation instruction Va = Vb + Vc. 4. Each element of the vector register A (Va) is copied to the array A on the memory.

Here, in each of the steps 1, 2, and 4, a copy instruction for collectively copying between the n array elements and the vector register which are continuously arranged on the memory is used. .

[0005] In the field of scientific and technological calculations, vector operations having the same number of arrays and the same type of operation may be continuously executed. Also in this case, conventionally, the same procedure as in the case of the equation (1) has been repeated for each operation.
Below are some examples where the same kind of vector operation is continuous,
A conventional calculation method in that case will be described.

Example 1 A (:) = B (:) + C (:) (2-1) D (:) = E (:) + F (:) (2-2) (However, arrays A and B , C has a range of 1 to n. The range of the elements of arrays D, E, and F has a range of 1 to m. -1) followed by sequence E and sequence F
The addition formula (2-
This is an example of executing 2).

FIG. 7 shows arrays A to F allocated on the memory at the time of execution. Each of the arrays A to F is allocated to continuous areas E1 to E6 on the memory as shown in FIG.

FIG. 8 shows the above two equations (2-1) and (2)
2 is a flowchart showing a conventional procedure in the case of executing (-2) using a vector operation, and includes the following steps. Step S21: Copy each element of the array B from the memory to the vector register B (Vb). Step S22: Each element of the array C is copied from the memory to the vector register C (Vc). Step S23: Execute the vector operation instruction Va = Vb + Vc. Step S24: Each element of the vector register A (Va) is copied to the array A on the memory. Step S25: Copy each element of the array E from the memory to the vector register B (Vb). Step S26: Copy each element of the array F from the memory to the vector register C (Vc). Step S27: Execute the vector operation instruction Va = Vb + Vc. Step S28: Each element of the vector register A (Va) is copied to the array D on the memory.

[0009] Example _{2 DO I = 1,1 1, 1} 2 A (:, I) = B (:, I) + C (:, I) ... (3-1) D (:, I) = E (: , I) + F (:, I) ENDDO (However, the range of the first dimension of the two-dimensional arrays A, B, and C is 1 to n, and the range of the second dimension is 1 to 1 ₁ , the range of the first dimension subscript of the two-dimensional arrays D, E, and F is 1 to m, and the range of the second dimension subscript is 1 to ₁₁ , and 1 ₁ ≧ 1 ₂ ≧ 1. loop, subscripts second dimension of the array C and array B is _{1,1 + 1 2, 1 + 2} × 1 2, ... become the second dimension of the subscripts a sum of the elements to each other sequence C is _{1,1 + 1 2, 1 + 2} × 1
_2, a calculation formula to ... become elements (3-1), the second dimension of the array subscript F and SEQ E is _{1,1 + 1 2, 1 + 2} ×
1 _2, ... second dimension subscripts a sum of the elements to each other sequence D is 1, 1 + 1 _2, 1 + 2 × 1 _2, are examples for performing the calculation formula (3-2) to ... become elements .

FIG. 9 shows arrays A to F allocated on the memory at the time of execution. Each of the arrays A to F is allocated to continuous areas E1 to E6 on the memory as shown in FIG.

FIG. 10 is a flowchart showing a conventional procedure for executing the DO loop by using a vector operation, and comprises the following steps. Step S31: 1 is substituted into the loop control variable I. Step S32; I> ₁ 1 if the process ends, the process branches to step S33 if not. Step S33: Each element B (1, I) to B of array B
(N, I) is stored in the vector register B (Vb) from the memory.
Copy to Step S34: Each element C (1, I) to C of array C
(N, I) is stored in a vector register C (Vc) from the memory.
Copy to Step S35: Execute the vector operation instruction Va = Vb + Vc. Step S36: The contents of the vector register A (Va) are stored in the elements A (1, I) to A (n, I) of the array A on the memory.
Copy to Step S37: Each element E (1, I) to E of the array E
(M, I) is stored in the vector register B (Vb) from the memory.
Copy to Step S38: Each element F (1, I) to F of the array F
(M, I) is stored in a vector register C (Vc) from the memory.
Copy to Step S39: Execute the vector operation instruction Va = Vb + Vc. Step S3A: The contents of the vector register A (Va) are stored in the elements D (1, I) to D (m, I) of the array D on the memory.
Copy to Step S3B; 1 ₂ is added to the I, the flow returns to step S32.

A computer having a vector operation function is described in, for example, "New Edition Information Processing Handbook".
(Ohm Co., Ltd., issued on November 25, 1995), there is a detailed explanation in "Vector Calculator" in Chapter 3, Chapter 6.

[0013]

As described above, when a plurality of calculation formulas having the same number of arrays and the same kind of calculation are executed by using a vector calculation, conventionally, an array on a memory is used for each calculation formula. The process of copying to the vector register, the process of executing the vector operation instruction, and the process of copying the contents of the vector register to the memory are repeated. Therefore, particularly in the case of an operation on an array having a small number of elements, the time required to copy the array in memory to the vector register before executing the vector operation instruction and the value obtained by the vector operation instruction The time required to copy data from a register to an array in memory is relatively large compared to the time required for the vector operation instruction itself, and there has been a problem that the high speed of vector operation cannot be fully utilized. .

Accordingly, an object of the present invention is to provide a method for executing a plurality of formulas having the same number of arrays and the same type of operation by using a vector operation. An object of the present invention is to reduce the number of executions and improve the processing speed.

[0015]

According to the present invention, there are provided a plurality of calculation formulas which can be calculated independently of each other, wherein all the arrays included in each calculation formula are one-dimensional arrays, and the number and type of operation are the same. There are a plurality of formulas in which the sum of the number of elements of the arrays that appear on the left side of the plurality of formulas and the number of elements of the arrays that appear at the same position (the same term) on the right side is smaller than the size of the vector register held by the computer, A DO loop including a plurality of calculation formulas that can be calculated in a loop, wherein the arrays included in each calculation formula are all multidimensional arrays having the same number of dimensions, the number of which is the same, and the type of operation is the same. The sum of the number of elements per iteration of the loop between the arrays that appear on the left side of the calculation formula and the array that appears at the same position on the right side is less than the size of the vector register held by the computer. When a plurality of calculation formulas in the map are executed by using a vector operation, they can be processed collectively by one set of vector registers, and array elements in the calculation formulas that can be processed by the same vector register are successively stored on the memory. By arranging them in such a manner, they can be copied to a vector register all at once by a single copy instruction, and conversely, copied to a memory. A first step of allocating the arrays that appear on the left side and the arrays that appear at the same position on the right side to each other, and allocating the same set of arrays to a continuous area on the memory; One input vector register is assigned to each set of appearing arrays, and each set of arrays is read from a contiguous area on the memory. A second step of copying in accordance with a copy instruction, and an operation on the array copied in the input vector register is executed by a vector operation unit corresponding to the type of operation of the calculation expression, and the operation result is output to a vector for output. And storing the data in a register.

The operation result stored in the output vector register is copied by a copy instruction to a continuous area on the memory allocated to a set of arrays appearing on the left side of the plurality of formulas. It is characterized by including four steps.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an example of a computer for implementing the vector operation method of the present invention. The computer of this example includes a CPU 1 and a memory (main memory) 2
, A loader 3, storage devices 4 and 5, and a compiler 6.

The CPU 1 has a C having a vector operation function.
It is a PU, and includes a vector register set 11, a vector adder 12, a vector multiplier 13, a data transfer unit 14, and an instruction interpreting unit 15.

The vector register set 11 includes a plurality of vector registers A (Va), B (Vb), C (Vc),
... The size (vector length) of each vector register is L.

The vector adder 12 adds data supplied from any two vector registers in the vector register set 11, and stores the addition result in another vector register in the vector register set 11. And the vector multiplier 13 multiplies the data supplied from any two vector registers in the vector register set 11 and stores the multiplication result in another vector register in the vector register set 11. , Respectively.

The data transfer unit 14 responds to a copy command
Data existing in a continuous area on the memory 2 is copied to an arbitrary vector register in the vector register set 11, and conversely, contents stored in an arbitrary vector register are copied to a continuous area on the memory 2. It is a means to do.

The instruction interpreter 15 fetches and decodes instruction codes, such as a vector operation instruction and a copy instruction, from the memory 2, and decodes the fetched instruction code.
1, means for controlling the vector adder 12 and the vector multiplier 13.

Although the CPU 1 has a scalar operation function in addition to the vector operation function, it is not shown because it is not directly related to the operation of the present invention.

The memory 2 includes an instruction code section 21 for storing an instruction code and a data section 2 for storing data such as an array.
And 2. The instruction code section 21 stores an instruction code string 211 optimized according to the present invention, and the data section 22 stores a data string 2 optimally arranged according to the present invention.
21 is stored.

The storage device 5 is a file on the magnetic disk device, and stores a source program 51 describing a plurality of arithmetic expressions for an array.

The compiler 6 inputs the source program 51 from the storage device 5 and performs syntax analysis, semantic analysis, code generation, and the like to generate an object program 41. At this time, when the calculation formulas for the array appear continuously in the source program 51, it is determined whether or not the plurality of calculation formulas can be optimized according to the present invention. A program 41 is generated.

The conditions under which a plurality of formulas can be optimized according to the present invention are as follows. (1) Each formula can be calculated independently. In other words, there must be no dependencies, such as quoting the array defined in the preceding calculation formula in the subsequent calculation formula. (2) The number of arrays included in all the formulas is equal and the same operation is used. (3) When the arrays included in each calculation expression are all one-dimensional arrays, the sum of the numbers of elements of the arrays appearing on the left side of each calculation expression and the arrays appearing at the same position on the right side is equal to or smaller than the size of the vector register. thing. (4) When the arrays included in each calculation formula are all multidimensional arrays having the same number of dimensions and the calculation formulas are included in the same DO loop, the arrays appearing on the left side of each calculation formula and the same position on the right side The sum of the number of elements per iteration of the loop between arrays appearing in the above is equal to or smaller than the size of the vector register.

The compiler 6 performs the following optimization for a plurality of calculation expressions satisfying the above conditions.

First, as a data allocating method, arrays which appear on the left side and arrays which appear at the same position on the right side in a plurality of formulas are respectively set as a set, and the same set of arrays is allocated to a continuous area on the memory 2. Such a data allocation method is adopted.

Next, the following instruction codes are generated as instruction codes corresponding to a plurality of calculation formulas. (1) One input vector register is allocated to each set of arrays appearing at the same position on the right side of a plurality of calculation formulas, and the array of each set is allocated from a continuous area on the memory 2 to a corresponding input vector register. To generate an instruction code of a copy instruction to be copied to the. At this time, the length of the vector to be copied is equal to the total value of the number of elements of the array of the set. (2) The array copied to the input vector register is
A vector operation is performed by a vector operation unit corresponding to the type of operation, and an instruction code of a vector operation instruction for storing the operation result in an output vector register is generated. On this occasion,
The vector length required for the operation is equal to the size of the array copied to the input vector register, that is, the total value of the number of elements of the array appearing at the same position on the right side of a plurality of formulas. (3) Generating an instruction code of a copy instruction for copying the operation result stored in the output vector register to a continuous area on the memory 2 allocated to a set of arrays appearing on the left side of the plurality of formulas I do.

Next, the storage device 4 in FIG. 1 is a file on a magnetic disk device for storing the object program 41 generated by the compiler 6, and the loader 3
This is a means for loading the object program 41 into the memory 2. The instruction code sequence in the object program 41 is loaded into the instruction code unit 21 as an instruction code sequence 211, and data such as an array is loaded into the data unit 22 as a data sequence 221. When loading the array into the data section 22, the data allocation method determined by the compiler 6 is followed.

The instruction code sequence 211 of the object program 41 loaded into the instruction code unit 21 of the memory 2 as described above is sequentially interpreted and executed by the instruction interpreting unit 15 of the CPU 1.

Next, an example of this embodiment will be described.

Now, in the source program 51, following the addition formula (4-1) in which the sum of the elements of the arrays B and C is used as the element of the array A, The addition formula (4-
Assume that 2) is described. This equation is the same as the equations (2-1) and (2-2) described in the prior art. A (:) = B (:) + C (:) (4-1) D (:) = E (:) + F (:) (4-2) However, the range of the elements of the arrays A, B, and C Are 1 to n, array D,
The range of the elements of E and F is 1 to m, and n + m is not more than the size L of the vector register in the vector register set 11.

When the compiler 6 detects a position in the source program 51 where arithmetic expressions for an array are continuous, it determines whether or not these arithmetic expressions can be optimized by the present invention. In this case, equations (4-1) and (4-
It can be calculated independently of 2), the number of arrays included in both equations is equal to three, and the same operation of addition is used. Arrays A and D appearing on the left side of each expression
Arrays B and E, C and F appearing at the same position on the right side
The sum of the numbers of elements is n + m, which is equal to or smaller than the size L of the vector register. Therefore, the compiler 6 determines that the equations (4-1) and (4-2) can be optimized according to the present invention, and performs the following optimization.

First, as a data allocation method, equation (4)
-1) and (4-2), the arrays A and D appearing on the left side and the arrays B and E appearing at the same position on the right side, and C and F constitute a set, and as shown in FIG. A data allocation method is adopted in which the array is allocated to continuous areas E1, E2, and E3 on the memory 2.

Next, the following instruction codes are generated as instruction codes corresponding to the expressions (4-1) and (4-2). One input vector register (referred to as B (Vb)) is assigned to a set of arrays B and E appearing in the first term on the right side of the equation (1), and the arrays B and E of the set are stored in the memory 2. An instruction code of a copy instruction to be copied to the vector register B (Vb) from the continuous area E2 shown in FIG. 2 is generated. (2) Similarly, one vector register (referred to as C (Vc)) for input is assigned to a set of arrays C and F appearing in the second term on the right side of the equation, and the arrays C and F of the set are stored in the memory 2 From the continuous area E3 shown in FIG.
An instruction code of a copy instruction to be copied to (Vc) is generated. (3) Generate a vector addition instruction Va = Vb + Vc.
As shown in FIG. 3, the vector addition instruction includes an element of the vector register B (Vb) and a vector register C (V
This is an instruction for obtaining an addition value with the element of c) by the vector adder 12, and storing the result in an output vector register A (Va). (4) The operation result stored in the vector register A (Va) is stored in an array A that appears on the left side of the equations (4-1) and (4-2).
2 and D are generated, and an instruction code of a copy instruction to be copied to the continuous area E1 shown in FIG.

FIG. 4 shows the equation (4) generated as described above.
Instruction code strings corresponding to -1) and (4-2) are shown in a flowchart format.

An object program 4 including an instruction code string as shown in FIG.
1 is stored in the storage device 4, and thereafter the instruction code sequence 211 is stored in the instruction code unit 21 of the memory 2 by the loader 3.
And a data string 221 such as an array is
Is loaded. At this time, Expressions (4-1) and (4-2)
As shown in FIG. 2, the array defined and referred to is allocated to continuous areas E1 to E3 of the memory 2 for each set of predetermined arrays. Then, the instruction interpreting unit 15 of the CPU 1 sequentially reads and interprets the instruction code from the instruction code sequence 211 and controls each unit. Thus, when the execution proceeds to the instruction code string shown in FIG. 4, the following operation is performed.

Step S1: Under the control of the instruction interpreting unit 15, the data transfer unit 14 stores the elements of the array B and the array E from the continuous area E2 on the memory 2 into the vector register B (V
Copy to b). Step S2: Under the control of the instruction interpreting section 15, the data transfer section 14 copies each element of the arrays C and F from the continuous area E3 on the memory 2 to the vector register C (Vc). Step S3: Under the control of the instruction interpreting section 15, the vector adder 12 executes the vector operation instruction Va = Vb + Vc. That is, an addition value for each element of the vector register B (Vb) and the vector register C (Vc) is obtained,
The data is stored in the vector register A (Va). Step S4: Under the control of the instruction interpretation unit 15, the data transfer unit 14 stores each element of the vector register A (Va)
Copies to the continuous area E1 on the memory 2.

As described above, the processing which conventionally required eight steps as shown in FIG. 8 can be completed in this embodiment with four steps as shown in FIG.

In the above embodiment, the number of terms on the right side of the operation is 2
And the left-hand side is not the same as any array of terms on the right-hand side,
In addition, although the description has been given of a plurality of calculation formulas in which the calculation is addition, there is no limitation on the number of terms on the right side, the type of calculation, and the difference in terms. Applicable.

A (:) = − A (:) B (:) = − B (:) (5) A (:) = B (:) − C (:) * D (:) E (:) = F (:)-G (:) * H (:) (6) A (:) = sinB (:) + cosC (:) D (:) = sinE (:) + cosF (:) (7)

In the above example, the operation for a one-dimensional array has been described, but the present invention is also applicable to an operation for an array having two or more dimensions. An example is shown below.

DO I = 1, 1 ₁ , 1 ₂ (8-1) A (:, I) = B (:, I) + C (:, I) (8-2) D (:, I) = E (:, I) + F (:, I) (8-3) ENDDO (8-4) However, the range of subscripts in the first dimension of the two-dimensional arrays A, B, and C is 1 to n, The range of the subscript of the dimension is 1 to 11 ₁ , the range of the subscript of the first dimension of the two-dimensional arrays D, E, and F is 1 to m, the range of the subscript of the second dimension is 1 to ₁₁ and 1 ₁ ≧ 1 ₂ ≧ 1 and n + m is equal to or smaller than the size L of the vector register in the vector register set 11.

The calculation formula by the above DO loop is as follows:
And the second dimension of the array C are 1,1 + 1 ₂ , 1 + 2 × 1
_2, ... Element by element second dimension subscripts 1,1 + 1 ₂ of the sum sequence C of, 1 + 2 × 1 _2, and ... become elements, the second dimension of the array subscript F and SEQ E is 1,1 + 1 ₂ , 1 + 2
The sum of the elements of × 1 ₂ ,... Is defined as the element whose second dimensional subscript of the array D is 1,1 + 1 ₂ , 1 + 2 × 1 ₂ ,. 1), (3-
Same as 2).

The above formula is used in the source program 5
If they are present in 1, the compiler 6 determines whether or not these formulas can be optimized according to the present invention. In this case, the equations (8-2) and (8-3) in the DO loop can be calculated independently, the number of arrays included in both equations is equal to three, and the addition is called addition. The same operation is used. The sum of the number of elements per iteration of the loop between the arrays A and D appearing on the left side of each expression and the arrays B and E appearing at the same position on the right side and between the arrays C and F is n +
m, which is smaller than or equal to the size L of the vector register. For this reason, the compiler 6 calculates the expression (8-
2) and (8-3) determine that the optimization according to the present invention is possible, and perform the following optimization.

First, as a data allocation method, equation (8)
2), arrays A and D appearing on the left side of (8-3) and arrays B, E, C and F appearing at the same position on the right side are respectively grouped and assigned to a continuous area on the memory 2. Adopt a simple data allocation method. At this time, since the equations (8-2) and (8-3) exist in the DO loop, in each continuous area, the same subscripts corresponding to the loop control variables I are allocated so as to be continuous. That is, as shown in FIG. 5, for the arrays A and D, the subscript of the second dimension corresponding to the loop control variable I is 1 (A (1,
1),..., A (n, 1) and D (1, 1),.
1) is continuously allocated to the continuous area E1 on the memory 2,
Next thing subscript 2, a three, ..., allocated likewise continuously from 1 ₁ in a continuous area E1 in the memory 2. Similarly, arrays B and E and arrays C and F are allocated to continuous areas E2 and E3 on the memory 2 as shown in FIG.

Next, the following instruction code is generated as an instruction code corresponding to the DO loop.

First, the control statement (8-1) of the DO loop,
Corresponds to (8-4), the instruction code initializes the loop control variable I, instruction code processing branches by comparing the controlled variable I closing 1 ₁ and the loop control variable for each run one loop I the generates an instruction code for adding increment value 1 _2.

Next, the following instruction codes are generated as instruction codes corresponding to the equations (8-2) and (8-3). One set of input vector registers (referred to as B (Vb)) is assigned to the set of arrays B and E appearing in the first term on the right side of the equation (1), and the current loop control variable I of the arrays B and E of the set is assigned. Is generated from the continuous area E2 shown in FIG. 5 in the memory 2 into the vector register B (Vb). (2) Similarly, one vector register for input (C (Vc)) is assigned to a set of arrays C and F appearing in the second term on the right side of the equation, and the current loop of arrays C and F of the set is assigned. An instruction code of a copy instruction for copying each element corresponding to the value of the control variable I from the continuous area E3 shown in FIG. 5 on the memory 2 to the vector register C (Vc) is generated. (3) Generate a vector addition instruction Va = Vb + Vc.
As shown in FIG. 3, the vector addition instruction includes the elements of the vector register B (Vb) and the vector register C (V
This is an instruction for obtaining an addition value with the element of c) by the vector adder 12, and storing the result in an output vector register A (Va). (4) The operation result stored in the vector register A (Va) is converted into an array A appearing on the left side of the equations (8-2) and (8-3).
The instruction code of a copy instruction to be copied to a portion corresponding to the value of the current loop control variable I in the continuous area E1 shown in FIG.

FIG. 6 shows the above D generated as described above.
An instruction code string corresponding to the O loop is shown in a flowchart format.

An object program 4 including an instruction code sequence as shown in FIG.
1 is stored in the storage device 4, and thereafter the instruction code sequence 211 is stored in the instruction code unit 21 of the memory 2 by the loader 3.
And a data string 221 such as an array is
Is loaded. At this time, equations (8-2) and (8-3)
As shown in FIG. 5, the array defined and referred to is allocated to the continuous areas E1 to E3 of the memory 2 for each set of the predetermined array. Then, the instruction interpreting unit 15 of the CPU 1 sequentially reads and interprets the instruction code from the instruction code sequence 211 and controls each unit. Thus, when the execution proceeds to the position of the instruction code string shown in FIG. 6, the following operation is performed.

Step S11: The instruction interpreter 15 substitutes 1 for a loop control variable I. Step S12; instruction interpreting unit 15 branches to I> 1 ₁ if step S13, and terminates the process of FIG. 6 otherwise. Step S13: Under the control of the instruction interpreting unit 15, the data transfer unit 14 reads the elements B (1, I) to B (n, I) of the array B and the elements E of the array E from the continuous area E2 on the memory 2.
(1, I) to E (m, I) are stored in a vector register B (V
Copy to b). Step S14: Under the control of the instruction interpreting unit 15, the data transfer unit 14 reads the elements C (1, I) to C (n, I) of the array C and the element F of the array F from the continuous area E3 on the memory 2.
(1, I) to F (m, I) are stored in a vector register C (V
Copy to c). Step S15: Under the control of the instruction interpreting unit 15, the vector adder 12 executes the vector operation instruction Va = Vb + Vc. That is, an addition value for each element of the vector register B (Vb) and the vector register C (Vc) is obtained and stored in the vector register A (Va). Step S16: Under the control of the instruction interpreting section 15, the data transfer section 14 copies each element of the vector register A (Va) to the continuous area E1 on the memory 2. Step S17; instruction interpreting unit 15 adds 1 ₂ to the loop control variable I, the process proceeds to step S12.

As described above, the processing which conventionally required many steps as shown in FIG. 10 can be reduced to a small number of steps as shown in FIG. 6 in this embodiment.

[0057]

As described above, according to the present invention, it is possible to improve the processing speed when executing a plurality of formulas having the same number of arrays and the same type of operation by using the vector operation. The reason is that arrays that appear at the same position on the right side of multiple formulas are grouped and allocated to a continuous area in memory, and the arrays of the same group are collectively copied to the same vector register, and the same vector operation is performed. To process with instructions,
This is because the number of times of copying from the memory to the vector register and the number of times of executing the vector operation instruction are reduced. Also,
Arrays appearing on the left side of a plurality of formulas are grouped and assigned to a continuous area in the memory, and the operation results obtained in the vector register by the vector operation instruction are collectively copied to a continuous area in the memory. This is because the number of times of copying from the vector register to the memory is reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an example of a computer that executes a vector operation method according to the present invention.

FIG. 2 is a diagram showing a method of allocating arrays to memories in one embodiment of the present invention.

FIG. 3 is an explanatory diagram of a vector addition instruction Va = Vb + Vc.

FIG. 4 is a diagram showing, in a flowchart form, an optimized instruction code sequence in one embodiment of the present invention.

FIG. 5 is a diagram showing a method of allocating arrays to memories according to another embodiment of the present invention.

FIG. 6 is a diagram showing, in a flowchart form, an optimized instruction code sequence in another embodiment of the present invention.

FIG. 7 is a diagram showing a conventional example of a method of allocating a one-dimensional array to a memory.

FIG. 8 is a flowchart showing a procedure of a conventional vector calculation method.

FIG. 9 is a diagram showing a conventional example of a method of allocating a two-dimensional array to a memory.

FIG. 10 is a flowchart showing a procedure of a conventional vector calculation method.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... CPU 11 ... Vector register set 12 ... Vector adder 13 ... Vector multiplier 14 ... Data transfer part 15 ... Instruction interpretation part 2 ... Memory (main memory) 21 ... Instruction code part 211 ... Instruction code string 22 ... Data part 221 ... data string 3 ... loader 4 ... storage device 41 ... object program 5 ... storage device 51 ... source program 6 ... compiler

Claims (4)

[Claims] 1. A method for performing an operation on an array by a vector operation on a computer having a vector operation function, wherein a plurality of same types of calculation formulas which can be calculated independently are to be optimized, and the plurality of calculation formulas are A first step of grouping the arrays that appear on the left side and the arrays that appear at the same position on the right side and assigning the same set of arrays to a continuous area on the memory; and the same position on the right side of the plurality of formulas Allocate one input vector register for each set of arrays that appear in
A second copy of each set of arrays from a continuous area on the memory to the input vector register by a copy instruction;
And an operation on the array copied to the input vector register is executed by a vector operation unit corresponding to the type of operation of the calculation expression, and the operation result is stored in an output vector register. And a vector operation method. 2. The method according to claim 1, wherein the operation result stored in the vector register for output is copied by a copy instruction to a continuous area on the memory allocated to a set of arrays appearing on the left side of the plurality of formulas. 4. The method according to claim 1, further comprising the steps of: 3. A plurality of calculation formulas each of which can be calculated independently, wherein all the arrays included in each calculation formula are one-dimensional arrays, the number and type of operation are the same, and the left side of the plurality of calculation formulas 3. The vector according to claim 1 or 2, wherein a plurality of formulas in which the sum of the number of elements of the arrays appearing in the array and the number of elements of the arrays appearing in the same position on the right side are equal to or smaller than the size of the vector register held by the computer are optimized. Calculation method. 4. A DO loop including a plurality of formulas which can be independently calculated in a loop, wherein the arrays included in the formulas are all multidimensional arrays having the same number of dimensions and the number and type of operation. And the sum of the number of elements per iteration of a loop between arrays appearing on the left side and arrays appearing at the same position on the right side of a plurality of formulas is equal to or less than the size of the vector register held by the computer. 3. The vector calculation method according to claim 1, wherein a plurality of calculation expressions in the DO loop are to be optimized.