JP2000076182A - Bus arbitration system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To avoid the succession of retrying by allowing each bus bridge to issue a bus use permission request to a target-side bus, acquire the right to access the target-side bus, and give priority to the retrying of a bus master when one bus answers retrying at the bus master. SOLUTION: Local bus masters 100, 200, and 300 start performing access and respective bus bridges 102, 202, and 302 issue bus request signals 109, 209, and 309 to a system bus arbiter 400. Namely, when a bus bridge 002 which was requesting access to the system bus answers retrying to access from a local bus master 000, the respective bus bridges 102 to 302 issue bus use permission requests to a target-side bus. Further, the bus bridge 002 acquires a bus grant 008 for the target-side bus and gives priority to the retrying of the local bus master 000 that has received the retrying.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a multiplexed bus for computers, and more particularly to a bus arbitration method suitable for improving reliability and communication performance.

[0002]

2. Description of the Related Art Conventionally, when a plurality of local buses are connected to a system bus, a bus bridge is provided to connect the respective buses. Access between the local bus and the system bus is given priority on a first-come, first-served basis, or Bus lock was avoided by giving either bus a fixed priority, permitting access from the priority bus, and responding to a retry for access to a non-priority bus.

Also, when the access destination bus is performing another access, and the bus is in a busy state, the bus master that has responded to the access source and has received the retry also needs to retry.

[0004]

Conventionally, when a retry response occurs, the bus master receiving the retry simply performs a retry. (A) At the time of retry, the same retry condition as the previous time is satisfied. In such a case, a retry response may be received again and this may be continued, causing a problem that processing is delayed or a phenomenon similar to the locked state of the bus occurs on the side receiving the retry.

(B) Similarly, the occurrence of a plurality of retries for the same access means that an insignificant bus cycle actually occurs, and there has been a problem that the total throughput of the bus is reduced.

(C) There is a problem that the worst definition of the processing time, response time, and throughput cannot be calculated practically because the number of continuous retries cannot be grasped.

(D) When three or more local buses are connected to the system bus, access to the system bus from each of the local buses may continue indefinitely, causing an error due to processing stoppage or timeout. There was a case.

[0008]

A first feature of the present invention is as follows.
When a retry is responded at the time of access from one bus via the bus bridge, each bus bridge requests a bus use permission to the target side bus (hereinafter, bus request).
And the own bus bridge acquires the access right of the target side bus (hereinafter, bus grant), and prioritizes the retry of the bus master that has received the retry, thereby avoiding retry continuation. Bus arbitration.

According to a second feature of the present invention, in addition to the first feature, when a retry occurs in the bus protocol, each local bus arbiter performs a retry until the local bus arbiter acquires the right to access the target side bus via the bus bridge. By providing a function that does not grant a bus grant even to the received master, the retry of the bus master is delayed until the bus related to the access can be acquired, unreliable retry access is avoided, and the total throughput of the bus is reduced. This is a bus arbitration system characterized in that the worst value of the bus access processing time can be calculated.

In other words, according to the present invention, access is completed after a specified number of retries in proportion to the bus hierarchy at worst, so that each bus master can perform equal processing, shorten the access processing time, and reduce the bus processing time. The throughput can be improved, and the access processing time can be guaranteed, so that the processing can be speeded up and the reliability can be improved.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 3 is a diagram illustrating the principle of operation of the present invention. In this figure, a bus arbitration system in a system in which processing devices each having a bus master and a bus target on a local bus are connected by a system bus will be described.

A local bus master 000 for performing bus access such as data processing, memory control, and input / output control, a register, a memory, a local bus target 001 as various input / output interfaces, and a bus bridge 002 for connecting a local bus and a system bus. A processing device A composed of a local bus arbiter 003 for arbitrating access rights of a local bus, and processing devices B, C, and
In a system composed of D and a system bus arbiter 400 for arbitrating the access right of the system bus, the local bus master 000 accesses the local bus target 301 and the local bus masters 100, 200 and 300 almost simultaneously access the local bus target 101.
The principle of operation when access is continuously performed will be described below.

The local bus master 000 issues a bus request signal 004 to the local bus arbiter 003.
Issues a bus grant 005 to Bass Grant 0
The bus master 000 that has received the “05” receives the bus bridge 007.
When the bus bridge 007 recognizes the access from the local bus master 000, the bus bridge 007 sends a bus request 009 to the system bus arbiter 400.
Issue By the same procedure, the local bus master 10
0, 200 and 300 initiate access, and bus bridges 107 and 207 and 307 also provide bus request lines 109 and 20 to system bus arbiter 400.
Issue 9 and 309. At this time, when the system bus arbiter issues the bus grant 108, the bus bridge 1
02 accesses bus bridge 002, where bus bridge 00 requesting access to the system bus
2 responds to the access from the local bus master 000 with a retry and terminates the access from the local bus master 000. Further, the local bus master 000 receiving the retry sends a bus request 0 to the local bus arbiter 003 to start a retry cycle.
Issue 04.

On the other hand, the bus bridge 002 issues a bus request 009 to the system bus side in preparation for the next retry, and issues a bus grant 0 from the system bus arbiter 400.
Wait 08.

Further, the local bus arbiter 003 keeps the bus master 00 until the bus grant 008 from the system bus arbiter 400 to the bus bridge 002 becomes valid.
Delay bus grant 005 to 0.

Meanwhile, the local bus master 10
0, 200 and 300 are completed, and the system bus arbiter 400 issues a bus grant 008.

The local bus arbiter 003, which recognizes the issuance of the bus grant 008, issues a bus grant 005 to the local bus master 000, executes access to the bus bridge 002, and the bus bridge has already acquired the right to access the system bus. Access is possible without receiving a retry response.

FIG. 4 shows an example of a state transition of the bus bridge, and FIG. 5 shows an example of a state transition of the local bus arbiter with respect to the local bus master.

[0019]

According to the present invention, at the worst, the access is completed after the specified number of retries in proportion to the bus hierarchy, so that each bus master can perform equal processing, shorten the access processing time and reduce the bus processing time. The throughput can be improved, and the access processing time can be guaranteed, so that the processing can be speeded up and the reliability can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an example of a system configuration according to a bus configuration of the present invention.

FIG. 2 is a block diagram showing a system configuration example using a conventional bus configuration.

FIG. 3 is an operation principle explanatory diagram for explaining a bus arbitration method of the present invention.

FIG. 4 is a diagram showing an example of a state transition of a bus bridge according to the present invention.

FIG. 5 is a diagram showing an example of a state transition of a local bus arbiter of the present invention with respect to a local bus master.

[Explanation of symbols]

001, 100, 200, 300: Local bus master, 001, 101, 201, 301: Local bus target, 002, 102, 202, 302: Bus bridge, 003, 103, 203, 303: Local bus arbiter, 004, 104, 204, 304, 006, 10
6,206,306,009,109,209,309
... Bus request signal, 005, 105, 205, 30
5,007,107,207,307,008,108,2
08, 308 bus grant signal, 400 system bus arbiter, 1-1, 1-2 CPU (bus master),
2 ... memory (bus target), 3-1, 3-2 ... I /
O (bus target), 1-1, 1-2... Bus arbiters.

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Toshiyuki Murakami 5-2-1, Omikacho, Hitachi City, Ibaraki Prefecture Inside Hitachi Process Computer Engineering Co., Ltd. (72) Ryuichi Watanabe 5-2 Omikacho, Hitachi City, Ibaraki Prefecture No. 1 F term in the Hitachi, Ltd. Omika factory (reference) 5B061 BA01 BB01 FF01 GG02 PP01 PP05

Claims (2)

[Claims] A computer is connected in a hierarchical structure by a plurality of buses, and a device (bus bridge) for connecting a main bus (system bus) to each local bus and a right to use each bus of the system bus and the local bus. In a system having an arbitrating device (bus arbiter), a bus bridge is provided with a bus protocol monitoring function so that when one bus master accesses a bus target connected to a bus different from the bus to which the bus master is connected, When a retry response (retry) is received from the target, the bus bridge that has issued a retry response to the bus master issues a bus use right request (bus request) to the bus arbiter on the target side, and the right to use the target side bus in advance. A bus arbitration method characterized in that the bus master is acquired and the bus master is retried. 2. A local bus arbiter according to claim 1, wherein a bus protocol monitoring function and a bus grant monitoring function on the system bus side are provided in each local bus arbiter, and when a retry occurs in the bus protocol, the local bus use permission (bus A bus arbitration method that stores a bus master to which a grant has been granted, delays a bus use right (bus grant) until a target-side bus can be acquired, and prohibits uncertain retry.