JP2000069373A - Ccd solid-state image pickup device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a CCD solid-state image pickup device that picks-up an image with high sensitivity. SOLUTION: A correction circuit 13 is operated synchronously with other prescribed bit change pattern in operating timing control data CKP to set various image pick-up conditions, such as selection of an exposure time and switching of a read speed of pixel charges, depending on any reference clock signal among reference clock signals CLK1, CLK2, CLK3, etc., and contents of pattern selection data PS.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a CCD solid-state imaging device.

[0002]

2. Description of the Related Art A conventional CCD solid-state imaging device is disclosed in Japanese Patent Application Laid-Open Nos. Hei 1-305672 and Hei 1-1114174.

[0003]

In recent years, in the field of measurement technology, a measurement system that receives light or the like emitted from an object to be measured by a CCD solid-state imaging device and analyzes and processes an output signal as image information has become widespread. There is a growing demand for such applications.

[0004]

According to the present invention, in a CCD solid-state imaging device capable of switching imaging conditions, the imaging conditions include a reading speed of pixel charges generated in a photosensitive portion. The imaging condition may include an exposure time.

[0005]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) A first embodiment of the present invention will be described with reference to FIGS. First, the overall configuration will be described with reference to FIG. The apparatus of the present embodiment is manufactured by a semiconductor manufacturing technique, and the photosensitive unit 1 for receiving light from a measurement target has a configuration to which a so-called line transfer (LT) system or an interline transfer (ILT) system is applied. .

That is, in the photosensitive section 1 based on the LT method, m vertical charge transfer paths having photosensitive characteristics by themselves are provided along the horizontal direction j in the figure.
In each vertical charge transfer path, n pixels are realized along the vertical direction i. Then, the pixel charges generated in each pixel by the exposure are transferred to a plurality of horizontal shift registers 5a, 5b, 5c to be described later in synchronization with a vertical transfer clock signal φV at a predetermined timing output from the vertical scanning circuit 2. Forward.

On the other hand, in the photosensitive section 1 based on the ILT method, a total of m × n of m columns in the horizontal direction j and n rows in the vertical direction i is used.
A pixel group including a plurality of photodiodes and the like is provided, and m light-shielded vertical charge transfer paths are alternately provided between m columns of pixel groups including n pixels per column. Then, after a pixel signal generated in each pixel by the exposure is once transferred to an adjacent vertical charge transfer path, a plurality of horizontal signals described later are synchronized with a vertical transfer clock signal φV at a predetermined timing from the vertical scanning circuit 2. Shift registers 5a, 5b,
Transfer to 5c side.

Therefore, in either system, a total of m × n pixel groups arranged in a matrix in the horizontal direction j and the vertical direction (the direction in which pixel charges are transferred) i are provided. In FIG. 1, each part divided by a dotted line is shown as equivalent to one pixel.

Further, a light-shielding layer such as an aluminum layer is laminated on the surface of the pixel group for one row or a plurality of rows from the lowermost end of the photosensitive section 1. Therefore, these light-shielded pixel groups do not expose the object to be measured, despite having normal photosensitive characteristics. For example, the photosensitive unit 1 generates unique pixel charges due to electrical characteristics. It will be. FIG. 1 shows a case where a light-blocking layer is provided in a pixel group for two horizontal lines in the (n-1) th row and the nth row.
In the following description, a region where such a light shielding layer is provided is referred to as a reference region 3. Further, the light-shielding layer is not limited to a layer that completely blocks external light from entering, and has, for example, a light-transmitting property such that uniform light can enter all pixels in the reference region 3. It may be something. In short, the reference region 3 refers to a region where uniform pixel charges are constantly generated in all pixels.

Following the reference area 3, a first transfer gate 4a, a first horizontal shift register 5a, a second transfer gate 4b, and a second horizontal shift register 5
b, a third transfer gate 4c and a third horizontal shift register 5c are sequentially provided. Further, output mechanisms 6a, 6b, and 6c are formed at the ends of the horizontal shift registers 5a, 5b, and 5c to convert pixel charges into voltage or current pixel signals and perform dot-sequential reading.

These transfer gates 4a, 4b,
4c and the horizontal shift registers 5a, 5b, 5c distribute pixel charges for one horizontal line to the horizontal shift registers 5a, 5b, 5c in synchronization with a predetermined timing signal output from the horizontal scanning circuit 7. And horizontal transfer of pixel charges. Although detailed operations will be described later, i = 1, 4, 7,... M by the first transfer gates 4a, 4b, 4c.
-2 pixel charges to the horizontal shift register 5c, i = 2,
The pixel charges of 5, 8,..., M-1 are transferred to the horizontal shift register 5b.
, M = 3, 6, 9,... M are distributed to the horizontal shift register 5a. The first to third horizontal shift registers 5a, 5b, and 5c receive a predetermined horizontal transfer clock signal φH from the horizontal scanning circuit 7 after the pixel charges for the one horizontal line are allocated in a predetermined arrangement. Synchronously,
The pixel charges are transferred in parallel to the output mechanisms 6a, 6b, 6c.

The vertical transfer clock signal φV and the horizontal transfer clock signal φH output from the vertical scanning circuit 2 and the horizontal scanning circuit 7 are generated in synchronization with the operation timing control data CKP output from the timing control circuit 8. You.

That is, the timing control circuit 8 includes a plurality of types of reference clock signals CLK1, CLK1 having different frequencies from each other.
CLK2, CLK3... Are supplied and the selection signal C
A multiplexer circuit 9 for selecting any one of the reference clock signals in accordance with S, a reference clock signal output from the multiplexer circuit 9 and a pattern selection data PS input via an external terminal. An address setting circuit 10 for generating decode data having a predetermined correlation with the count data, and a read-only memory 11 for outputting operation timing control data CKP from a memory area designated by the decode data are provided. . The vertical scanning circuit 2 and the horizontal scanning circuit 7 synchronize with the vertical transfer clock signal φV and the horizontal transfer clock signal at the predetermined timing in synchronization with a change pattern of data of a predetermined bit of the operation timing control data CKP composed of a plurality of bits. Output φH.

The output mechanisms 6a, 6b, 6c and a correction circuit 13, which will be described later, also operate in synchronization with a change pattern of another predetermined bit in the operation timing control data CKP. Signals CLK1 and CL
Setting of various imaging conditions, such as selection of exposure time and switching of pixel charge readout speed, in accordance with one of the reference clock signals K2, CLK3,... And the contents of the pattern selection data PS. Is available.

First to third horizontal shift registers 5a, 5
b, 5c, output mechanisms 6a, 6b,
FIG. 2 shows one structural example of 6c. As a representative of the output mechanism 6a, a transfer gate G1 and a reset gate G2 are formed at the end of the first horizontal shift register 5a, and a floating diffusion FD and a drain portion DD are formed in the substrate. Also, the drain portion D
D is always applied with a predetermined voltage VDD, and the floating diffusion FD is composed of electric field transistors FET1 and FE.
It is connected to an amplifier circuit composed of T2 and resistors R1 and R2.

Then, as shown in the timing chart of FIG. 3, the reset gate G2 is synchronized with the period τp in which the horizontal shift register 5a transfers the pixel charge of one pixel.
Charge is injected into the floating diffusion FD by applying a logic "H" reset signal DG to the floating diffusion FD, and a logic "H" on signal OG is applied to the transfer gate OG at a predetermined timing within each cycle τp. Thereby, the pixel charge for one pixel is transferred to the floating diffusion FD. When such an operation is repeated, the pixel signal Va output from the electric field transistor FET2 becomes a feedthrough voltage VF corresponding to the amount of charge injected into the floating diffusion FD due to the reset, and then the pixel signal Va for one pixel transferred is transferred. The electric charge is coupled with the electric charge injected into the floating diffusion FD, and becomes a voltage VQ corresponding to the pixel electric charge for one pixel. Then, a double sample-and-hold circuit, which will be described later, uses the voltages VF and VQ for each period τp.
Is sampled and held, and the difference between these voltages (VF−
VQ) is a pixel signal of one pixel.

The configuration and operation of the second and third output mechanisms 6b and 6c are the same as those of the first output mechanism 6a, and the pixel signals are indicated by Vb and Vc in the figure.

The three-channel output mechanism 6a,
Preamplifier circuits 12a, 12b, and 12c for amplifying each pixel signal Va, Vb, and Vc with a constant gain to a voltage (or current) level at which signal processing is possible are connected to 6b and 6c.
Each of the amplified pixel signals Va, Vb, and Vc is input to a correction circuit 13 where a predetermined correction process is performed, and each is converted into digital pixel data and sequentially recorded in the frame memory 14 or the like.

Next, the configuration of the correction circuit 13 will be described with reference to FIG. A pair of sample-and-hold circuits 15ax, 15a is connected to the output contact of the preamplifier circuit 12a of the first channel.
y are connected in parallel and these circuits 15ax and 1
The subtraction circuit 16a is connected to the output contact of 5ay. Preamplifier circuits 12b and 12c for second and third channels
Similarly, a pair of sample-and-hold circuits 15bx and 15by, 15cx and 15cy are connected in parallel to each output contact of
A subtraction circuit 16b is connected to the output contact of by, and a subtraction circuit 16c is connected to the output contacts of the sample hold circuits 15cx and 15cy.

Here, these circuits constitute the above-mentioned double sample hold circuit, all the sample hold circuits 15ax to 15cy have the same electrical characteristics, and all the subtraction circuits 16a to 16c have the same electrical characteristics. Characteristic. Further, the sample and hold circuits 15ax, 1
As shown in FIG. 3, 5bx and 15cx sample the feed-through voltage VF of the pixel signals Va to Vc in synchronization with the sample-and-hold signal SH1 in synchronization with the period τp in which each pixel charge is read out. 15ay, 15by and 15cy are the periods τp shown in FIG.
The pixel voltage VQ of the pixel signals Va to Vc is sampled in synchronization with the sample and hold signal SH2 synchronized with.
Accordingly, the subtraction circuits 16a to 16c of the respective channels output signals PVa, PVb and PVc of the difference voltage between the voltages VF and VQ in synchronization with the period τp.

According to such a double sample hold circuit, noise generated in each of the output mechanisms 6a, 6b, 6c generated in the photosensitive section 1 can be removed from the signals Va, Vb, Vc. That is, as shown in FIG. 3, the dark current generated in the photosensitive unit 1 or the fluctuation of the voltage VF generated in the floating diffusion FD when each of the output mechanisms 6a, 6b, 6c repeats the reset operation every cycle τp. Noise and low figure wave noise such as 1 / f noise generated in the output FETs 1 and 2 are converted to a differential voltage (VF-VQ) by each pixel signal PV.
a, PVb and PVc can be removed.

The pixel signal PV from which noise has been removed as described above
a, PVb, and PVc are supplied to a gain correction circuit. This gain correction circuit includes division circuits 17a and 17b, average value holding circuits 18a and 18b, and multiplication circuits 19a and 19b.
b.

The division circuit 17a divides the pixel signal PVa from the pixel signal PVc, and outputs the divided signal HV.
a (= PVc ÷ PVa), and the division circuit 17b outputs
The pixel signal PVb is divided from the pixel signal PVc, and a signal HVb (= PVc ÷ PVb) resulting from the division is output.

The average value holding circuit 18a calculates the average value of the signal HVa generated during the period TAV until all the pixel charges generated in the pixel group in the reference area 3 of FIG. 1 are read out, and calculates the average value. Is output as the average value signal AVa of the voltage or current corresponding to. The average value holding circuit 18b calculates the average value of the signal HVb generated during the period TAV of reading out all the pixel charges generated in the pixel group in the reference region 3 in FIG. 1, and calculates the voltage corresponding to the average value. Alternatively, it outputs an average value signal AVb of the current.

The average value holding circuits 18a, 18a,
18b has a uniform circuit configuration. For example, as shown in FIG. 5, each of the circuits includes an analog switch SW that is in a conductive state only during a period TAV during which the control signal SAV is at a logic "H", and a resistor Rx. It has a hold circuit formed by the capacitor Cx. When the analog switch SW is in the conductive state, the division circuits 17a and 17
The pixel signals HVa and HVb output from b are stored as charges in the capacitors Cx of the respective channels.

The multiplication circuit 19a multiplies the pixel signal PVa from the subtraction circuit 16a by the average value signal AVa from the average value holding circuit 18a, and outputs the result of the multiplication as a pixel signal Ra (= PVa × AVa). . The multiplication circuit 19b multiplies the pixel signal PVb from the subtraction circuit 16b by the average value signal AVb from the average value hold circuit 18b, and outputs the result of the multiplication by the pixel signal Rb (= PVb × A).
Vb).

The A / D converter 20a outputs the pixel signal R
a is digitally converted into pixel data Da having a predetermined number of bits and stored in the frame memory 14, and the A / D converter 20b converts the pixel signal Rb into digital data Db having a predetermined number of bits and stored in the frame memory 14. , An A / D converter 20c digitally converts the pixel signal PVc into pixel data Dc of a predetermined number of bits and stores the data in the frame memory 14.

Next, the operation of this embodiment having the above configuration will be described with reference to FIGS. The operation in one frame period for capturing one frame image will be described. FIG. 6 shows the horizontal shift registers 5a and 5a from the photosensitive unit 1.
The operation of reading out pixel charges via the lines b and 5c will be described. FIG.
Shows a timing chart of an output waveform, and a period TAV in the figure is a period during which all pixel charges of the pixel groups in a plurality of rows included in the reference region 3 are read out, and a period TRD is a period during which pixel charges to be measured are read out. , And the period of reading out the pixel charges for one horizontal line is indicated by a 1H period.

First, operation timing control data CKP for setting a desired exposure time or the like in one frame cycle is obtained by externally inputting a selection signal CS and pattern selection data PS to the timing control circuit 8 in FIG. Then, the entire apparatus operates synchronously based on the data CKP.

When the photosensitive section 1 exposes the object to be measured for a predetermined time, reading of pixel charges is started in synchronization with vertical and horizontal scanning clock signals output from the vertical scanning circuit 2 and the horizontal scanning circuit 7. An example of the read operation will be described with reference to FIG. For convenience of explanation, a case where pixel charges A to F generated in six pixels existing in the n-th row in the reference area 3 are read as shown in FIG. .

First, as shown in FIG. 2B, when the first transfer gate 4a is turned on for a certain period of time, the pixel charges A and D are transferred to a predetermined potential well of the first horizontal shift register 5a. Is forwarded to next,
As shown in FIG. 3C, the second transfer gate 4
By turning on b for a certain period of time, the pixel charges A and D are transferred to a predetermined potential well of the second horizontal shift register 5b, and then the first transfer gate 4a is turned on for a certain period of time. As a result, the pixel charges B and E are transferred to a predetermined potential well of the first horizontal shift register 5a. Next, as shown in FIG. 4D, the third transfer gate 4c is turned on for a certain period of time, so that the pixel charges A and D become the third state.
Is transferred to a predetermined potential well of the horizontal shift register 5c, the second transfer gate 4b is turned on for a certain period of time, so that the pixel charges B and E are transferred to the predetermined potential of the second horizontal shift register 5b. The pixel charges C and F are transferred to a predetermined potential well of the first horizontal shift register 5a by being transferred to the well and then the first transfer gate 4a being turned on for a predetermined time. As described above, the pixel charges A to F for one horizontal line are stored in the first to third horizontal shift registers 5.
a to 5c are transferred after being divided into three parts, as shown in FIG.
5c perform horizontal transfer, and output pixel charges A, B, and C located in the front row via output mechanisms 6a to 6c. Next, as shown in FIG.
5c perform the next horizontal transfer, and output pixel charges D, E, and F via output mechanisms 6a to 6c. When the reading of the pixel charges generated in the pixel group on the n-th row in the reference region 3 is completed in this way, the pixel charges generated on the pixel group on the next (n-1) -th row are similarly read. Similarly, pixel charges generated in the remaining pixel groups of each row i are read out in the same manner.

The pixel signals Va to Vc read out in this manner are input to the correction circuit shown in FIG.
The sample hold circuits 15ax, 15ay, 15bx,
15by, 15cx, 15cy and subtraction circuits 16a-1
6c removes various noise components from the pixel signals Va to Vc, and outputs the pixel signals PVa to PVc. Further, the dividing circuit 17
a and 17b perform the above-mentioned division processing, and convert the operation result signals HVa and HVb into average value hold circuits 18a and 18b.
Supply to

Here, the control signal SAV becomes logic "H" during a period TAV until all the pixel charges generated in the reference area 3 are read out from the output mechanisms 6a to 6c.
The average value holding circuit 18a samples and holds the pixel charges in the reference area 3 read via the horizontal shift register 5a and the output mechanism 6a of the first channel, and the average value holding circuit 18b controls the horizontal charge of the second channel. The pixel charge in the reference area 3 read via the shift register 5b and the output mechanism 6b is sampled and held. Then, at the end of the period TAV, the average value signal AV based on the pixel charges read from each channel.
a and AVb are determined. FIG. 7 is a typical example,
In the case where the reference region 3 is formed of a group of light-shielded pixels of 10 rows, it is shown that the average value signals AVa and AVb are determined by reading out the pixel charges over a 10H period.

Further, the average value holding circuits 18a, 18b
Then, as shown in FIG. 7, the divided signals HVa, HV
b is input, and the average value signals AVb, AVb gradually converge to a predetermined voltage level. On the other hand, the output signals Ra and Rb of the multiplication circuits 19a and 19b are the result of multiplication of the average signal AVa and the pixel signal PVa and the result of multiplication of the average signal AVb and the pixel signal PVb.
The amplitude of b gradually coincides with each other by correcting the mutual gain variation of the output mechanisms 6a, 6b, 6c.
The time tx coincides at the completion time tx of the period TAV.

Therefore, for example, the pixel signals Va to Vc which should have the same amplitude are output from the output mechanisms 6a and 6c.
Even if pixel signals PVa to PVc having different amplitudes are generated due to gain variations between b and 6c, the average value signals AVa and A held in the average value holding circuits 18a and 18b.
Pixel signals Ra and R whose amplitude levels have been corrected by Vb
b is formed. Since the gain correction is performed based on the signal PVc, a gain correction circuit for correcting the signal PVc is not provided in this embodiment. And
In the period TRD, the average signal AVa,
Based on AVb, the gain of each of the pixel signals PVa and PVb is corrected.

The pixel signals PVa, PVb, and PVc generated every period (period of dot-sequential reading) τp are converted to PVa, respectively.
(k), PVb (k), and PVc (k), as shown in FIG.
In a CCD solid-state imaging device having channels, 1
Number of pixel charges K output by each channel per H period
Since K = m / 3, 1 ≦ k ≦ m / 3, and the average value signals AVa and AVb are represented by the following equations.

[0037]

(Equation 1)

Further, when the reference area 3 includes N rows of light-shielded pixel groups, the following equation is obtained.

[0039]

(Equation 2)

The signals Ra (k) and Rb output during the period TRD after the average value signals AVa and AVb are determined.
(k) is given by the following equation.

[0041]

(Equation 3)

As is apparent from these equations (1) to (6), the gain variation between channels is corrected.

By the way, when the gain correction circuit of this embodiment is not provided, the gain variation of the pixel signals PVa to PVc of each channel is not corrected during the period TAV as shown in FIG. , The true pixel signals PVa to PVc cannot be obtained even in the period TRD.

As described above, in this embodiment, before reading out the pixel charges of the object to be measured generated by the exposure, the pixel charges generated in the reference area 3 are read out in advance through the respective channels, and the output mechanisms 6a to 6c To obtain average value signals AVa and AVb corresponding to the variation in the gain of
Since the pixel signal to be measured is corrected by a and AVb, a so-called feed-forward type correction circuit is provided. As a result of applying such a feedforward method, it is extremely difficult to set a time constant for feedback in the conventional feedback method described later, but such a problem can be solved. Note that, in this embodiment, the case of three channels has been described. However, the present device can be applied to a CCD solid-state imaging device having a plurality of channels by providing a correction circuit corresponding to the number of channels. Can be.

(Second Embodiment) Next, a second embodiment will be described.
This will be described with reference to FIGS. In these figures, the same or corresponding components as those in FIG. 1 are indicated by the same reference numerals. The basic difference between this embodiment and the first embodiment is that, in the first embodiment, as shown in FIG. 1, a plurality of horizontal shift registers 5a to 5c realizes a plurality of channels and reads pixel charges in parallel. In the present embodiment, the photosensitive unit 101 is divided into a plurality of regions (divided into four regions in FIG. 9) and provided independently in each region. Horizontal shift register 10 for four channels
Pixel charges are read out in parallel via 7UL, 107UR, 107LL, and 107LR.

First, the overall configuration of this embodiment will be described with reference to FIG. The photosensitive unit 101 has a configuration to which the LT system or the ILT system is applied, and is equally divided into four photosensitive regions, and each region corresponds to an individual channel.
Regarding the reference numerals indicating the components, those belonging to the first channel are suffixed with UL, those belonging to the second channel are suffixed with UR, and those belonging to the third channel are L.
Subscripts of L and those belonging to the fourth channel are indicated by subscripts of LR.

As a representative example of the configuration of the first channel, a horizontal shift register 105UL is formed in this photosensitive area via a transfer gate 104UL, and an output mechanism 106UL is formed at the end of the horizontal shift register 105UL. I have. Further, a pixel group for a plurality of horizontal lines from the transfer gate 104UL is
03UL. Then, the pixel charges generated in the photosensitive area by the exposure are transferred to the horizontal shift register 1 in synchronization with the vertical transfer clock signal φVU from the vertical scanning circuit 102U.
05UL, one horizontal line at a time, and the horizontal shift register 105UL further synchronizes with the horizontal scanning clock signal φHUL from the horizontal scanning circuit 107UL.
Transferred to 6UL. Therefore, each pixel charge is read out in a dot-sequential manner. Further, after the pixel charges of the shielded reference region 103UL are read out first, the pixel charges relating to the measured object are read out. The output mechanism 106UL has the same configuration as that shown in FIG. 2, and reads out pixel charges in a dot-sequential manner based on the same operation principle as the timing chart shown in FIG. The horizontal scanning circuit 107UL and the vertical scanning circuit 102U operate in synchronization with predetermined bit data of the operation timing control data CKP output from the timing control circuit 8, as in the first embodiment.

The configuration of the remaining second to fourth channels is the same as that of the first channel. The second channel is composed of a reference unit 103UR and a transfer gate 104UR.
, Horizontal shift register 105UR, and output mechanism 106UR
And a horizontal scanning circuit 107UR, and after transferring pixel charges generated in the photosensitive region by exposure to the horizontal shift register 105UR by one horizontal line in synchronization with the vertical transfer clock signal φVU from the vertical scanning circuit 102U, The horizontal shift register 105UR is synchronized with the horizontal scanning clock signal φHUR from the horizontal scanning circuit 107UR to output the output mechanism 106UR.
And read them out dot-sequentially.

The third channel includes a reference section 103LL, a transfer gate 104LL, and a horizontal shift register 10LL.
5LL, an output mechanism 106LL, and a horizontal scanning circuit 107LL.
The vertical transfer clock signal φVL from the vertical scanning circuit 102L
The horizontal shift register 105LL transfers the data to the output mechanism 106LL in synchronization with the horizontal scanning clock signal φHLL from the horizontal scanning circuit 107LL, and reads the data in a dot-sequential manner. put out.

The fourth channel includes a reference section 103LR, a transfer gate 104LR, and a horizontal shift register 10LR.
5LR, an output mechanism 106LR, and a horizontal scanning circuit 107LR.
The vertical transfer clock signal φVL from the vertical scanning circuit 102L
The horizontal shift register 105 LR transfers the data to the output mechanism 106 LR in synchronization with the horizontal scanning clock signal φHLR from the horizontal scanning circuit 107 LR, and reads the data in a dot-sequential manner. put out.

An example of the operation of reading out the pixel charges will be described with reference to FIG. FIG. 11 shows, as shown in FIG. 11A, the reference areas 103UL, 103UR, 1
A case where pixel charges A to X generated in 03LL and 103LR are read is shown as a representative. First, as shown in FIG.
By turning on the transfer gates 104UL to 104LR for a certain period of time, the pixel charges A to F are stored in the horizontal shift register 105UL, the pixel charges G to L are stored in the horizontal shift register 105UR, and the pixel charges M to R are stored in the horizontal shift register 105LL. Next, the pixel charges S to X are respectively transferred to the horizontal shift register 105LR. Next, as shown in FIG. 3C, the horizontal shift registers 105UL to 105LR perform horizontal transfer for one pixel, thereby causing the pixel charges A,
L, M, and X are read out, and then, as shown in FIG.
When the horizontal shift registers 105UL to 105LR perform horizontal transfer for one pixel again, the next pixel charges B, K,
Read N and W. The remaining horizontal charges are read out by repeating the same horizontal transfer, and when the reading of one horizontal line is completed, the pixels of the next one horizontal line transferred from each area of the photosensitive unit 101 are read out. This process is repeated until charges are read out and all pixel charges are read out.

As described above, in synchronization with the predetermined period τp, 4
4 via the channel output mechanism 106UL-106LR
Since the two pixel charges are read out in parallel, the reading speed can be improved about four times.

Each of the output mechanisms 106UL to 106LR is connected to the correction circuit 13 via the preamplifier circuits 112UL to 112LR, and the output of the correction circuit 13 is connected to the frame memory 14.

Next, the configuration of the correction circuit 13 will be described with reference to FIG. The first channel is provided with a double sample and hold circuit comprising sample and hold circuits 115ULx and 115ULy and a subtraction circuit 116UL, and the second channel is provided with sample and hold circuits 115URx and 115UR.
y and a subtraction circuit 116UR, a double sample and hold circuit is provided on the third channel, sample and hold circuits 115LLx and 115LLy and a subtraction circuit 116LL are provided on the third channel, and a sample and hold circuit is provided on the fourth channel. 115LRx, 115L
A double sample and hold circuit including Ry and a subtraction circuit 116LR is provided. Each of the double sample hold circuits operates in the same manner as in the first embodiment.
Noise components generated in the output mechanisms 106UL, 106UR, 106LL, 106LR, etc. are removed from the pixel signals VUL, VUR, VLL, VLR, and the pixel signals PVUL, PVU without the noise components are removed.
R, PVLL, and PVLR are output.

Further, a gain correction circuit including division circuits 117UL, 117UR, 117LL, average value hold circuits 118UL, 118UR, 118LL, and multiplication circuits 119UL, 119UR, 119LL is connected to the double sample hold circuit. This gain correction circuit is similar to the gain correction circuit in the first embodiment (see FIG. 4), and the output mechanism 106
The gain variation among UL, 106UR, 106LL, 106LR is corrected, and the corrected pixel signals RUL, RUR, RLL are corrected.
Is output. And A / D converters 120UL, 121U
R, 120LL, and 120LR are the pixel signals RUL, RU
R, RLL and PVLR are respectively set to pixel data DUL,
The data is converted into DUR, DLL, and DLR and stored in the frame memory 14.

As described above, according to this embodiment, even if the positions of the horizontal shift register and the output mechanism provided in the photosensitive section are different from those of the first embodiment, the position of the horizontal shift register and the output mechanism is different between the output mechanisms. Gain variation can be corrected. Further, since the correction circuit is a so-called feed-forward type correction circuit, it is possible to eliminate the difficulty of changing the feedback time constant as in the conventional feedback control method described later.

(Third Embodiment) Next, a third embodiment of the present invention will be described with reference to FIG. In FIG.
Components that are the same as or correspond to those in FIG. 4 are denoted by the same reference numerals. The difference between this embodiment and the first embodiment will be described.
The gain correction circuit of the first embodiment corrects the amplitudes of the pixel signals PVa and PVb of the first and second channels with reference to the pixel signal PVc of the third channel, so that the output mechanisms 6a, 6b, In the third embodiment, all the output mechanisms of the first to third channels are corrected with reference to a constant reference voltage Vref output from the reference voltage generation circuit 200. It is configured to correct the gain variation between the two.

Referring to FIG. 12, the configuration of such a gain correction circuit will be described. A subtraction circuit (divider circuit) 217a and an average value hold circuit 21 are provided in a subtraction circuit 16a, which is a component of a double sample hold circuit relating to the first channel.
8a and a gain correction circuit comprising a multiplication circuit (multiplication circuit) 219a, and a subtraction circuit 16b of the second channel.
Includes a division circuit 217b and an average hold circuit 218b.
And a gain correction circuit including a multiplication circuit 219b, and a subtraction circuit 2c is connected to the subtraction circuit 16c of the third channel.
17c, average value hold circuit 218c and multiplication circuit 21
9c is connected.

All the gain correction circuits have the same configuration and electrical characteristics. As a representative of the gain correction circuit of the first channel, the division circuit 217a divides the reference voltage Vref output from the reference voltage generation circuit 200 by the pixel signal PVa output from the subtraction circuit 16a, and calculates the operation result. Is supplied to the average value hold circuit 218a. Note that the average value holding circuit 218a has the same function as the average value holding circuit 18a (see FIG. 4) described in the first embodiment, and generates a signal HVa generated during a period TAV set by the control signal SAV. , And outputs an average signal AVa indicating the average value. Then, the multiplying circuit 219a multiplies the pixel signal PVa by the average value signal AVa, outputs a signal Ra of the operation result, and the A / D converter 20a converts the signal Ra into pixel data Da and stores it in the frame memory 14. Let it.

Therefore, the average value holding circuit 218a
Since the average value is determined by adding the division result HVa of the division circuit 217a during the period TAV during which the pixel group of the reference area 3 is read, the average value is determined. Is the determined average signal A
Va is multiplied by the pixel signal PVa in the period TRD.

The pixel signals PVa, PVb, and PVc generated in each cycle τp for reading out the pixel charges are respectively represented by PVa
(k), PVb (k) and PVc (k), the CCD solid-state imaging device having three channels shown in FIG.
Number of pixel charges K output from each channel per 1H period
Since K = m / 3, 1 ≦ k ≦ m / 3, and the average value signals AVa and AVb are represented by the following equations.

[0062]

(Equation 4)

Further, when the reference area 3 includes N rows of light-shielded pixel groups, the following equation is obtained.

[0064]

(Equation 5)

The pixel signals Ra (k) and R (k) output during the period TRD after the average value signals AVa and AVb are determined.
b (k) and Rc (k) are represented by the following equations.

[0066]

(Equation 6)

As is apparent from the equations (7) to (15), the gain variation between the output mechanisms 6a to 6c related to each channel is determined by the respective average value signals AVa and AVa.
Since there is a correlation with b and AVc, it is possible to obtain pixel signals Ra to Rc from which gain variations have been removed from the pixel signals PVa to PVc read out during the period TRD.

(Fourth Embodiment) Next, a fourth embodiment will be described.
This will be described with reference to FIG. In this figure, the same or corresponding components as those in FIGS. 9 and 10 are denoted by the same reference numerals. The basic difference between the present embodiment and the second embodiment is that the gain correction circuit of the second embodiment is configured to correct the variation in the gain between the output mechanisms 6a to 6c in order to correct the pixel signal of the fourth channel. P
Pixel signals PV of the first to third channels with reference to VLR
In the fourth embodiment, the amplitudes of UL, PVUR, and PVLL are corrected and controlled. In the fourth embodiment, the first to fourth signals are set based on a constant reference voltage Vref output from the reference voltage generation circuit 300.
The configuration is such that gain variations among all output mechanisms of the channel are corrected.

Referring to FIG. 13, the difference from the second embodiment (see FIG. 10) is that the subtraction circuit 11 which is a component of the double sample and hold circuit related to the first channel is shown.
A gain correction circuit including a division circuit (division circuit) 317UL, an average hold circuit 318UL, and a multiplication circuit 319UL is connected to 6UL, and the subtraction circuit 116 of the second channel is connected to 6UL.
UR has a dividing circuit 317UR and an average value holding circuit 318.
A gain correction circuit including a UR and a multiplication circuit 319UR is connected. A subtraction circuit 317LL, an average hold circuit 318LL, and a multiplication circuit 3
A gain correction circuit composed of 19LL is connected to the subtraction circuit 116LR of the fourth channel, and a gain correction circuit composed of a division circuit 317LR, an average hold circuit 318LR, and a multiplication circuit 319LR is connected.

All the gain correction circuits have the same configuration and electrical characteristics. As a representative example of the gain correction circuit of the first channel, the division circuit 317UL is
The pixel signal PVUL output from 6UL is divided by the reference voltage Vref of a constant value output from the reference voltage generation circuit 300, and the signal HVUL of the calculation result is supplied to the average hold circuit 318UL. The average value hold circuit 318UL
Is the average value hold circuit 118 described in the second embodiment.
It has the same function as UL (see FIG. 10), finds the average value of the signal HVUL generated during the period TAV set by the control signal SAV, and outputs an average signal AVUL indicating the average value. . The multiplication circuit 319UL outputs the pixel signal PV
The multiplication of UL and the average value signal AVUL is performed, and a signal RUL of the calculation result is output. The A / D converter 120UL converts the signal into pixel data DUL and stores the data in the frame memory 14.

Therefore, the average value holding circuit 318UL
Since the division result HVUL of the dividing circuit 317UL is added during the period TAV for reading out the pixel group of the reference region 3 and the average value is determined, the period TRD for reading out the pixel charges obtained by exposing the object to be measured is Is the determined average signal A
VUL is multiplied by the pixel signal PVUL for the period TRD.

The gain correction circuits of the other channels function in the same manner, and the output mechanism 106U for each channel
The variation in gain among L, 106UR, 106LL, and 106LR is determined by the average signal VAUL, VAUR, VALL, VA, respectively.
Since there is a correlation with LR, it is possible to obtain pixel signals RUL to RLR from which gain variations have been removed from the pixel signals PVUL to PVLR read out during the period TRD.

As described above, according to this embodiment, the so-called feed-forward type correction circuit can suppress the variation in the gain of the output mechanism between the channels, and can read out the pixel signals with high accuracy, thereby providing a clear image. A reproduced image can be realized.

(Fifth Embodiment) Next, a fifth embodiment will be described. The configuration of the apparatus of this embodiment is shown in FIGS.
Since this is the same as the first embodiment shown in FIG.

The difference between the present embodiment and the first embodiment will be described. The correction circuit 13 of the first embodiment corrects the gain variation between the output mechanisms to equalize the variation in characteristics between channels. In this embodiment,
A correction circuit is provided for correcting variations in the offset level between the output mechanisms.

The configuration of the offset characteristic correction circuit of this embodiment will be described with reference to FIG. This offset characteristic correction circuit is provided instead of the gain correction circuit of the first embodiment cascaded with the subtraction circuits 16a to 16c of each channel included in the double sample hold circuit. In the present embodiment, the division circuits 17a and 17b provided in the first embodiment are replaced with subtraction circuits, and the multiplication circuits 19a and 19b provided in the first embodiment are replaced by Instead of an adder circuit. The subtraction circuit and the addition circuit are denoted by reference numeral 17a,
17b, 19a, and 19b.

The subtraction circuit 17a subtracts the pixel signal PVa of the first channel from the pixel signal PVc of the third channel, and a signal HVa (= PVc-PVa) resulting from the subtraction is obtained.
Is supplied to the average value holding circuit 18a. The average value holding circuit 18a adds and averages the signal HVa generated during the period TAV during which all the pixel charges of the pixel group in the reference area 3 are read out, and outputs the result as an average value signal AVa. This period T
After the lapse of AV, during a period TRD for reading out the pixel charges of the photosensitive section 1, the addition circuit 19a adds the average value signal AVa and the pixel signal PVa to remove an offset component in the pixel signal PVa. Then, the pixel signal Ra obtained as a result of the addition is converted into digital pixel data Da by the A / D converter 20a and stored in the frame memory 14.

On the other hand, the subtraction circuit 17b converts the pixel signal PVc of the third channel into the pixel signal PVb of the second channel.
And the signal HVb (= PVc-P
Vb) is supplied to the average value holding circuit 18b. The average value holding circuit 18b outputs a signal HVb generated during a period TAV during which all pixel charges of the pixel group in the reference region 3 are read out.
Are averaged and output as an average signal AVb. After the elapse of the period TAV, during a period TRD for reading out the pixel charges of the photosensitive section 1, the addition circuit 19b adds the average value signal AVb and the pixel signal PVb to thereby obtain the pixel signal PVb.
Remove the offset component inside. Then, the pixel signal Rb obtained as a result of the addition is converted into digital pixel data Db by the A / D converter 20b, and the frame memory 1
4 is stored.

The pixel signal PVc serving as a reference for correcting the pixel signals PVa and PVb of the first and second channels is directly converted by the A / D converter 20c into pixel data D.
c and is stored in the frame memory 14.

During the period TAV, the subtraction circuits 16a, 1
The pixel signals sequentially output from 6b and 16c are PVa
(k), PVb (k), and PVc (k), the CCD solid-state imaging device having three channels shown in FIG.
The number of pixel charges K output from each channel per period is
Since K = m / 3, 1 ≦ k ≦ m / 3, and the average value signals AVa and AVb are represented by the following equations.

[0081]

(Equation 7)

Further, when the reference area 3 includes a pixel group of N rows, the following equation is obtained.

[0083]

(Equation 8)

The signals Ra (k) and Rb output during the period TRD after the average value signals AVa and AVb are determined
(k) is given by the following equation.

[0085]

(Equation 9)

As is apparent from the equations (16) to (21), the variation in the offset characteristics between channels is corrected.

(Sixth Embodiment) Next, a sixth embodiment will be described. The configuration of the apparatus of this embodiment is shown in FIGS.
9 and FIG. 1 are the same as in the second embodiment shown in FIG.
It will be described together with 0.

The difference between the present embodiment and the second embodiment will be described. The correction circuit 13 of the second embodiment corrects the gain variation between the output mechanisms to equalize the characteristic variation between channels. In this embodiment,
A correction circuit is provided for correcting variations in the offset level between the output mechanisms.

The configuration of the offset characteristic correction circuit of this embodiment will be described with reference to FIG. Subtraction circuits 116UL to 116 of each channel included in the double sample hold circuit
This offset characteristic correction circuit is provided instead of the gain correction circuit of the first embodiment cascaded to LR. And the second
The division circuits 117UL, 117UR,
In this embodiment, 117LL is replaced with a subtraction circuit,
Multiplying circuits 119UL, 119UR,
119LL is replaced by an adder circuit in this embodiment.
The subtraction circuit and the addition circuit are denoted by reference numerals 117UL, 117UR, 1
17LL, 119UL, 119UR, and 119LL will be described below.

As a representative example of the offset correction circuit in the first channel, the subtraction circuit 117UL subtracts the pixel signal PVUL of the first channel from the pixel signal PVLR of the fourth channel, and the signal HVUL of the operation result is averaged. Supply to the hold circuit 118UL. The average value holding circuit 118UL adds and averages the signal HVUL generated during the period TAV during which all the pixel charges of the pixel group in the reference area 3 are read, and outputs the result as an average signal AVUL. This period TAV
After the lapse of the period, the period TRD for reading out the pixel charges of the photosensitive portion 101
During the addition, the addition circuit 119UL adds the average value signal AVUL and the pixel signal PVUL to remove an offset component in the pixel signal PVUL. The pixel signal RUL obtained as a result of the addition is converted into digital pixel data DUL by the A / D converter 120UL, and
4 is stored.

The same offset correction circuit is provided also for the remaining channels, and it is possible to correct the variation in the offset characteristics between the respective channels based on the pixel signal PVLR of the fourth channel.

(Seventh Embodiment) Next, a seventh embodiment will be described. The configuration of the apparatus of this embodiment is the same as that of the third embodiment shown in FIG. 12, and will be described with reference to FIG.

The difference between this embodiment and the third embodiment will be described. In the correction circuit 12 of the third embodiment, the first to the first reference voltages are based on a constant reference voltage Vref output from the reference voltage generation circuit 200. The characteristic variation between channels is made uniform by correcting the gain variation among all the output mechanisms of the third channel. In this embodiment, however, the offset level variation between the output mechanisms is corrected. Correction circuit is provided.

The configuration of the offset characteristic correction circuit of this embodiment will be described with reference to FIG. This offset correction circuit is provided instead of the gain correction circuit of the third embodiment cascaded with the subtraction circuits 16a to 16c of each channel included in the double sample hold circuit. Then, the division circuits 217a, 217b, 217c provided in the third embodiment
Are multiplication circuits 219a, 219b, 219 provided in the third embodiment instead of the subtraction circuit in the present embodiment.
c is replaced by an adding circuit in the present embodiment. The subtraction circuit and the addition circuit are denoted by reference numerals 217a, 217b, and 217.
c, 219a, 219b, and 219c.

All the offset correction circuits have the same configuration and electrical time characteristics. The offset correction circuit of the first channel will be described as a representative. Subtraction circuit 217a
Is the reference voltage V output from the reference voltage generation circuit 200.
The pixel signal PVa of the first channel is subtracted from ref, and a signal HVa = (Vref · PVa) as a result of the operation is subtracted.
Is supplied to the average value holding circuit 218a. The average value holding circuit 218a outputs a signal HVa generated during the period TAV during which all pixel charges of the pixel group in the reference region 3 are read.
Are added and averaged and output as an average signal AVa. After the elapse of this period TAV, during the period TRD for reading out the pixel charges of the photosensitive section 1, the adding circuit 219a outputs the average value signal AV.
The offset component in the pixel signal PVa is removed by adding a to the pixel signal PVa. Then, the pixel signal Ra obtained as a result of the addition is output to the A / D converter 20a.
Is converted into digital pixel data Da and stored in the frame memory 14.

Note that the subtraction circuit 216 during the period TAV is used.
If the pixel signals sequentially output from a, 216b, and 216c are PVa (k), PVb (k), and PVc (k), the CCD solid-state imaging device having three channels shown in FIG. Since the number of pixel charges K output from each channel per period is K = m / 3, 1 ≦ k ≦
m / 3, and the average value signals AVa, AVb and A
Vc is given by the following equation.

[0097]

(Equation 10)

Further, when the reference area 3 includes a pixel group of N rows, the following equation is obtained.

[0099]

[Equation 11]

Then, the average value signals AVa, AVb and AV
signal Ra output during a period TRD after c is determined
(K), Rb (k), and Rc (k) are represented by the following equations.

[0101]

(Equation 12)

As is evident from these equations (22) to (30), variations in offset characteristics between channels are corrected. (Eighth Embodiment) Next, an eighth embodiment will be described. still,
The configuration of this embodiment is the same as that of the fourth embodiment shown in FIG. 13, and will be described with reference to FIG.

The difference between the present embodiment and the fourth embodiment will be described. The correction circuit of the fourth embodiment compensates for the variation in gain between the output mechanisms to make the variation in characteristics between channels uniform. In this embodiment,
A correction circuit is provided for correcting a variation in the offset level with respect to the reference voltage Vref between the output mechanisms.

The configuration of the offset correction circuit of this embodiment will be described with reference to FIG.

This offset correction circuit is provided in place of the gain correction circuit of the fourth embodiment cascaded to the subtraction circuit 116UL of each channel included in the double sample hold circuit. In the present embodiment, the division circuit 117UL provided in the fourth embodiment is replaced with a subtraction circuit, and the multiplication circuit 119UL provided in the fourth embodiment is replaced by a subtraction circuit.
Is replaced by an adder circuit in this embodiment. The subtraction circuit and the addition circuit are denoted by 117UL, 117UR, 11
7LL, 117LR, 119UL, 119UR, 119
LL and 119LR will be described below.

As a representative example of the offset correction circuit in the first channel, the subtraction circuit 117UL subtracts the pixel signal PVUL of the first channel from the voltage Vref output from the reference voltage generation circuit, and a signal HVUL of the operation result is obtained. Is supplied to the average value holding circuit 118UL. The average value holding circuit 118UL adds and averages the signals HVUL generated during the period TAV during which all the pixel charges of the pixel group in the reference region 3 are read out, and outputs the result as an average value signal AVUL. After the elapse of this period TAV, the photosensitive unit 101
During the period TRD for reading out the pixel charges of the adder 119,
UL removes the offset component in the pixel signal PVUL by adding the average value signal AVUL and the pixel signal PVUL. Then, the pixel signal RUL obtained as a result of the addition is converted into digital pixel data DUL by the A / D converter 120UL and stored in the frame memory 14.

The same offset correction circuit is provided also for the remaining channels, and it is possible to correct the variation of the offset characteristics between the channels with reference to the reference voltage Vref.

As described above, the above apparatus relates to a multi-channel CCD solid-state imaging device that reads out signal charges generated in a photosensitive section through a plurality of output channels.
In particular, a signal correction circuit is provided for removing characteristic variations of signals output from each channel.

The conventional technology will be described. In recent years, in the field of measurement technology, light emitted from an object to be measured, etc.
A measurement system that receives a CD solid-state imaging device and analyzes and processes the output signal as image information has become widespread. In order to further improve the measurement accuracy, the resolution, frame rate, and sensitivity of the CCD solid-state imaging device have been increased. There is a growing demand for such applications.

In response to these demands, in particular, a high resolution and a large number of pixels have been achieved in order to increase the amount of information obtained from the object to be measured. However, if the readout speed of the signal charges is relatively slow with the increase in the number of pixels, the object of increasing the frame rate cannot be achieved. Therefore, a plurality of horizontal shift registers (also referred to as horizontal charge transfer paths) for signal reading are provided in parallel with the photosensitive section, and the signal charges are read out in parallel by the plurality of horizontal shift registers, so that the reading speed of the signal charges is reduced. Improvements have been made.

That is, since each horizontal shift register serially transfers the signal charges for one horizontal line transferred from the vertical charge transfer path of the photosensitive portion, the reading speed of the signal charges is naturally limited. By reading signal charges in parallel by a plurality of horizontal shift registers, high-speed reading becomes possible, and it is possible to sufficiently cope with an increase in the number of pixels.

However, when a plurality of horizontal shift registers are provided to increase the number of channels, the variation in the characteristics of each horizontal shift register and the variation in the characteristics of the output mechanism connected to the end of each horizontal shift register are caused. Due to the adverse effects, the characteristics of the signals output from the respective channels also vary.

That is, in a conventional CCD solid-state image pickup device for reading out signal charges generated in a photosensitive portion through one horizontal shift register and an output mechanism provided therein, such a problem occurs. On the other hand, if there is a configuration in which signal charges are read out through a plurality of horizontal shift registers, the horizontal shift registers and their output mechanisms will have characteristic variations among each other.

In particular, characteristic variations among output mechanisms include noise variation including gain variation and offset, and noise variation including offset.
If there are variations in temperature characteristics, etc., and the signals output from each channel are adversely affected by these effects, false colors, vertical stripe-like pseudo patterns, moiré, degradation in resolution, etc. will occur in the reproduced image, Will be greatly deteriorated.

In particular, the main factor of the gain variation is caused by the structure and operation of the output mechanism formed at the end of the horizontal shift register of each channel.

As a correction technique for solving such a problem of the multi-channel CCD solid-state imaging device, Japanese Patent Application Laid-Open Nos. Hei 1-305672 and Hei 1-1114174 are disclosed.
However, there are the following problems because all of them apply feedback control.

According to the former correction technique, two (two-channel) horizontal shift registers are formed for the photosensitive section, and a variable gain preamplifier circuit is connected to the output mechanism of each horizontal shift register. Further, a drain diode for injecting a charge into each horizontal shift register is provided. Then, during the vertical blanking period, a constant charge is injected into each horizontal shift register via the drain diode, and at that time, the difference between the output signals read from each variable gain preamplifier circuit is obtained, and the difference is zero. The gain of each variable gain preamplifier circuit is feedback-controlled so that Therefore, when the signal charge of the photosensitive section is read out after the elapse of the vertical blanking period, the variation in gain between channels is corrected, and a pixel signal without variation can be obtained.

However, according to this technique, the time constant of the feedback control circuit can be fixed for a multi-channel CCD solid-state imaging device that performs imaging in synchronization with a predetermined timing conforming to the standard television system. Although it is effective, in the measurement technology field, it is necessary to set an arbitrary exposure time or an arbitrary pixel signal readout period for imaging, so that it is extremely difficult to arbitrarily set the time constant of the feedback control circuit. There is a problem.

In the latter correction technique, two (two-channel) horizontal shift registers are formed for the photosensitive section, and a variable gain preamplifier circuit is connected to the output mechanism of each horizontal shift register. ing. Then, the gain variation of each output mechanism is detected from the difference between the pixel signals obtained from each channel when the white chart is imaged, and the gain of each variable gain preamplifier circuit is fed back so that the gain variation becomes zero. Control. This technique also has the same problem as the former technique.

Further, a high-sensitivity CCD solid-state used in an emission microscope or the like for destructively detecting weak light generated when an abnormality occurs in an internal circuit of a semiconductor device such as an IC, LSI, or VLSI from the outside of the package. In an imaging device, in order to obtain optimal imaging conditions, it is necessary to variably set the exposure time or arbitrarily set the frame rate in an extremely wide range according to the emission intensity of the measurement target. Therefore, the conventional feedback control cannot be applied.

For example, exposure is performed for a long time (for example, one hour) by a CCD solid-state imaging device, whereby signal charges corresponding to one frame image accumulated in each pixel of the photosensitive portion are read out at a predetermined pixel rate, and the next imaging operation is performed. For a short time (eg 1
Second) It is difficult to apply the prior art to a usage mode such as exposing and reading out signal charges at a predetermined pixel rate.
If the time constant of the conventional feedback control circuit is forcibly reduced, the feedback control system becomes unstable, and the oscillation phenomenon and the correction characteristics for each channel fluctuate, resulting in variations in characteristics between channels. Will be done.

On the other hand, the apparatus of the above embodiment can suppress the characteristic variation between channels without applying the conventional feedback control.
It has a correction circuit for the D solid-state imaging device.

The apparatus of the above embodiment includes a gain correction circuit that corrects a variation in gain between channels, and an offset correction circuit that corrects a variation in offset between channels.

In a CCD solid-state imaging device having the above-described gain correction circuit, a multi-channel type in which pixel charges generated in a photosensitive portion are read out in parallel via a plurality of horizontal shift registers provided on a plurality of channels and an output mechanism. In a CCD solid-state imaging device, a pixel group for one or more horizontal lines existing in the photosensitive section is shielded or a structure that is not affected by external light allows only a certain amount of pixel charges to be stored in the pixel group. The reference region to be generated, and the pixel signal of each channel obtained by reading out the pixel charges generated in the reference region in parallel via the horizontal shift register and the output mechanism of the plurality of channels, the pixel signal of the specific channel. A division circuit for dividing a pixel signal of another channel based on a reference, and a division for each channel output from the division circuit An average value holding circuit that outputs an average value signal having a correlation with a gain variation between channels by adding and averaging the result signals, and an average value signal of each channel output from the average value holding circuit. A multiplication circuit that multiplies a pixel signal of each channel read from the photosensitive unit excluding the reference area, and outputs a signal of the multiplication result as a corrected pixel signal;
Was provided.

In a CCD solid-state imaging device having another gain correction circuit, a pixel group for one or more horizontal lines in the photosensitive portion is shielded from light or is affected by external light. Each structure is obtained by reading the pixel charges generated in the reference region in parallel through the horizontal shift register and the output mechanism of the plurality of channels in parallel with the reference region that generates only a fixed pixel charge in the pixel group. A pixel circuit of a channel is divided by a predetermined reference voltage as a reference, and a signal of a result of division for each channel output from the divider is averaged to obtain a gain variation between the channels. An average hold circuit that outputs an average signal having a correlation,
The average value signal of each channel output from the average value holding circuit is multiplied by the pixel signal of each channel read from the photosensitive unit excluding the reference area, and a signal of the multiplication result is used as a corrected pixel signal. And a multiplying circuit for outputting.

On the other hand, a CCD having an offset correction circuit
In a solid-state imaging device, in a multi-channel CCD solid-state imaging device that reads pixel charges generated in a photosensitive portion in parallel via a plurality of horizontal shift registers provided in a plurality of channels and an output mechanism, 1 in
Or a light-shielding pixel group for two or more horizontal lines, or a structure that is not affected by external light, so that a reference region that generates only a fixed pixel charge in the pixel group, and a horizontal shift register of the plurality of channels. A subtraction circuit for subtracting pixel signals of other channels with respect to pixel signals of the specific channel from pixel signals of the respective channels obtained by reading pixel charges generated in the reference area in parallel via an output mechanism. An average value holding circuit that outputs an average signal having a correlation with the offset characteristic variation between channels by adding and averaging the signals of the subtraction results for each channel output from the subtraction circuit; The average value signal of each channel output from the average value hold circuit and the signal read from the photosensitive section excluding the reference area. By adding the pixel signals of each channel to be, has a configuration that includes an adding circuit and outputting the addition result as the pixel signal after the correction, the.

In addition, C provided with another offset correction circuit
In a CD solid-state imaging device, a pixel group for one or more horizontal lines in the photosensitive section is shielded, or the pixel group has a structure that is not affected by external light. Through a reference region that generates only pixel charges, the horizontal shift register of the plurality of channels, and an output mechanism,
A subtraction circuit for subtracting a pixel signal of each channel obtained by reading pixel charges generated in the reference area in parallel with reference to a predetermined reference voltage, and a subtraction result for each channel output from the subtraction circuit And an average value holding circuit that outputs an average value signal having a correlation with the offset characteristic variation between channels with respect to a reference voltage by adding and averaging the reference signals, and the average value of each channel output from the average value holding circuit. An addition circuit for adding the signal and the pixel signal of each channel read from the photosensitive unit excluding the reference area, and outputting the addition result as a corrected pixel signal.

According to the apparatus provided with the gain correction circuit, the pixel charge generated in the pixel group in the reference area is read before the pixel charge generated in the pixel group of the photosensitive section by imaging the object to be measured is read out. Is read out via the horizontal shift register and output mechanism of each channel. That is, they are allocated to each channel and read in parallel. The pixel signals output in this manner are supplied to the division circuit, and the division circuit divides the pixel signals of the remaining channels based on the pixel signals of the predetermined channel. As a result, the division result indicates a gain variation for each channel with respect to the pixel signal of the predetermined channel. The average hold circuit adds and averages the signals indicating the gain variation to generate an average signal indicating the final gain variation of each channel. Then, the multiplying circuit multiplies the pixel signal of each channel generated by reading out the pixel charges generated in the pixel group of the photosensitive section by imaging the object to be measured with the average signal.
Therefore, by using the multiplied signal as the corrected pixel signal, it is possible to eliminate the gain variation between the channels.

Further, even if the division circuit divides pixel signals of all channels with reference to a predetermined reference voltage output from the reference voltage generation circuit, a signal indicating a gain variation for each channel is obtained. Can be Then, the average value holding circuit adds and averages the signals indicating the gain variations to obtain an average value signal indicating the final gain variations of the respective channels. By multiplying the pixel signal of each channel generated by reading out the pixel charge generated in the pixel group of the photosensitive unit by imaging the target by the average value signal, the gain variation between the channels is reduced. The removed pixel signal can be obtained.

Further, according to the apparatus provided with the offset correction circuit, before reading out the pixel charge generated in the pixel group of the photosensitive portion by imaging the object to be measured, the pixel charge generated in the pixel group in the reference area is read out. The pixel charges are read out via the horizontal shift register and output mechanism of each channel. That is,
It is allocated to each channel and read in parallel. The pixel signal output in this way is supplied to the subtraction circuit,
Such a subtraction circuit subtracts pixel signals of the remaining channels with reference to pixel signals of a predetermined channel. As a result, the subtraction result indicates a variation in the offset characteristic of each channel with respect to the pixel signal of the predetermined channel. The average hold circuit adds and averages the signals indicating the variation of the offset characteristics to generate an average signal indicating the final variation of the offset characteristics of each channel. Then, the addition circuit adds the average signal to the pixel signal of each channel generated by reading out the pixel charges generated in the pixel group of the photosensitive unit by imaging the object to be measured. Therefore, by using the added signal as the corrected pixel signal, it is possible to eliminate the variation in the offset characteristics between the channels.

Since these correction circuits are feedforward circuits, there are problems with the feedback circuit,
That is, complicated and difficult problems such as adjusting the feedback time constant are solved.

In the subtraction circuit, a predetermined reference voltage output from the reference voltage generation circuit is used as a reference.
Even if the pixel signals of all the channels are subtracted, a signal indicating the offset characteristic variation of each channel can be obtained. Then, the average value holding circuit adds and averages the signals indicating the offset variations to obtain an average value signal indicating the final offset variation of each channel. By adding the average value signal to the pixel signal of each channel generated by reading out the pixel charge generated in the pixel group of the photosensitive unit by imaging the measurement target, the offset variation between the channels is obtained. Can be obtained.

As described above, according to the apparatus provided with the gain correction circuit, the pixel charges of the photosensitive section are read out in parallel by a plurality of channels by providing a plurality of horizontal shift registers and a plurality of output mechanisms provided therein. CC to do
In the D solid-state imaging device, a reference area is provided at a specific position of the photosensitive unit, and pixel charges generated in a pixel group in the reference area are read out for each channel, and based on pixel signals read out from the specific channel. The ratio to the pixel signals of the remaining channels is obtained by a division operation, and the amplitude of the pixel signals of each channel is automatically corrected based on the average value of the division operation results until all the pixel charges in the reference area are read out. Therefore, it is possible to correct the variation in the gain characteristics between the channels. Further, since the gain correction circuit is a feedforward correction circuit, the difficulty of setting the feedback time constant, which is a problem in the conventional feedback correction circuit, is solved.

According to the device provided with the offset correction circuit, the CCD solid-state image pickup device, which includes a plurality of horizontal shift registers and a plurality of output mechanisms provided therein, reads out the pixel charges of the photosensitive portion in a plurality of channels in parallel. A reference area is provided at a specific position of the photosensitive section, pixel charges generated in a pixel group in the reference area are read out for each channel, and pixel signals of the remaining channels are read based on pixel signals read out from the specific channel. And the offset component of the pixel signal of each channel is automatically removed based on the average value of the subtraction results until all the pixel charges in the reference area are read out. Variations in offset characteristics between each other can be corrected. Further, since the offset correction circuit is also a feedforward correction circuit, the difficulty of setting the feedback time constant, which has been a problem in the conventional feedback correction circuit, is solved.

[0135]

According to the present invention, it is possible to provide a CCD solid-state imaging device that performs high-sensitivity imaging.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a device configuration of a first embodiment or a fifth embodiment.

FIG. 2 is an explanatory diagram showing a structure of an output mechanism.

FIG. 3 is a timing chart for explaining the operation of the output mechanism.

FIG. 4 is a block diagram illustrating a configuration of a correction circuit included in FIG. 1;

FIG. 5 is a circuit diagram showing an example of an average value hold circuit in the correction circuit.

FIG. 6 is an explanatory diagram for explaining a pixel charge reading operation in the first embodiment.

FIG. 7 is a waveform chart for explaining the operation of the correction circuit in the first embodiment.

FIG. 8 is a waveform chart for explaining a problem in the case where the correction circuit is not provided in the first embodiment.

FIG. 9 is a block diagram showing a device configuration of the second embodiment or the sixth embodiment.

FIG. 10 is a block diagram illustrating a configuration of a correction circuit included in FIG. 9;

FIG. 11 is an explanatory diagram for explaining a pixel charge readout operation in the second embodiment.

FIG. 12 is a block diagram showing an apparatus configuration of a third embodiment.

FIG. 13 is a block diagram showing a device configuration of a fourth embodiment.

[Explanation of symbols]

1, 101: photosensitive section, 3, 103UL, 103UR, 103
LL, 103LR: Reference area, 5a, 5b, 5c, 105U
L, 105UR, 105LL, 105LR ... horizontal shift registers, 6a, 6b, 6c, 106UL, 106UR, 106L
L, 106LR: output mechanism, 13: correction circuit, 17a, 1
7b, 117UL, 117UR, 117LL, 117LR ... Division circuit (or subtraction circuit), 18a, 18b, 118UL, 1
18UR, 118LL: average value hold circuit, 19a, 19
b, 119UL, 119UR, 119LL ... multiplication circuit (or addition circuit), 217UL, 217UR, 217LL, 217LR ...
Divider circuit, 218UL, 218UR, 218LL, 218LR ...
Average value hold circuit, 219UL, 219UR, 219LL,
219LR: Multiplication circuit, 200: Reference voltage generation circuit, 31
7UL, 317UR, 317LL, 317LR ... Division circuit, 31
8UL, 318UR, 318LL, 318LR: average value hold circuit; 319UL, 319UR, 319LL, 319LR: multiplier circuit; 300: reference voltage generation circuit.

Claims (2)

[Claims] 1. A CCD solid-state imaging device capable of switching imaging conditions, wherein the imaging condition includes a reading speed of pixel charges generated in a photosensitive section. 2. The CCD solid-state imaging device according to claim 1, wherein the imaging condition includes an exposure time.