JP2000069280A - Image signal generating device, its method, pixel interpolation device, its method and storage medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a magnified/reduced image of high image quality. SOLUTION: Data to be displayed are written in a memory 22, read start position, read range and read speed are set in an address generating circuit 32 via a command decoder 30. A magnification/reduction rate is set in a magnification/reduction rate circuit 24 via the command decoder 30. A time interval for interrupt is set at a timer on the inside of a CPU 10 for magnification/reduction as a time elapses and the CPU 10 goes into a waiting state of timer interrupt. When a setting time elapses and timer interrupt takes place, first a read start position, a read range and a read speed of the address generating circuit 32 are updated via the command decoder 30 to update the magnification/reduction rate of the magnification/reduction circuit 24. The timer interrupt is repeated until desired final magnification is obtd.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image signal forming apparatus and method, a pixel interpolating apparatus and method, and a storage medium, and more specifically, to an image signal for forming an image signal for displaying image data on a display. The present invention relates to a forming apparatus and method, a pixel interpolating apparatus and method for enlarging and reducing an image, and a storage medium for storing program software for executing these methods.

[0002]

2. Description of the Related Art Recent advances in semiconductor technology have made it possible to create two-dimensional or three-dimensional images in real time and display them on a display. Such an image display technique is used in, for example, a CAD or a game.

An image signal forming apparatus for forming an image signal to be applied to a display generally includes a video memory,
It has a D / A converter and a synchronization signal generator. This image signal forming apparatus is provided inside a personal computer or a game machine, and raster-scans image data written into a video memory by a CPU in accordance with a clock generated by a synchronization signal generator, and provides a D / A converter. Is converted into an analog image signal and applied to an external display.

[0004] As another type of image signal forming device, many devices equipped with a so-called accelerator for writing pixel data corresponding to a video memory in accordance with a command instructing a predetermined operation such as drawing a straight line have been put into practical use. At the same time, high-speed drawing is enabled by hardware, and the load on the CPU can be reduced, so that the performance of the entire system can be improved.

[0005] Further, a 3D accelerator has been put to practical use in which functions such as polygon drawing and texture mapping, which are often used when drawing a three-dimensional image, are added to such an accelerator.

[0006] Recent advances in digital signal processing technology have brought great developments in the video field. Digital image input devices such as image scanners, digital video cameras and digital still cameras have become readily available and available, and the performance of personal computers has been significantly improved. This allows
It has become easy to edit and process image data on a personal computer, and it has become possible to perform the processing with high image quality.

[0007] Under such circumstances, it is presumed that a technique for the image pickup apparatus itself to enlarge or reduce an image in real time will be important in the future. Conventional digital video cameras are equipped with an optical zoom device and an electronic zoom device for interpolating and enlarging a captured image, and use the electronic zoom when enlarging the image beyond zooming by an optical system. Of course, electronic zoom-out for electronically reducing a captured image is also possible.

When there is continuous image data sampled at a certain frequency and the image data is linearly interpolated at a sampling interval of another frequency, the original sampled pixel data located before and after the interpolated pixel and the interpolated pixel are interpolated. Is required relative time data k. As a method of continuously obtaining this, US Pat.
A configuration using a memory reading unit using an accumulator as shown in the specification of Japanese Patent No. 81 is known.

FIG. 9 is a conceptual diagram of linear interpolation. S_n,
S_n-1Is adjacent pixel data on the same line, and S 'is
Pixel S_n, S_n-1Pixel data to be interpolated by
Shown respectively. At this time, S_n, S_n-1, S '
Is S '= S_n・ K + S_n-1-It is represented by (1-k). If this is realized by a digital circuit,
This equation is modified to reduce the number of multipliers, and S ′ = (S_n-S_n-1) ・ K + S_n-1  And

FIG. 10 is a block diagram showing a schematic configuration of a horizontal portion of a conventional linear interpolation device. Field memory 2
Image data S having a predetermined sampling frequency (for example, a sampling frequency determined by an image sensor) is input to the input terminal 120 from the input terminal 120, and one field is stored. Memory read circuit 216 continuously determine the interpolated pixel position in accordance with the zoom ratio setting value zoom from the zoom ratio input terminal 214, pixel data S _n immediately after the interpolation pixel position of the original image data in the field memory 212
Is supplied to the field memory 212 so as to output the read control signal Cr.

The zoom ratio setting value zoom is obtained by setting the zoom ratio R to R = 256 / (25) when the zoom resolution is 8 bits.
6 + zoom). If zoom takes a positive integer value, the image is reduced, and if it takes a negative integer value, the image is enlarged.

The coefficient generation circuit 220 is connected to the update control terminal 21
8 according to the update control signal inc from
The absolute value of oom is cumulatively added to calculate a coefficient k indicating the distance between the original sampling pixel position and the interpolation pixel position, and output to the linear interpolation circuit 222. The coefficient generation circuit 220 also
When carry occurs in the process of accumulating the coefficient k, ho
The ld signal is supplied to the field memory 212 and the delay circuit 22.
4 is applied.

FIG. 11 shows a schematic block diagram of the coefficient generation circuit 220. The absolute value circuit 230 has an input terminal 214
From the zoom ratio setting value zoom from
32. The output of the adder 232 is the delay circuit 234
Is applied to the adder 232 through the accumulator. The delay circuit 234 outputs the held value in response to the rise of the update control signal inc from the update control terminal 218, and takes in the output of the adder 232. Delay circuit 234
Is the coefficient k and is applied to the linear interpolation circuit 222. When a carry occurs due to the addition result, the adder 232 supplies the carry to the memory 212 and the delay circuit 224 as a hold signal.

[0014] field memory 212 reads the pixel data _{S n} instructed by the read control signal Cr from the memory read circuit 216. Pixel data _{S n} read from the memory 212 is applied to the linear interpolation circuit 222 and the delay circuit 224. The delay circuit 224 supplies the pixel data _{S n-1} obtained by delaying the pixel data _{S n} by one clock of the original sampling frequency to the linear interpolation circuit 222. As a result, the pixel data _Sn and _Sn-1 are simultaneously input to the linear interpolation circuit 222.

The linear interpolation circuit 222 calculates S_n-S_n-1To
The subtractor 236 to be calculated and the output of the subtractor 236 (S_n-S
_n-1) Is multiplied by a coefficient, and a multiplier 238
38 output (S_n-S_n-1) · K for S_n-1Add
S ′ = (S_n-S_n-1) ・ K + S_n-1  Is output.

When receiving the hold signal from the coefficient generation circuit 220, the field memory 212 repeatedly outputs the pixel data specified by the immediately preceding read control signal Cr.

The delay circuit 224 includes, as shown in FIG.
It comprises a selector 242 and a delay element 244 for one clock. The selector 242 normally selects data input from the memory 212 and selects output data of the delay element 244 according to the hold signal. The delay element 244
The data selected by the selector 242 is delayed by one clock and fed back to the selector 242. The output of the delay element 244 is supplied to the linear interpolation circuit 222. With this configuration, the delay circuit 224 repeatedly outputs the same data (data held in the delay element 244) when the hold signal is applied.

[0018]

The prior art has the following problems. That is, there is a case where a natural image or a multi-valued image is to be displayed in an enlarged or reduced manner. In that case, in the conventional example, the CPU creates an image enlarged or reduced to a desired size from the original image data, and writes the obtained image data to the video memory. In this method, if an attempt is made to obtain a high-quality image using an algorithm with less image quality degradation that occurs during enlargement or reduction, the amount of calculation becomes enormous,
Frames drop when changing continuously, or cannot be processed in real time.

Further, in the conventional linear interpolation using two adjacent pixels, although the circuit configuration is simplified, the frequency characteristic is not as shown in FIG.
As shown in FIG. Therefore, the obtained image has a flat feeling without sharpness.

An object of the present invention is to provide an image signal forming apparatus and method, an image interpolating apparatus and method, and a storage medium which solve such problems.

It is another object of the present invention to provide an image signal forming apparatus and method, an image interpolating apparatus and method, and a storage medium capable of forming a high-quality image at high speed with little deterioration in image quality when the image is enlarged or reduced. I do.

[0022]

According to the present invention, there is provided an image signal forming apparatus comprising: an image memory for storing image data; and image data read from the image memory in at least one of a horizontal direction and a vertical direction. 4 adjacent in one direction
The image processing apparatus includes image processing means for performing scaling by interpolating pixel data of points or more, and output means for generating an image signal from an output of the image processing means.

The image signal forming apparatus according to the present invention further comprises a first image memory for holding partial data of an image, and image data read from the first image memory in at least one of a horizontal direction and a vertical direction. Image processing means for interpolating and scaling the pixel data of four or more points adjacent in one direction in the direction, a second image memory for holding the output of the image processing means and other partial data of the image, Output means for generating an image signal from the output of the second image memory.

In the image signal forming method according to the present invention, a storing step of storing image data in an image memory; and storing the image data read from the image memory in at least one of a horizontal direction and a vertical direction. And an output step of generating an image signal from the processing result of the image processing step.

In the image signal forming method according to the present invention, a first storing step of storing a part of the image data in a first image memory, and storing the image data read from the first image memory in a horizontal direction and a vertical direction. An image processing step of interpolating and scaling at least in one direction from pixel data of four or more points adjacent to the one direction, and storing the image in a second image memory for storing other partial data of the image A second storage step of storing a processing result of the processing step; and an output step of generating an image signal from an output of the second image memory.

The storage medium according to the present invention stores program software for executing the above-described image signal forming method.

The image interpolation apparatus according to the present invention stores image data, and stores two pixel signals _Sn , _{Sn-1 on} one side and two pixel signals Sn on the other side with respect to an interpolation pixel S '.
image memory means for outputting _n-2 and _Sn-3 , and the pixel position of the interpolated pixel signal S 'between the pixel position of the pixel signal _{Sn-1 and} the pixel position of the pixel signal _Sn-2 First coefficient generation means for generating an interpolation coefficient k indicating the following, multiplication means for calculating the square and the third power of the interpolation coefficient k, k, k ² ,
The pixel signal from the ^{_{k 3 S n, S n-}} 1, S n-2 and interpolation for the pixel signals _{S n-3} coefficients _{k 0, k 1, k 2} , k
₃ and the second coefficient generating means for generating a, the pixel signals _{S n, S n-1,} S n-2 and _{S n-3} in the interpolation coefficient _{k 0, k 1, k 2} , k 3 multiplied, Calculating means for calculating the sum and outputting the interpolated pixel signal S ′.

The image interpolating apparatus according to the present invention stores image data, and stores two pixel signals _Sn , _{Sn-1 on} one side and two pixel signals Sn on the other side with respect to an interpolated pixel S '.
image memory means for outputting _n-2 and _Sn-3 , and the pixel position of the interpolated pixel signal S 'between the pixel position of the pixel signal _{Sn-1 and} the pixel position of the pixel signal _Sn-2 First coefficient generating means for generating an interpolation coefficient k indicating the following, multiplication means for calculating the square of the interpolation coefficient k and (k-1) and (k-1) ² , k, k ² , (1 -K) and (1-k) ²
A second coefficient generating means for generating interpolation coefficients k ₀ , k ₁ , k ₂ , and k ₃ for the pixel signals _Sn , _Sn-1 , _Sn-2 and the pixel signal _{Sn-3 from the} pixel signal, Signals S _n and S
_{n-1, S n-2} and _{S n-3} in the interpolation coefficient _{k 0, k 1,}
and a calculating means for multiplying k ₂ and k ₃ , calculating the sum, and outputting an interpolated pixel signal S ′.

According to the image interpolation method of the present invention, the image data
From the image memory means for storing the interpolation pixel S '
Two pixel signals S on one side_n, S_n-1And the other side
Two pixel signals S_n-2, S_n-3Pixel signal to output
Signal output step and the pixel signal S_n-1Pixel position and
The pixel signal S_n-2Interpolated pixel signal between pixel positions
A first relation for generating an interpolation coefficient k indicating the pixel position of the symbol S '
Calculate the number generation step and the square and cube of the interpolation coefficient k
Outgoing multiplication step and k, k², K³From the pixel signal
No. S_n, S_n-1, S_n-2And the pixel signal S_n-3To
Interpolation coefficient k ₀, K₁, K₂, K₃The second that produces
Coefficient generating step and the pixel signal S_n, S_n-1, S
_n-2And S_n-3To the interpolation coefficient k₀, K₁, K₂, K₃
To calculate the sum and output the interpolated pixel signal S '
And a calculating step.

The image interpolation method according to the present invention also includes an image memory means for storing image data, two pixel signals S _n on one side with respect to the interpolation pixel S _', the S _n-1 and the other side A pixel signal output step of outputting _two pixel signals _Sn-2 and _Sn-3 , and an interpolation pixel between a pixel position of the pixel signal _{Sn-1 and} a pixel position of the pixel signal _Sn-2. First to generate an interpolation coefficient k indicating a pixel position of the signal S ′
And a multiplication step for calculating the square of the interpolation coefficient k and (k-1) and (k-1) ² , and k, k ² , (1-k) and (1-k) ² From the pixel signals _Sn , Sn _{- 1} and _Sn-2 and the pixel signal _Sn-3.
A second coefficient generation step of generating interpolation coefficients k ₀ , k ₁ , k ₂ , and k ₃ for the pixel signals S _n ,
Interpolation coefficients k ₀ , S _n-1 , _Sn-2 and _Sn-3 are
an operation step of multiplying k ₁ , k ₂ , and k ₃ to calculate a sum and output an interpolated pixel signal S ′.

The storage medium according to the present invention stores program software for executing the above-described image interpolation method.

[0032]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a schematic block diagram of the first embodiment of the present invention. 10 is a CPU, 12 is a ROM, 14 is a RAM, 16 is a disk device, 18 is a data bus, 20
Is an address bus, 22 is a memory for holding display data,
24 is a scaling circuit for expanding or reducing the display data held in the memory 22 in real time, 26 is a scaling circuit 24
A digital-to-analog (D / A) converter for converting image data from an analog signal into an analog signal; 28, an RGB signal output terminal; 30, a command decoder; 32, an address generation circuit for generating a read address of the memory 22; A sync signal output circuit 36; a synchronizing signal SYNC output terminal 36; an output signal from the RGB output terminal 28 and the SYNC output terminal 36;
It is a display (hereinafter abbreviated as a monitor).

The CPU 10 has a ROM 12 or a RAM 14
According to the above program, the disk device 16 and the memory 2
2 and the command decoder 30 to write or read data. In the ROM 12, fixed programs and data necessary for system startup and programs for accessing each peripheral device are written. The RAM 14 holds programs and data loaded from the disk device 16. The disk device 16 stores an operating system, various application programs, and various data.

When displaying an image, an application program first writes image data to be displayed in the memory 22 in raster scan order. Next, the read start position, the read range, and the read speed are set in the address generation circuit 32 via the command decoder 30, and the enlargement / reduction ratio is set in the enlargement / reduction circuit 24.

The address generation circuit 32 generates an address for sequentially reading the set read range from the set read start position at the set read speed, and applies the generated address to the memory 22. As a result, the image data in the set read range is read from the memory 22 to the scaling circuit 24. The scaling circuit 24 is a memory 2
2 is enlarged or reduced in accordance with the enlargement / reduction ratio set by the command decoder 30, and output.

The scaled image data is converted into an analog signal by a D / A converter 26 and output to a monitor 38 from an RGB signal output terminal 28.

Further, the address generation circuit 32 outputs the SYNC
The timing signal is output to the generation circuit 34, and the SYNC generation circuit 34
Generate a signal. The SYNC signal is applied from a SYNC output terminal 36 to a monitor 38.

FIG. 2 shows an operation flowchart of this embodiment. The data to be displayed is written into the memory 22 (S
1) The read start position, read range, and read speed are set in the address generation circuit 32 via the command decoder 30 (S2). The enlargement / reduction ratio is set in the enlargement / reduction circuit 24 via the command decoder 30 (S3).
A time interval for scaling up and down with time is set for a timer interrupt inside the CPU 10 (S4), and a timer interrupt waiting state is entered (S5).

When the time set in S4 elapses, a timer interrupt occurs. First, the read start position, read range, and read speed of the address generation circuit 32 are updated via the command decoder 30 (S6), and the enlargement / reduction ratio of the enlargement / reduction circuit 24 is updated (S7).

It is determined whether or not the desired final magnification has been reached (S8). If the final magnification has been reached, the process ends. If the final magnification has not been reached, a timer interrupt wait is made again (S9), and S6 and S7 are repeated until the final magnification is reached by the timer interruption.

FIG. 3 is a schematic diagram showing an example of a display image according to the present embodiment. Reference numeral 40 denotes the entire image stored in the memory 22. The horizontal direction is the x axis, the vertical direction is the y axis, the upper left coordinate is (x0, y0), and the lower right coordinate is (x3, y3). It is assumed that a rectangular area (x1, y1) to (x2, y2) surrounding the human image 42 stored in the memory 40 is to be enlarged to the entire screen.

At first, a magnification of 1 is set in the enlargement / reduction circuit 24, and the image stored in the memory 22 is displayed as it is on the screen of the monitor 38 as shown by reference numeral 44, and the person image 42a is displayed. , The human image 4 stored in the memory 22
It is theoretically equal to 1 for 2.

Rectangular areas (x1, y1) to (x2, y2)
Is set in the enlargement / reduction circuit 24, the rectangular area (x1, y1) to (x2, y) of the memory 22 is displayed on the screen of the monitor 38, as indicated by reference numeral 46.
The image in 2) is enlarged and displayed on the full screen, and the human image 42 is also enlarged and displayed as indicated by reference numeral 42b. At this time, the final target read start position is (x
1, y1), and the reading range is x1 to x in the horizontal direction.
2. The vertical direction is set to y1 to y2. The reading speed is the reciprocal of the magnification. In other words, in the case of twice, the speed is ア ド レ ス, that is, the speed at which the address advances by only one pixel while the address normally advances by two pixels.

The read start position, read range, read speed, and enlargement / reduction ratio are changed at separately determined time intervals from the entire image stored in the memory 40 to the rectangular areas (x1, y1) to (x2, y2). By doing so, for example, it is possible to continuously change from the screen 44 to the screen 46.

FIG. 4 is a block diagram showing a schematic configuration of the enlargement / reduction circuit 24. 50 is a data input terminal to which data from the memory 22 is inputted, 52 is a synchronous pulse input terminal to which a synchronous pulse from the address generating circuit 32 is inputted, and 54 is a magnification input terminal to which the enlargement / reduction magnification k from the command decoder 30 is inputted. , 56 are clock input terminals to which a pixel clock from the address generation circuit 32 is input, and 58 is a horizontal pixel shift signal Ssh, a horizontal interpolation coefficient Sch, based on a synchronization pulse, a magnification and a clock input from the input terminals 52, 54, 56. Line shift signal Ssv and vertical interpolation coefficient S
The coefficient generation circuits 60, 62 and 64 for generating cv are one-pixel delay circuits for holding and shifting data in the horizontal direction according to the horizontal pixel shift signal Ssh, and 88, 90 and 92.
Is a one-line delay circuit for holding and shifting data in the line direction according to the line shift signal Ssv, 66, 7
2,78,84,94,100,106,112 are subtractors, 68,74,80,86,96,102,108,
114 is a multiplier, 70, 76, 82, 98, 104, 1
Reference numeral 10 denotes an adder, and 116 denotes an output terminal for outputting the enlarged or reduced data to the D / A converter 26.

Data input from data input terminal 50
Is divided by one pixel by the one-pixel delay circuits 60, 62 and 64.
Is delayed. Set the input of the delay circuit 60 to Sh_nNotation,
The outputs of the delay circuits 60, 62, 64 are S
h_n-1, Sh_n-2, Sh_n-3Notation. Subtractor
66 is Sh_nFrom Sh_n-3, And the multiplier 68 decreases
Output Sh of the arithmetic unit 66_n-Sh_n-3Coefficient generating circuit 58
Is multiplied by the horizontal interpolation coefficient Sch. The adder 70
The output of the multiplier 68 (Sh_n-Sh_n-3) × S for S
h _n-3Is added. The output of the adder 68 is Ph_nAnd notation
Then Ph_nIs represented by the following equation. That is, Ph_n= (Sh_n-Sh_n-3) × Sch + Sh_n-3  = Sh_n× Sch + (1-Sch) × Sh_n-3  Ph_nIs Sh_nAnd Sh_n-3Primary interpolation by Sch
Value.

The subtractor 72 has a function of Sh_n-1From Sh_n-2
And the multiplier 74 outputs the output Sh of the subtractor 72._n-1
-Sh_n-2Is multiplied by a horizontal interpolation coefficient Sch.
6 is the output of the multiplier 74 (Sh_n-1-Sh_n-2) × S
Sh to ch_n-2Is added. The output of the adder 76 is Ph
_n-1Notation, Ph_n-1Is represented by the following equation
You. That is, Ph_n-1= Sh_n-1× Sch + (1-Sch) × S
h_n-2  Ph_n-1Is Sh_n-1And Sh_n-2By Sch
It becomes the value obtained by primary interpolation.

The subtractor 78 calculates the value of Ph_n-1From Ph_nReduced
Calculate. The multiplier 86 squares the horizontal interpolation coefficient Sch,
The subtractor 84 outputs the output of the multiplier 86 from the horizontal interpolation coefficient Sch.
Sch²Is subtracted. The multiplier 80 outputs the output of the subtractor 78
Ph_n-1-Ph_nOutput Sch-Sch of the subtractor 84
², And the adder 82 outputs the output of the multiplier 80 (Ph
_n-1-Ph_n) × (Sch-Sch²) To adder 76
Output Ph_n-1Is added. The output of the adder 82 is
When expressed as o, Sho is represented by the following equation. That is, Sho = (Sch−Sch²) × Ph_n+ (1 + Sch
-Sch²) × Ph_{n -1}  Sho is Ph_nAnd Ph_n-1To (Sch-Sch²)
To obtain a value obtained by primary interpolation.

Next, the output Sho of the adder 82 is one line.
Delay lines 88, 90, and 92 one line at a time.
It is. Input of delay circuit 88 (that is, output of adder 82)
To Sv_nAnd the outputs of the delay circuits 88, 90, 92
Each Sv_n-1, Sv_{n -2}, Sv_n-3Notation
I will do it. The subtracter 94 outputs the output Sv of the adder 82. _n
To the output Sv of the delay circuit 92_n-3And a multiplier 9
6 is the output Sv of the subtractor 94_n-Sv_n-3Coefficient generation
The vertical interpolation coefficient Scv from the circuit 58 is multiplied.
The arithmetic unit 98 outputs the output (Sv_n-Sv_n-3)
× Scv to Scv _n-3Is added. Output of adder 98
(Sv_n-Sv_n-3) × Scv + Sv_{n -3}To Pv_n
Notation.

Further, the subtractor 100 calculates Sv _n−1 to S
v the _n-2 subtracted, multiplier 102, multiplied by the vertical interpolation coefficient Scv output _Sv n-1 _{-Sv n-2} of the subtracter 100, the adder 104, the output of the multiplier 102 _{(Sv n- 1}
−Sv _n−2 ) × Scv and Sv _n−2 . The output of the adder 104 will be denoted as Pvn-1.

The subtracter 106 outputs the output Pv of the adder 104
_n-1From the output Pv of the adder 98_nIs subtracted. Multiplier
114 squares the vertical interpolation coefficient Scv,
Is the output Scv of the multiplier 114 from the vertical interpolation coefficient Scv.²
Is subtracted. The multiplier 108 outputs the output Pv of the subtractor 106
_n-1-Pv_nThe output Scv-Scv of the subtractor 112 ²
, And the adder 110 outputs the output (Pv
_n-1-Pv_n) × (Scv−Scv)²) To adder 10
Output Pv of 4_n-1Is added. The output of adder 110 is
The signal So expanded or reduced in the horizontal and vertical directions.
Applied from the output terminal 116 to the A / D converter 26.
You.

FIG. 5 is a diagram showing the relationship between the horizontal interpolation coefficient Sch generated by the coefficient generation circuit 58 and the horizontal pixel shift signal Ssh. The enlargement / reduction circuit 24 includes a magnification input terminal 154.
The position of the pixel Sho at a certain time t1 is input to the input terminal 50 in accordance with the data Si input according to the scaling factor k.
When the pixel value is between the pixel Sh _n-1 and the pixel Sh _n-2 , the data value of the pixel Sh
Interpolated from two pixels. The coefficient generation circuit 58 calculates S
The distance from ho to Sh _n-2 is calculated from Sh _n-1 to Sh _n-2.
The value obtained by dividing the distance up to _n-2 is defined as a horizontal interpolation coefficient Sch. That is, Sch = (Sh _n−2 −Sh) / (Sh _n−2 −Sh)
_n-1 ).

At the next time t2, the pixel Sho becomes the pixel Sh.
_n-2 and Sh _n-3 . In this case, the coefficient generation circuit 58 generates a horizontal pixel shift signal Ssh,
h _{n -1,} shifting _{Sh n-2} and _{Sh n-3.} S
For h _n, by reading from the memory 22 by the address generated from the address generating circuit 32 the data of the next pixel are shifted in the same manner.

At the next time t3, the pixel Sho becomes:
Since it is located between Sh _n−2 and Sh _n−3 as in t2, the coefficient generation circuit 58 does not generate the horizontal shift signal Ssh at this time.

The coefficient generating circuit 58 generates the horizontal interpolation coefficient Sch and the horizontal shift signal Ssh in this manner, and according to these, Sh _n , Sh _n−1 , Sh _n−2 and Sh _n−2.
Data Sho is interpolated from the _n-3 data.

Since the operation is basically the same in the vertical direction, detailed description is omitted. Sv _n, S
Output data So is interpolated from the four data vn _-1 , Svn _-2 , and Svn _-3 according to the vertical interpolation coefficient Scv.

FIG. 6 is a schematic block diagram of a second embodiment of the present invention. The same components as those in FIG. 1 are denoted by the same reference numerals.

Reference numeral 120 denotes a memory for storing an image before scaling, 122 a memory for storing image data after scaling, and 124 an address generation circuit for generating a read address of the memory 120 and a write address of the memory 122. , 126 are address generation circuits for generating a read address of the memory 122.

The operation of the embodiment shown in FIG. 6 will be described. When an application program displays an image, first, the image data to be tallest is written to the memory 122 in the raster scan order, and then the image data to be enlarged or reduced is written to the memory 120. Then, the memory 1 is stored in the address generation circuit 124 via the command decoder 30.
A read speed of 20 and a writing range to the memory 122 are set, and a scaling ratio is set in the scaling circuit 24.

The address generation circuit 124 generates a read address for sequentially reading data from the memory 120 at the set read speed and supplies the read address to the memory 120.
At the same time, a write address for writing the scaled data output from the scaling circuit 24 to a set range of the memory 122 is generated and supplied to the memory 122. The memory 120 reads the stored data to the scaling circuit 24 according to the read address from the address generation circuit 124.

The scaling circuit 24 includes a command decoder 3
0 according to the enlargement / reduction ratio set by 0.
The data from 0 is enlarged or reduced and output to the memory 122. The memory 122 writes the output data of the enlargement / reduction circuit 24 at a position specified by the write address generated by the address generation circuit 124 on the background to be stored first. As a result, the image scaled by the scaling circuit 24 is overwritten on the previously stored background.

The image synthesized on the memory 122 is sequentially read out to the A / D converter 26 in accordance with the read address generated by the address generation circuit 126, converted into an analog signal, and converted to an RGB signal output terminal 28. To the monitor 38.

As in the case of FIG. 1, the address generation circuit 1
A timing signal is output from 26 to a SYNC generation circuit 34, and the SYNC generation circuit 34 generates a SYNC signal from the input timing signal. The SYNC signal is applied from a SYNC output terminal 36 to a monitor 38.

FIG. 7 is a flowchart showing the operation of the embodiment shown in FIG. The background data is written into the memory 122 (S11), and the image data to be enlarged or reduced is written into the memory 120 (S12). Via the command decoder 30,
The read speed of the memory 120 and the write start position and write range of the memory 122 are determined by the address generation circuit 12.
4 (S13). The enlargement / reduction ratio is set in the enlargement / reduction circuit 24 via the command decoder 30 (S1).
4). A time interval for scaling up and down with time is set for a timer interrupt inside the CPU 10 (S15), and a standby state for the timer interrupt is entered (S16).

When the time set in S14 elapses, a timer interrupt occurs. First, the write start position and write range of the memory 122 and the read speed of the memory 120 are updated via the command decoder 30 (S1).
7), the scaling factor of the scaling circuit 24 is updated (S1).
8). It is determined whether or not a desired final magnification has been reached (S1).
9) When the final magnification has been reached, the process ends. When the final magnification has not been reached, the timer interrupt is again waited for (S20), and S16 and S18 are repeated until the final magnification is reached by the timer interruption.

FIG. 8 is a schematic diagram showing an example of the screen of the embodiment shown in FIG. Reference numeral 130 denotes a storage data area of the memory 120, in which a person image 132 is written by the CPU 10. Reference numeral 134 denotes a storage data area of the memory 122, in which a background image 136 is stored.
Is written.

In the rectangular area 138 of the storage data area 134 of the memory 122, an image read from the memory 120 and scaled by the scaling circuit 24 is stored.
The magnification of the scaling circuit 24 is 1 and the image 132 stored in the memory 120 is
The size is transferred to the rectangular area 138 of the memory 122.

Reference numeral 140 denotes a storage data area of the memory 122. The image 130 stored in the memory 120 is enlarged and transcribed into the storage data amount area 140. A rectangular area 141 surrounded by a dotted line is obtained by enlarging the data storage area 130 of the memory 120 at the enlargement ratio of the enlargement / reduction circuit 24 and overlapping the storage area 140 of the memory 122. It can be seen that the size of the background image 136 does not change and only the person image 132b is enlarged.

Next, an embodiment of the present invention for realizing high image quality interpolation will be described. FIG. 14 is a schematic block diagram of an embodiment of a horizontal interpolation device using four pixels in the horizontal direction.

The field memory 252 has an input terminal 2
Image data S having a predetermined sampling frequency (for example, a sampling frequency determined by an image sensor) is input from 50, and one field is stored. The memory readout circuit 256 continuously determines the interpolation pixel position according to the zoom ratio setting value zoom from the zoom ratio input terminal 254, similarly to the memory readout circuit 216, and determines the interpolation pixel position in the original image data of the field memory 252. to output the pixel data S _n immediately after the field memories 2
52, a read control signal Cr is supplied.

The zoom ratio setting value zoom is a value that sets the zoom ratio R to R = 256 / (256 + zoom) when the zoom resolution is 8 bits, as in the conventional example shown in FIG. If zoom takes a positive integer value, the image is reduced, and if it takes a negative integer value, the image is enlarged.

The coefficient generation circuit 260 is connected to the update control terminal 25
8 according to the update control signal inc from
The absolute value of oom is cumulatively added to calculate a coefficient k indicating the distance between the original sampling pixel position and the interpolation pixel position. The coefficient generating circuit 260 also applies a hold signal to the field memory 252 and the delay circuits 262, 264, 266 when a carry occurs in the process of accumulating the coefficient k. The function and configuration of the coefficient generation circuit 260 may be exactly the same as those of the coefficient generation circuit 220.

[0074] field memory 252 reads the pixel data _{S n} instructed by the read control signal Cr. The read pixel data is sequentially delayed by one clock of the original sampling frequency by serially connected delay circuits 262, 264, and 266. The delay circuits 262, 264, and 266 simultaneously output the respective delay data. Outputs of the delay circuits 262, 264, and 266 are represented as pixel data Sn _-1 , _Sn-2 , and _Sn-3 , respectively.

The multiplier 268 receives the signal from the coefficient generation circuit 260
The output coefficient k is squared, and the multiplier 270
The output of 8 is further multiplied by a coefficient k. Coefficient generation circuit 260
Output k of the multiplier 268²And the multiplier 270
Output k³Are the coefficient generation circuits 272, 274, 276, 2
78. Coefficient generation circuits 272, 274, 27
6 and 278 respectively represent the interpolation pixel value S ′ as the original pixel data.
S_n, S_n-1, S_{n -2}, S_n-3And from coefficient k to 3
Original pixel data S when approximated by the degree polynomial_n, S
_n-1, S_n-2, S_n-3Interpolation coefficient k corresponding to₀,
k₁, K₂, K ₃Occurs. These coefficients k₀,
k₁, K₂, K₃Is k, k²And k³Easy number from
It can be calculated by the formula.

The multiplier 280 outputs the output S of the delay circuit 266.
The coefficient _{k 3} is multiplied by _n-3, multiplier 282 multiplies the coefficient _{k 2} to the output _{S n-2} of the delay circuit 264, the multiplier 28
4 multiplies the coefficient _{k 1} to the output _{S n-1} of the delay circuit 262, multiplier 286, coefficient output _{S n} of the memory 252 k
Multiply by _zero . The adder 288 adds the outputs of the multipliers 280 and 282, the adder 290 multiplies the output of the adder 288 by the output of the multiplier 284, and the adder 292 adds
The output of the multiplier 286 is added to the output of 0. Adder 29
The output of No. 2 is the interpolated pixel value S ', which is output to the outside.

FIG. 15 shows the pixel data S _n , S _n−1 , S
The relationship between _n-2 and Sn _-3 and the interpolated pixel S 'is shown.

The operation of the field memory 252 is the same as that of the conventional field memory 212. The configurations of the delay circuits 262, 264, and 266 are exactly the same as those of the conventional delay circuit 224.

Coefficient generation circuits 272, 274, 276, 2
The configuration of 78 is shown in FIG. These coefficient generating circuits 27
Interpolation coefficient k obtained by 2,274,276,278
_x (x = 0, 1, 2, 3) is obtained by approximating a time characteristic obtained by Fourier-transforming a desired frequency characteristic of the interpolation filter by a cubic function k _x = ak ³ + bk ² + ck + d. is there.

The horizontal interpolation pixel data S 'thus obtained
FIG. 17 shows the response characteristics of. For reference, the response characteristics of the conventional example using two-pixel linear interpolation are also shown. As can be seen from FIG. 17, the response in the band is significantly improved as compared with the linear interpolation, and a high-resolution enlarged / reduced image can be provided.

FIG. 18 is a block diagram showing a schematic configuration of an embodiment of the vertical interpolation device. In this embodiment, four pixels near the vertical direction are used to calculate the interpolated pixel value. FIG.
14 differs from the embodiment shown in FIG. 14 in that the delay amounts of the delay circuits 322, 324, 326 corresponding to the delay circuits 262, 264, 266 of the embodiment shown in FIG.

The field memory 312 has an input terminal 3
10 to image data S of a predetermined sampling frequency (for example,
For example, the horizontal interpolation device shown in FIG.
Pixel data S ') is input and one field is stored.
Is done. The memory read circuit 316 reads the memory
Similar to the circuits 216 and 256, the zoom ratio input terminal 314
The interpolation pixel position according to the zoom ratio setting value zoom from
It is determined continuously and the original image data in the field memory 312 is determined.
Pixel data S immediately after the interpolation pixel position in the data _nOutput
Read control signal to the field memory 312
No. Cr is supplied.

The zoom ratio setting value zoom is set to be R = 256 / (256 + zoom) when the zoom resolution is 8 bits, as in the conventional example shown in FIG. 10 and the embodiment shown in FIG. Value. If zoom takes a positive integer value, the image is reduced, and if it takes a negative integer value, the image is enlarged.

The coefficient generation circuit 320 is connected to the update control terminal 31
8 according to the update control signal inc from
The absolute value of oom is cumulatively added to calculate a coefficient k indicating the distance between the original sampling pixel position and the interpolation pixel position. The coefficient generation circuit 320 also applies a hold signal to the field memory 312 and the delay circuits 322, 324, 326 when a carry occurs in the process of accumulating the coefficient k. The function and configuration of the coefficient generation circuit 320 are exactly the same as those of the coefficient generation circuits 220 and 260.

[0085] field memory 312 reads the pixel data _{S n} instructed by the read control signal Cr. The read pixel data is sequentially delayed by one horizontal line of the input image data S by serially connected delay circuits 322, 324, and 326. The delay circuits 322, 324, and 326 output respective delay data at the same time. Outputs of the delay circuits 322, 324, and 326 are represented as pixel data Sn _-1 , _Sn-2 , and _Sn-3 , respectively.

The multiplier 328 outputs a signal from the coefficient generation circuit 320
The output coefficient k is squared, and the multiplier 330
The output of 8 is further multiplied by a coefficient k. Coefficient generation circuit 320
Output k of the multiplier 328²And the multiplier 330
Output k³Are the coefficient generation circuits 332, 334, 336, 3
38. Coefficient generation circuits 332, 334, 33
6 and 338 each represent the interpolation pixel value S ′ as the original pixel data.
S_n, S_n-1, S_{n -2}, S_n-3And from coefficient k to 3
Original pixel data S when approximated by the degree polynomial_n, S
_n-1, S_n-2, S_n-3Interpolation coefficient k corresponding to₀,
k₁, K₂, K ₃Occurs. These coefficients k₀,
k₁, K₂, K₃Is k, k²And k³Easy number from
It can be calculated by the formula.

The multiplier 340 outputs the output S of the delay circuit 326.
The coefficient _{k 3} is multiplied by _n-3, multiplier 342 multiplies the coefficient _{k 2} to the output _{S n-2} of the delay circuit 324, the multiplier 34
4 multiplies the coefficient _{k 1} to the output _{S n-1} of the delay circuit 322, multiplier 346, coefficient output _{S n} of the memory 312 k
Multiply by _zero . The adder 348 adds the outputs of the multipliers 340 and 342, the adder 350 multiplies the output of the adder 348 by the output of the multiplier 344, and the adder 352 adds the output of the adder 35.
The output of the multiplier 346 is added to the output of 0. Adder 35
The output of No. 2 is the interpolated pixel value S ', which is output to the outside.

FIG. 19 shows pixel data S _n , S _n−1 , S
The relationship between _n-2 and Sn _-3 and the interpolated pixel S 'is shown.

The operation of the field memory 312 is shown in FIG.
14 and the field memory 252 of the embodiment shown in FIG.

The delay circuits 322, 324 and 326 correspond to those shown in FIG.
0, the line delay element 35 for one horizontal line
Consists of four. When the hold signal is input, the line delay element 354 repeatedly outputs the pixel data specified by the immediately preceding read control signal Cr.

Coefficient generation circuits 332, 334, 336, 3
38 is a coefficient generation circuit 272, 274, 276, 278
It has exactly the same configuration. That is, the interpolation coefficient k obtained by these coefficient generation circuits 332, 334, 336, 338
_x (x = 0, 1, 2, 3) is obtained by approximating a time characteristic obtained by Fourier-transforming a desired frequency characteristic of the interpolation filter by a cubic function k _x = ak ³ + bk ² + ck + d. is there.

The vertical interpolation pixel data S ′ thus obtained
And the comparison with the response characteristics according to the conventional example are the same as in the case of the horizontal interpolation pixel data S ′ from four pixels (FIG. 17). The response in the band is greatly improved as compared with the linear interpolation, and a high-resolution enlarged / reduced image can be provided.

FIG. 21 is a schematic block diagram showing a modification of the embodiment of the horizontal interpolation apparatus shown in FIG. The same components as those in FIG. 1 are denoted by the same reference numerals. Specifically, FIG.
Coefficient generating circuits 272, 274, 27 of the embodiment shown in FIG.
6,278 are converted to a coefficient generation circuit 272 having the configuration shown in FIG.
a, 274a, 276a, and 278a, so that the coefficients a, b, c, and d in k _x = ak ³ + bk ² + ck + d can be changed from outside. The coefficient generation circuit 356 is connected to the zoom ratio input terminal 25
According to the zoom ratio setting value zoom from 4, the coefficients a,
b, c, d are generated, and coefficient generating circuits 272a, 274
a, 276a, 278a.

The coefficient generation circuit 356 comprises, for example, a look-up table or a selector. Thereby, a desired one can be selected from several cubic functions obtained by performing Fourier transform.

The operation of the other parts is exactly the same as that of the embodiment shown in FIG. The embodiment shown in FIG. 21 can also achieve the same operation and effect as the embodiment shown in FIG. It can also be enjoyed. Interpolation filters having different characteristics can be applied according to the enlargement / reduction ratio, and a more preferable enlarged / reduced image can be obtained.

FIG. 23 is a schematic block diagram showing a further modification of the embodiment of the horizontal interpolation device shown in FIG. The same components as those in FIG. 1 are denoted by the same reference numerals. Multipliers 268 and 270 and coefficient generating circuit 2 of the embodiment shown in FIG.
The portion consisting of 72 to 278 has been changed.

The changed parts will be described. Multiplier 360
Squares the output k of the coefficient generation circuit 260 and subtracts
2 subtracts 1 from the output k of the coefficient generation circuit 260 and multiplies
The unit 364 squares the output (k-1) of the subtractor 362.
The coefficient generation circuit 366 outputs the output k of the coefficient generation circuit 260,
Output k of multiplier 360², The output of the subtractor 362 (k−
1) and the output of the multiplier (k-1)²From the following equation
And the multiplication coefficient of the multipliers 280, 282, 284, 286
k₃, K₂, K₁, K₀(Ie, the original pixel data
S_{n- 3}, S_n-2, S_n-1, S_nInterpolation coefficient for
k₀, K₁, K₂, K₃). That is, k₀= K²・ (K-1) k₁= K−k²・ (K-1) k₂= K · (k-1)²+ (K-1) k₃= -K · (k-1)²  It is. FIG. 12 is a schematic block diagram of a configuration of a coefficient generation circuit 366.
24.

In the embodiment shown in FIG. 14 and subsequent figures, a field memory is used. However, when frame processing is performed by an all-pixel readout type CCD image sensor or the like, the frame memory is used to increase the vertical resolution. It goes without saying that it can be improved.

The present invention may be applied to a system composed of a plurality of devices or an apparatus composed of one device.

Further, in order to operate various devices so as to realize the functions of the above-described embodiment, software for realizing the functions of the above-described embodiments is installed in a computer in an apparatus or a system connected to the various devices. The present invention also includes a case in which a program (code) is supplied and a computer (CPU or MPU) of the apparatus or system is operated by operating the various devices according to stored programs.

In this case, the program code itself of the software realizes the functions of the above-described embodiment, and the program code itself and means for supplying the program code to the computer, for example,
A storage medium storing such a program code constitutes the present invention. As a storage medium for storing such a program code, for example, a floppy disk, hard disk, optical disk, magneto-optical disk, CD-ROM, magnetic tape, nonvolatile memory card, ROM and the like can be used.

When the computer executes the supplied program code, not only the functions of the above-described embodiment are realized, but also the OS (operating system) or other operating system running on the computer. Even when the functions of the above-described embodiments are realized in cooperation with application software and the like, it goes without saying that such program codes are included in the embodiments of the invention according to the present application.

Further, the supplied program code is:
After being stored in the memory provided in the function expansion board of the computer or the function expansion unit connected to the computer, the CPU or the like provided in the function expansion board or the function expansion unit performs one of the actual processing based on the instruction of the program code. It is needless to say that a case where the functions of the above-described embodiments are realized by performing all or part of the processes and executing the processing is also included in the invention according to the present application.

[0104]

As can be easily understood from the above description, according to the present invention, an image enlarged or reduced to high quality can be obtained at high speed, for example, in real time. Since enlargement / reduction is performed based on data of four pixels around the pixel to be interpolated, image deterioration at the time of enlargement / reduction can be minimized.

Since scaling can be performed only by integer operations, a logic IC can be easily formed, and high integration can be performed at low cost.

Since only a part of the image can be enlarged and reduced with high image quality, a larger image effect can be obtained.

According to the pixel interpolation apparatus of the present invention, an image can be enlarged or reduced in a vertical or horizontal direction in real time with a simple circuit configuration. In addition, it is possible to obtain better frequency characteristics than before.

[Brief description of the drawings]

FIG. 1 is a schematic configuration block diagram of an embodiment of an image signal forming apparatus according to the present invention.

FIG. 2 is an operation flowchart of the embodiment shown in FIG. 1;

FIG. 3 is a schematic diagram illustrating an example of a display image of the embodiment illustrated in FIG. 1;

FIG. 4 is a schematic block diagram of an enlargement / reduction circuit 24;

FIG. 5 shows a horizontal interpolation coefficient S generated by a coefficient generation circuit 58;
FIG. 6 is a diagram illustrating a relationship between a channel and a horizontal pixel shift signal Ssh.

FIG. 6 is a schematic configuration block diagram of a second embodiment of the present invention.

FIG. 7 is an operation flowchart of the embodiment shown in FIG. 6;

8 is a schematic diagram showing an example of a screen of the embodiment shown in FIG.

FIG. 9 is a conceptual diagram of linear interpolation.

FIG. 10 is a schematic configuration block diagram of a horizontal portion of a conventional linear interpolation device.

11 is a schematic configuration block diagram of a coefficient generation circuit 220. FIG.

FIG. 12 is a schematic configuration block diagram of a delay circuit 224.

FIG. 13 shows frequency characteristics of conventional linear interpolation using two adjacent pixels.

FIG. 14 is a schematic configuration block diagram of an embodiment of a horizontal interpolation device according to the present invention. Is shown.

FIG. 15 shows pixel data S in the embodiment shown in FIG.
It is a figure which shows the relationship between _n , _Sn-1 , Sn _{- 2} , _Sn-3 and the interpolation pixel S '.

FIG. 16 shows a coefficient generation circuit 272, 274, 276, 2
It is a schematic block diagram of 78.

17 shows horizontal interpolation pixel data S ′ according to the embodiment shown in FIG. 14 and response characteristics of a conventional example.

FIG. 18 is a schematic configuration block diagram of an embodiment of a vertical interpolation device according to the present invention.

FIG. 19 shows pixel data S in the embodiment shown in FIG.
It is a figure which shows the relationship between _n , _Sn-1 , Sn _{- 2} , _Sn-3 and the interpolation pixel S '.

FIG. 20 is a schematic configuration block diagram of delay circuits 322, 324, and 326. 354: Line delay element

FIG. 21 is a schematic block diagram of a modification of the embodiment shown in FIG. 14;

FIG. 22 shows coefficient generation circuits 272a, 274a, and 276.
It is a schematic block diagram of a, 278a.

FIG. 23 is a schematic block diagram of still another modification of the embodiment shown in FIG. 14;

FIG. 24 is a schematic block diagram of a configuration of a coefficient generation circuit 366.

[Explanation of symbols]

10: CPU 12: ROM 14: RAM 16: Disk device 18: Data bus 20: Address bus 22: Memory 24: Enlargement / reduction circuit 26: D / A converter 28: RGB output terminal 30: Command decoder 32: Address generation circuit 34: SYNC generation circuit 36: SYNC output terminal 40: whole image stored in memory 22 42: person image 42a, 42b: person image 44, 46: screen 50: data input terminal 52: synchronization pulse input terminal 54: magnification Input terminal 56: Clock input terminal 58: Coefficient generation circuit 60, 62, 64: 1 pixel delay circuit 88, 90, 92: 1 line delay circuit 66, 72, 78, 84, 94, 100, 106, 11
2: subtractor 68, 74, 80, 86, 96, 102, 108, 11
4: Multiplier 70, 76, 82, 98, 104, 110: Adder 116: Output terminal 120, 122: Memory 124: Address generating circuit 126: Address generating circuit 130: Storage data area 132, 132a of memory 120: Person Image 134: Storage data area of memory 122 136: Background image 138: Rectangular area 140: Storage data area of memory 122 141: Rectangular area 210: Input terminal 212: Field memory 214: Zoom ratio input terminal 216: Memory read circuit 218: Update control terminal 220: coefficient generating circuit 222: linear interpolation circuit 224: delay circuit 230: absolute value circuit 232: adder 234: delay circuit 236: subtractor 238: multiplier 240: adder 242: selector 244: delay element 250 : Input terminal 252: Field Mori 254: zoom ratio input terminal 256: memory readout circuit 258: update control terminal 260: coefficient generation circuit 262, 264, 266: delay circuit 268, 270: multiplier 272, 274, 276, 278: coefficient generation circuit 280, 282 , 284, 286: multipliers 288, 290, 292: adder 310: input terminal 312: field memory 314: zoom ratio input terminal 316: memory readout circuit 318: update control terminal 320: coefficient generation circuit 322, 324, 326: Delay circuits 328, 330: Multipliers 332, 334, 336, 338: Coefficient generation circuits 340, 342, 344, 346: Multipliers 348, 350, 352: Adders 272a, 274a, 276a, 278a: Coefficient generation circuits 356: Coefficient generation circuit 360: multiplier 362 Subtractor 364: Multiplier 366: coefficient generating circuit

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5B057 BA02 CB12 CD05 CD06 CD16 DA17 5C073 AA06 AB05 BB01 BD04 CE01 5C076 AA21 AA22 BA03 BA04 BB04 BB25 CB01

Claims (42)

[Claims] An image memory for holding image data, and image data read from the image memory interpolated in at least one of horizontal and vertical directions from pixel data of four or more points adjacent in the one direction. An image signal forming apparatus, comprising: an image processing means for changing the size of the image by changing the magnification; and an output means for generating an image signal from an output of the image processing means. 2. The image processing means determines a distance between an interpolated pixel and a pixel D2 when there is a pixel to be interpolated between the pixels D1 and D2 of four adjacent pixels D0, D1, D2, and D. When the value divided by the distance between the pixels D1 and D2 is k, in the two combinations of the pixel D0 and the pixel D3 and the pixel D1 and the pixel D2, the data of each combination is k for the former and k for the latter. 2. The image signal forming apparatus according to claim 1, wherein an average value obtained by adding and averaging (1-k) is obtained, and the two average values are used as pixel values of the interpolation pixels. 3. A first image memory for holding partial data of an image, and image data read from the first image memory being adjacent in at least one of a horizontal direction and a vertical direction in the one direction. Image processing means for interpolating and scaling from four or more pixel data, a second image memory for holding the output of the image processing means and other partial data of the image, and an output from the second image memory An image signal forming apparatus comprising: an output unit that generates an image signal. 4. The image processing means determines a distance between an interpolated pixel and a pixel D2 when there is a pixel to be interpolated between the pixels D1 and D2 of four adjacent pixels D0, D1, D2, and D. When the value divided by the distance between the pixels D1 and D2 is k, in the two combinations of the pixel D0 and the pixel D3 and the pixel D1 and the pixel D2, the data of each combination is k for the former and k for the latter. 4. The image signal forming apparatus according to claim 3, wherein an average value obtained by adding and averaging (1−k) is determined, and the two average values are used as pixel values of the interpolation pixels. 5. 5. A storage step of storing image data in an image memory, and four or more pixels adjacent to the image data read from the image memory in at least one of horizontal and vertical directions in the one direction. An image signal forming method, comprising: an image processing step of interpolating and scaling data from data; and an output step of generating an image signal from a processing result of the image processing step. 6. The image processing step includes, when there is a pixel to be interpolated between pixels D1 and D2 of four adjacent pixels D0, D1, D2, and D, the distance between the interpolated pixel and pixel D2. Assuming that a value obtained by dividing the distance between the pixels D1 and D2 is k, two of the pixels D0 and D3 and the pixels D1 and D2
In each of the combinations, an average value is obtained by adding and averaging the data of each combination with the weight of the former being k and the latter being (1-k), and calculating the two average values as the pixel value of the interpolation pixel. The image signal forming method according to claim 5, wherein 7. A first storing step of storing a part of data of an image in a first image memory; and storing the image data read from the first image memory in at least one of a horizontal direction and a vertical direction. An image processing step of interpolating and scaling from four or more pixel data adjacent in one direction, and storing the processing result of the image processing step in a second image memory for storing another part of the image data An image signal forming method, comprising: a second storage step; and an output step of generating an image signal from an output of the second image memory. 8. When there is a pixel to be interpolated between pixels D1 and D2 of four adjacent pixels D0, D1, D2, and D, the image processing means determines the distance between the interpolated pixel and pixel D2. When the value divided by the distance between the pixels D1 and D2 is k, in the two combinations of the pixel D0 and the pixel D3 and the pixel D1 and the pixel D2, the data of each combination is k for the former and k for the latter. 8. The image signal forming method according to claim 7, wherein an average value obtained by adding and averaging (1-k) as a weight is obtained, and the two average values are used as pixel values of the interpolation pixels. 9. A storage step of storing image data in an image memory, and four or more pixels adjacent to the image data read from the image memory in at least one of the horizontal and vertical directions in the one direction. And storing program software for executing an image signal forming method, comprising: an image processing step of interpolating and scaling from data; and an output step of generating an image signal from a processing result of the image processing step. Storage media. 10. The image processing step includes the steps of:
When there is a pixel to be interpolated between the pixels D1 and D2 of the pixels D0, D1, D2, and D, the interpolation pixel and the pixel D2
When the value obtained by dividing the distance between the pixel D1 and the pixel D2 by the distance between the pixels D1 and D2 is k, in each of the two combinations of the pixels D0 and D3 and the pixel D1 and the pixel D2, The storage medium according to claim 9, wherein an average value is obtained by adding and averaging k and the latter with (1−k) as weights, and the two average values are used as pixel values of interpolation pixels. 11. A first storage step of storing a part of data of an image in a first image memory; and storing image data read from the first image memory in at least one of a horizontal direction and a vertical direction. An image processing step of interpolating and scaling from four or more pixel data adjacent in one direction, and storing the processing result of the image processing step in a second image memory for storing another part of the image data A storage medium storing program software for executing an image signal forming method, comprising: a second storage step; and an output step of generating an image signal from an output of the second image memory. 12. The image processing means determines a distance between an interpolated pixel and a pixel D2 when there is a pixel to be interpolated between the pixels D1 and D2 of four adjacent pixels D0, D1, D2, and D. When the value divided by the distance between the pixels D1 and D2 is k, in the two combinations of the pixel D0 and the pixel D3 and the pixel D1 and the pixel D2, the data of each combination is k for the former and k for the latter. 12. The storage medium according to claim 11, wherein an average value obtained by adding and averaging (1-k) as a weight is obtained, and the two average values are used as a pixel value of an interpolation pixel. 13. stores image data, two pixel signals _S n on one side with respect to the interpolation pixel S _{', S} 2 a pixel signal of _n-1 and the other side _{S n-2, S n- 3} , the pixel position of the pixel signal _Sn-1 and the pixel signal S
first coefficient generating means for generating an interpolation coefficient k indicating the pixel position of the interpolation pixel signal S 'between the pixel position of _n-2 and multiplication means for calculating the square and the third power of the interpolation coefficient k And k, k ² , k ^3, and the pixel signals _Sn , _Sn-1 , S
interpolation coefficients k ₀ , k for _n−2 and pixel signal _{Sn− 3
1, k} 2, _{k 3} and the second coefficient generating means for generating a, the pixel signals _{S n, S n-1,} S n-2 and _{S n-3} in the interpolation coefficient _{k 0,} k _{1, k} 2, multiplied by k _3, to calculate the sum, image interpolation apparatus characterized by comprising a calculating means for outputting the interpolated pixel signal S '. 14. The interpolation coefficient k ₀ , k ₁ , k ³ from the k, k ² , k ³ in the second coefficient generation means.
_2, the coefficient of the arithmetic expression for calculating the k _3, the image interpolation apparatus according to claim 13 having a coefficient adjustment means for generating in response to the scaling factor. 15. The image data is stored and stored in an interpolated pixel S '.
On the other hand, two pixel signals S on one side_n, S_n-1And others
Two pixel signals S on one side_n-2, S_n-3Output
Image memory means, and the pixel signal S_n-1Pixel position and the pixel signal S
_n-2Pixel position of the interpolated pixel signal S 'between the pixel position
First coefficient generating means for generating an interpolation coefficient k indicating the position, a square of the interpolation coefficient k, and (k-1) and (k-1)
²Multiplication means for calculating k, k², (1-k) and (1-k)²From the pixel signal
No. S_n, S_n-1, S _n-2And the pixel signal S_n-3To
Interpolation coefficient k₀, K₁, K₂, K₃The second that produces
Coefficient generating means, and the pixel signal S_n, S_n-1, S_n-2And S_n-3To
Interpolation coefficient k₀, K₁, K₂, K₃Multiply and calculate the sum
And an operation means for outputting an interpolation pixel signal S ′
An image interpolating device, characterized in that: 16. The image memory means includes: an image memory for storing the image data; a memory reading means for sequentially reading pixel data from the image memory; and a pixel data read from the image memory for a predetermined period. A series of first, second and third delay means, wherein a pixel signal read from the image memory is a pixel signal _Sn , an output of the first delay means is a pixel signal _Sn-1 , The output of the second delay means is a pixel signal S
_n-2 , the output of the third delay means is a pixel signal _Sn-3.
The image interpolation device according to claim 13 or 15, wherein 17. The image interpolation apparatus according to claim 16, wherein said first, second, and third delay means have a delay amount corresponding to one clock of the original sampling frequency. 18. The image interpolation apparatus according to claim 16, wherein said first, second and third delay means have a delay amount corresponding to one scanning line of the original sampling frequency. 19. The image interpolation apparatus according to claim 13, wherein said first coefficient generation means updates the interpolation coefficient when receiving an update control signal of an original sampling pixel for generating an interpolation pixel. 20. The image interpolation device according to claim 16, wherein the image memory repeatedly reads out the pixel data read immediately before when the update control signal of the pixel requires holding. 21. The image interpolation apparatus according to claim 16, wherein said first, second, and third delay means hold current pixel data when a pixel update control signal requires holding. 22. The first coefficient generation circuit includes an accumulator having an n-bit width, and when receiving an update control signal of an original sampling pixel for generating an interpolation pixel, sets a constant representing an interpolation ratio to n bits. 16. The image interpolation apparatus according to claim 13, wherein the image interpolation apparatus performs cumulative addition by width and outputs a carry as a pixel update holding signal when the width exceeds an n-bit width. 23. Image memory means for storing image data
From the two pixel signals on one side with respect to the interpolation pixel S '
S_n, S_n-1And two pixel signals on the other side
S _n-2, S_n-3Output pixel signal output step
And the pixel signal S_n-1Pixel position and the pixel signal S
_n-2Pixel position of the interpolated pixel signal S 'between the pixel position
First coefficient generating step of generating an interpolation coefficient k indicating the position
And a multiplication step for calculating the square and the third power of the interpolation coefficient k
And k, k², K³From the pixel signal S_n, S_n-1, S
_n-2And the pixel signal S_{n -3}Interpolation coefficient k for₀, K
₁, K₂, K₃And a second coefficient generating step of generating the pixel signal S_n, S_n-1, S_n-2And S_n-3To
Interpolation coefficient k₀, K₁, K₂, K₃Multiply and calculate the sum
And an operation step of outputting an interpolation pixel signal S ′.
An image interpolation method comprising: 24. Further, in the second coefficient generating step,
K, k², K ³From the interpolation coefficient k₀,
k₁, K₂, K₃The scaling factor of the calculation formula that calculates
Claims: A coefficient adjusting step which is performed according to a rate.
24. The image interpolation method according to 23. 25. Image memory means for storing image data
From the two pixel signals on one side with respect to the interpolation pixel S '
S_n, S_n-1And two pixel signals on the other side
S _n-2, S_n-3Output pixel signal output step
And the pixel signal S_n-1Pixel position and the pixel signal S
_n-2Pixel position of the interpolated pixel signal S 'between the pixel position
First coefficient generating step of generating an interpolation coefficient k indicating the position
And the square of the interpolation coefficient k and (k-1) and (k-1)
²A multiplication step of calculating k, k², (1-k) and (1-k)²From the pixel signal
No. S_n, S_n-1, S _n-2And the pixel signal S_n-3To
Interpolation coefficient k₀, K₁, K₂, K₃The second that produces
A coefficient generation step and the pixel signal S_n, S_n-1, S_n-2And S_n-3To
Interpolation coefficient k₀, K₁, K₂, K₃Multiply and calculate the sum
And an operation step of outputting an interpolation pixel signal S ′.
An image interpolation method comprising: 26. The pixel signal output step includes the steps of:
Pixel data from image memory that stores data
And a first, second, and third delay means for a series of predetermined delay periods.
Pixels delayed by the stage and read from the image memory
The signal is a pixel signal S _n, The output of the first delay means
Signal S_n-1, The output of the second delay means to the pixel signal S
_n-2, The output of the third delay means to the pixel signal S_n-3
The image interpolation method according to claim 23 or 25. 27. The image interpolation method according to claim 26, wherein said first, second and third delay means have a delay amount corresponding to one clock of the original sampling frequency. 28. The image interpolation method according to claim 26, wherein said first, second and third delay means have a delay amount corresponding to one scanning line of the original sampling frequency. 29. The first coefficient generating step updates an interpolation coefficient when receiving an update control signal of an original sampling pixel for generating an interpolation pixel.
The image interpolation method described in 1. 30. The image interpolation method according to claim 26, wherein the image memory repeatedly reads out pixel data read immediately before, when the pixel update control signal requests holding. 31. The image interpolation method according to claim 26, wherein said first, second, and third delay means hold current pixel data when a pixel update control signal requires holding. 32. The first coefficient generation step includes, when receiving an update control signal of an original sampling pixel for generating an interpolation pixel, accumulating a constant representing an interpolation ratio with an n-bit width and exceeding the n-bit width. 26. The image interpolation method according to claim 23, wherein the carry is output as an update holding signal of the pixel when the image is held. 33. Image memory means for storing image data
From the two pixel signals on one side with respect to the interpolation pixel S '
S_n, S_n-1And two pixel signals on the other side
S _n-2, S_n-3Output pixel signal output step
And the pixel signal S_n-1And the pixel signal S
_n-2Pixel position of the interpolated pixel signal S 'between the pixel position
First coefficient generating step of generating an interpolation coefficient k indicating the position
And a multiplication step for calculating the square and the third power of the interpolation coefficient k
And k, k², K³From the pixel signal S_n, S_n-1, S
_n-2And the pixel signal S_{n -3}Interpolation coefficient k for₀, K
₁, K₂, K₃And a second coefficient generating step of generating the pixel signal S_n, S_n-1, S_n-2And S_n-3To
Interpolation coefficient k₀, K₁, K₂, K₃Multiply and calculate the sum
And an operation step of outputting an interpolation pixel signal S ′.
Program / software that executes the image interpolation method
A storage medium characterized by storing the information. 34. The image interpolating method further coefficient calculation formula for calculating the ^k, k 2, the interpolation coefficient _k 0 from ^{_{k 3, k 1, k 2}} , k 3 in the second coefficient generating step 34. The storage medium according to claim 33, further comprising: a coefficient adjustment step of generating a coefficient according to a scaling ratio. 35. Image memory means for storing image data
From the two pixel signals on one side with respect to the interpolation pixel S '
S_n, S_n-1And two pixel signals on the other side
S _n-2, S_n-3Output pixel signal output step
And the pixel signal S_n-1Pixel position and the pixel signal S
_n-2Pixel position of the interpolated pixel signal S 'between the pixel position
First coefficient generating step of generating an interpolation coefficient k indicating the position
And the square of the interpolation coefficient k and (k-1) and (k-1)
²A multiplication step of calculating k, k², (1-k) and (1-k)²From the pixel signal
No. S_n, S_n-1, S _n-2And the pixel signal S_n-3To
Interpolation coefficient k₀, K₁, K₂, K₃The second that produces
A coefficient generation step and the pixel signal S_n, S_n-1, S_n-2And S_n-3To
Interpolation coefficient k₀, K₁, K₂, K₃Multiply and calculate the sum
And an operation step of outputting an interpolation pixel signal S ′.
Program / software that executes the image interpolation method
A storage medium characterized by storing the information. 36. The pixel signal output step includes the steps of:
Pixel data from image memory that stores data
And a first, second, and third delay means for a series of predetermined delay periods.
Pixels delayed by the stage and read from the image memory
The signal is a pixel signal S _n, The output of the first delay means
Signal S_n-1, The output of the second delay means to the pixel signal S
_n-2, The output of the third delay means to the pixel signal S_n-3
The storage medium according to claim 33 or 35. 37. The storage medium according to claim 36, wherein said first, second and third delay means have a delay amount corresponding to one clock of the original sampling frequency. 38. The storage medium according to claim 36, wherein said first, second and third delay means have a delay amount corresponding to one scanning line of the original sampling frequency. 39. The method according to claim 33, wherein the first coefficient generating step updates the interpolation coefficient when receiving an update control signal of the original sampling pixel for generating the interpolation pixel.
A storage medium according to claim 1. 40. The storage medium according to claim 36, wherein the image memory repeatedly reads out the pixel data read immediately before when the update control signal of the pixel requests holding. 41. The storage medium according to claim 36, wherein said first, second, and third delay means hold current pixel data when a pixel update control signal requests holding. 42. The first coefficient generating step includes, when receiving an update control signal of an original sampling pixel for generating an interpolation pixel, accumulating a constant representing an interpolation ratio with an n-bit width and exceeding the n-bit width. 36. The storage medium according to claim 33, wherein the carry is output as an update holding signal of the pixel when the signal is output.