JP2000068993A - Word synchronization circuit and data transmitter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it possible to simplify the circuit considerably based on because a shift register in a syndrome arithmetic circuit usable in common for an error correction decoder. SOLUTION: The word synchronization circuit at a receiver side that, respect to a data stream the information bit of which a redundant bit is added to for error correction and transmitted from a transmitter side, calculates a syndrome from the information bit and the redundant bit and establishes word synchronization for error correction based on the syndrome consists of a syndrome arithmetic circuit that receives simultaneously all of information and redundant bits being an object of syndrome calculation, calculated them altogether, a word synchronization protection circuit that generates an initializing signal of a timing for error correction and a timing pulse generating circuit to be initialized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a data transmission device,
In particular, the present invention relates to a word synchronization circuit that synchronizes with a transmission side in a receiving section in a microwave band digital multiplex radio apparatus.

[0002]

2. Description of the Related Art In recent years, it has become important to secure transmission quality by error correction even in a data transmission device such as a wireless device. However, on the other hand, an increase in the amount of transmission information due to additional bits has become a problem. There is a demand for a transmission amount reduction method such as a synchronization method that does not require the additional bits.

Against this background, as in the present invention, Japanese Patent Publication No. 7-386 describes a method of synchronizing words by syndrome.
No. 26 publication.

According to the above publication, referring to FIG. 5, an error correction operation means for inputting a coded data signal 102 transmitted from the transmission side and subjected to error correction coding as one word and performing error correction decoding is provided. In the word synchronization detection circuit provided, the encoded data signal is delayed from 1 bit to (n-1) bits (n is 2 ≦ n ≦ error correction code length) by (n−1) delay codes. (N-1) delay units 24 for outputting encoded data signals, and timings indicating start points of error detection calculations for the encoded data signal and the (n-1) delayed encoded data signals, respectively. A timing generator 25 for generating a signal, wherein the error correction operation means is configured to execute the encoding data signal and (n-1) based on a timing signal from the timing generator 25.
And n error correction arithmetic units 22 for performing error detection operation and synchronization determination for each of the delayed encoded data signals and outputting a synchronization determination signal, respectively. A synchronous data signal selector 23 for selectively outputting a synchronous data signal according to a determination signal is provided.

[0005] With such a configuration, the receiving side has n error correction calculators 22 and simultaneously performs n synchronization determination processes in parallel, calculates the syndrome using the check bits in word units, and detects the error. It indicates that there is no error. By repeatedly detecting no error M times and considering it as synchronous, the maximum number of hunting times becomes 1 / n compared to the case where the number of error correction calculators 22 is one. It is disclosed that the word synchronization can be shortened, and the word has the characteristic that the synchronization can be established by an error correction operation without requiring a synchronization identification signal for detecting the synchronization within the word.

[0006]

However, since the delay unit and the error correction operation unit are required to be at least as many as the number of word bits in word units, the configuration becomes large-scale, so that the limiting factor of miniaturization and the reliability are reduced. This was the cause of the decline.

Further, the above-mentioned error correction calculator, that is, a circuit for calculating a syndrome, employs a sequential calculation system having feedback adders 31, 32, registers 33, 34 and a multiplier 35 as shown in FIG. Although the arithmetic circuit itself becomes simple, it still requires a plurality of groups of delay units and registers, so that the configuration is large and complicated.

An object of the present invention is to provide a shift register in a syndrome operation circuit that can be used in common with an error correction decoder.

[0009]

According to the present invention, a data string transmitted from a transmitting side by adding redundant bits to information bits for error correction is transmitted from a transmitting side to a syndrome from the information bits and the redundant bits. In a word synchronization circuit that calculates and establishes word synchronization for error correction by the syndrome, all the bits of the information bits and the redundant bits to be subjected to the syndrome calculation are simultaneously taken into the syndrome operation circuit and collectively operated to perform word synchronization protection. A timing pulse generating circuit for generating and initializing the error correction timing initialization signal by a circuit.

In the above word synchronizing circuit, the data stream is decoded into an original data stream in accordance with a timing signal of the timing pulse generating circuit and a syndrome signal of the syndrome operation circuit, and the redundant data is decoded. An error correction decoder for performing error correction of the data string according to bits is provided.

In the above word synchronizing circuit, the syndrome operation circuit includes: a shift register for the information bits and the redundant bits for inputting the data string; a predetermined word bit register for comparing with the shift register; It is characterized by comprising: the first addition circuit for adding the bit comparison result, and a second addition circuit for multiplying each bit of the bit comparison result by each multiplication coefficient and adding the result.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments according to the present invention will be described.
This will be described in detail with reference to the drawings.

[First Embodiment] (Configuration of this Embodiment) FIG. 1 shows a block diagram of an embodiment of the present invention. According to the figure, reference numeral 1 denotes a syndrome operation circuit which correctly calculates the relationship between information bits and redundant bits of a data sequence continuously received from a received data sequence input and outputs syndromes S0 and S1, and 2 and 3 denote syndrome operation circuits. A NOR circuit for inverting the syndrome signals S0 and S1 of the OR circuit;
Reference numeral 5 denotes each of the syndromes S0 and S1 from the output of the OR circuit 4.
When both are zero, a word synchronization protection circuit that is synchronized and outputs a synchronization protection signal, and a timing generator that receives the synchronization protection signal and generates a timing signal matching the synchronization protection signal from the free-running timing signal The circuit 7 detects and decodes a received data string input signal according to the timing signal according to the synchronization protection state and the syndromes S0 and S1 composed of redundant bits, and performs error correction using the error correction signal of redundant bits. It is a correction decoder.

Here, a Reed-Solomon code in which the generator polynomial G (x) = (x-1) (x-α) and the code word length is n + 1 words will be described as an example of the error correction code. That is, the redundant bits to be added to the information bits are a bit sequence corresponding to the Reed-Solomon code, and even if there are a plurality of error bits in the information bits, it can be corrected to a normal code.

Further, the signal flow will be described.
The received data sequence branches into two, one of which is an error correction decoder 7.
, And the other is input to the syndrome operation circuit 1 to output a first syndrome (hereinafter, S0) and a second syndrome (hereinafter, S1). If the received code has no error and the syndrome is correctly calculated, S0 and S1 become zero.

That is, if the relationship between the information bits of the data string to be continuously received and the redundant bits is correctly calculated, the syndrome is set to zero by adding the redundant bits to the original information bits. , Is also zero when demodulated, which corresponds to the detection of a codeword (word).

The syndromes S0 and S1 each divide into two branches, one is an error correction decoding circuit, and the other is a negative logic circuit 2, 3 because S0 and S1 are zero when a word is detected.
After passing (NOT), the signal is input to the OR circuit 4, the logical OR (AND) operation of the two is performed, and the result is input to the word synchronization protection circuit 5, where synchronization protection processing is performed.

Here, the synchronization protection is for initializing a subsequent timing pulse generation circuit.

The timing pulse generating circuit 6 is normally in a self-running state, but outputs a self-running initialization pulse and a synchronization protection signal initialization pulse generated from the result of word detection by the word synchronization protection circuit 5 a plurality of times. If it is determined that they are different from each other, the self-running timing generation circuit 6 is initialized. If they are not different, the synchronization protection state is initialized according to the synchronization protection signal and a timing signal is generated.

The logical OR operation of the syndromes S0 and S1 is protection against an error in word detection, and is equivalent to backward protection at the subsequent stage.

The word synchronization is established by the above series of operations. The timing pulse obtained by the word synchronization is input to the error correction decoder 7 as discrimination information of the position of the code word, information bits in the code word and redundant bits.

FIG. 2 shows the syndrome operation circuit 1 shown in FIG.
FIG. 3 is a block diagram of the configuration of FIG. The syndrome operation circuit 1 includes an n + 1-stage shift register 11, a multiplier 12, a first adder 13, and a second adder 14 corresponding to the error correction codeword length (information bits + redundant bits) of the data string.

The received data sequence input to the syndrome operation circuit 1 is sequentially shifted by the shift register 11. One output of each stage of the shift register 11 is input to the first adder 13 and added, and output as S0.

The output of each stage of the other shift register 11 is input to a multiplier 12, multiplied by each of the multiplication coefficients α to α ^{n + 1} and then input to a second adder 14 for addition. Output as S1.

In this embodiment, the code word length is set to n + 2 (code word length = n information words + 2 parity words). Therefore, the highest order of the coefficient of calculation of the syndrome S1 is α ^{n + 1}
Becomes For example, α = ⁹ when n = 8. Here, for the coefficient α, the Reed-Solomon code is composed of elements on the Galois field. The element is expressed as 0,
1, α, α ² , α ³ ,. . . Expressed as α ⁿ . Original is GF (2 ⁸ )
In the case of 0, 1, α, α2,. . . α ²⁵⁴ . Since actual hardware cannot directly handle exponentiation, it can be handled by converting it to a vector representation (binary representation). Before defining an element, a primitive polynomial must be defined. For example, ETSI DVBstandards ET
In S300 421, primitive polynomial p (x) is defined as ^{p (x) = x 8 +} x 4 + x 3 + x 2 +1.

That is, the multiplication coefficient α is calculated by the generator polynomial G (x)
And error correction syndrome definitions. Also,
Here, “n” of α ⁿ is used because the codeword length is n + 1.
This is for generalization.

In the above embodiment, the adders 13 and 14 are used.
And a syndrome calculation circuit. Further, in the present embodiment, single error correction has been described. If double error correction is used, four syndromes S0 to S3 are required, and four blocks shown in FIG. 2 are required. Further, in the case of t-multiple error correction, since there are t syndromes from S0 to S (t-1), the processing blocks shown in FIG. However, for word synchronization, it is not necessary to calculate all t values.

(Operation of the Present Embodiment) The circuit operation of FIGS. 1 and 2 will be described with reference to the waveforms of the respective parts.

FIG. 3 is a time chart until a word synchronization pulse is generated from a received data string.

The received data string is composed of codeword-0 to codeword-
1, the code word-2 are sequentially input to the shift register 11 of the syndrome arithmetic circuit, and the code words are S0 and S1 in the next time slot in which all the bits are input to the shift register 11.
Is detected. The syndromes S0 and S1 pass through NOT circuits 2 and 3 and an AND circuit 4, and a word synchronization protection circuit 5
And is subjected to synchronization protection processing. Here, an example is shown in which the number of protection stages of the synchronization protection is two.

When the received data string input 102 is codeword-0,
When they are sequentially input as 1 and 2, after the input of codeword-0 is completed,
The syndromes S0 and S1 are output, the outputs of the NOT circuits 2 and 3 and the OR circuit 4 become AND outputs, and the output of the word synchronization protection circuit 5 is in an undefined state until after the input of the next code word -1 is completed. After the completion of the input of the code word-1, the output of the word synchronization protection circuit 5 is output while discriminating between the information bit position and the redundant bit position.

That is, the initialization pulse of the word synchronization protection circuit 5 is not output at the position of the code word-0, 1, and the initialization pulse is output only at the position of the code word-2 where the pulse is output twice from the AND circuit 4. Is output. A word synchronization pulse is generated by the initialization pulse, and word synchronization is established. The word sync pulse output before word sync is established is undefined.

Next, the syndrome calculation will be described.
The arithmetic expressions of the syndromes S0 and S1 are represented by the following expressions.

[0034] _{S0 = r n-1 + r} n-2 + r n-3 + ... r 0 + p 1 + p 0 S1 = r n-1 α n + 1 + r n-2 α n + r n-3 α n-1 + … + R ₀ α ²
+ P ₁ α + p ₀ Here, rn−1 to r0 indicate information bits in the order of reception, similarly indicate redundant bits received in the order of p1 and p0, and α ^{n + 1} , α ⁿ . The multiplication coefficient is shown.

The information bits are random, and if there is no code error on the transmission path, a parity (redundancy) bit is added so that the syndrome becomes zero.
This point is also defined from the definition of the Reed-Solomon code. That is, if there is no error, the syndrome is zero, and not all information bits and redundant bits are zero. For example, if the information bit is zero,
The redundant bits go to zero, which is just one of the codeword patterns.

In the above embodiment, the Reed-Solomon code has been described as the error correction code. However, a Hamming code, a BCH code, or the like may be used as the error correction code, or an interleaving method may be used.

[Second Embodiment] In the first embodiment, as shown in the example of FIG.
Although the word synchronization is performed using the two syndromes 1 and 2, the same word synchronization operation can be performed by increasing the number of synchronization protection stages at the subsequent stage using only the syndrome S0. is there. In that case,
As shown in the syndrome operation circuit of FIG. 2, in the operation of the syndrome S1, a necessary multiplier can be eliminated, and the circuit can be greatly simplified.

Further, in each of the above embodiments, the word synchronization circuit according to the present invention has been described in detail. However, when the word synchronization circuit is used in a data transmission device used in a microwave digital multiplex radio apparatus, an error called word synchronization can be obtained. , And accurate data demodulation by the synchronization is possible. In the microwave band digital multiplex radio apparatus, the word synchronization circuit of the present invention functions in accordance with a reception data string obtained after demodulation into a baseband signal by a reception unit. Further, the data transmission device, together with the demodulation of the baseband signal, continuously performs acquisition and tracking of the word synchronization, but outputs a timing signal from the word synchronization timing generation circuit to the transmission unit of the wireless device, By adding a redundant bit to the transmission data information and modulating and outputting the transmission data information in a synchronized state together with the syndrome calculation and the like, the system system can be synchronized and accurate data transmission and reception with few errors can be performed. .

[0039]

According to the present invention, since the syndrome operation circuit for word synchronization is a necessary function in the error correction decoder and can be shared, a word detection circuit dedicated to word synchronization is not required. Word synchronization can be achieved with a simple configuration without providing a plurality of stages of delay units and arithmetic circuits.

Further, since word synchronization is performed by the syndrome, transmission of additional bits such as frame bits dedicated to synchronization is not required, so that efficient transmission becomes possible.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram of the syndrome operation circuit of FIG. 1;

FIG. 3 is a waveform chart for explaining the operation of FIG. 1;

FIG. 4 is a syndrome calculation block diagram of a conventional error correction calculator.

FIG. 5 is a block diagram of a conventional word synchronization circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Syndrome arithmetic circuit 2, 3 Negation circuit 4 OR circuit 5 Word synchronization protection circuit 6 Timing generation circuit 7 Error correction decoder 11 Shift register 12 Multiplier 13, 14 Adder

Claims (4)

[Claims] 1. A data sequence transmitted from a transmitting side by adding a redundant bit to an information bit for error correction, a receiving side calculates a syndrome from the information bit and the redundant bit, and corrects an error by the syndrome. In the word synchronization circuit for establishing the word synchronization for all the information bits of the syndrome calculation target and all the bits of the redundant bits are simultaneously taken into the syndrome operation circuit and collectively operated. A timing pulse generating circuit for generating and initializing an initialization signal. 2. The word synchronization circuit according to claim 1, further comprising: decoding the data stream into an original data stream according to a timing signal of the timing pulse generation circuit and a syndrome signal of the syndrome operation circuit. A word synchronization circuit, further comprising an error correction decoder for performing error correction of the data string according to the redundant bit. 3. The word synchronization circuit according to claim 1, wherein the syndrome operation circuit is configured to compare a shift register of the information bits and the redundant bits for inputting the data string with a predetermined word bit to be compared with the shift register. A register, the first addition circuit for adding the comparison result of each bit, and a second addition circuit for multiplying each bit of the comparison result of each bit by each multiplication coefficient and adding the result. Characteristic word synchronization circuit. 4. A data transmission device for use in a microwave band digital multiplex radio device, wherein word synchronization for error correction is performed by using the word synchronization circuit according to any one of claims 1 to 3. Data transmission equipment.