JP2000068404A - Substrate for bga package - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a substrate for BGA package that can respond to and mount a plurality of sizes for semiconductor chips. SOLUTION: This substrate 10 has a pattern 11, comprising a plurality of electrically separated conductor lines 12 on its surface on which a semiconductor chip is mounted. Each conductor line has ball bonding regions 12a positioned on a via hole, a first bonding area 12b for wire-bonding a semiconductor chip positioned outside of a region on the substrate, where the via holes are formed and a second bonding region 12c for wire-bonding a semiconductor chip positioned inside a region on the substrate where the via holes are formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a substrate for a BGA package, and more particularly to a substrate on which a plurality of types of semiconductor chips having different sizes can be mounted.

[0002]

2. Description of the Related Art A BGA (Ball Grid Array) package is a surface-mount type semiconductor package in which solder balls are two-dimensionally arranged on the bottom surface of a package. QFP (Quad
Compared with a package using a lead frame such as a Flat Package, the BGA package can increase the number of connection terminals per unit area and is suitable for realizing high-density mounting.

FIG. 6 shows a conventional general BGA package semiconductor device. The semiconductor device 60 includes a plurality of solder balls 62 on a bottom surface of a rectangular insulating substrate 61.
Dimensionally provided. A conductor pattern 63 is formed on the upper surface of the insulating substrate 61 by a photolithography technique,
It is electrically connected to the solder ball 62 through the via hole 61a. The semiconductor chip 64 is adhered on the insulating substrate 61 by a die paste, and the electrical connection with the conductor pattern 63 is achieved by the conductor wires 65 provided by wire bonding. The semiconductor chip 64 is covered with a resin package material 66 formed by injecting a molten resin into a mold.

FIG. 7 is a plan view of the semiconductor device 60 with the resin package material 66 removed. In the figure, the arrangement of the conductor patterns 63 on the insulating substrate 61 is clearly shown by omitting a part of the semiconductor chip 64 and the conductor wires 65. One end of each line 70 constituting the conductor pattern 63 is a region 70a on the via hole. The other end of each line 70 extends to each side of the insulating substrate 61. The line 70 extending to each side of the insulating substrate 61
Is provided with a bond region 70b along the side of the insulating substrate. In the wire bonding step, one end of the conductor wire 65 is bonded to each electrode pad 64a of the semiconductor chip 64, extended outward, and the other end is bonded to the bond region 70b.

On the other hand, a large number of semiconductor chips of different sizes are supplied depending on the number of circuit elements to be built therein, circuit designs, and differences in design rules. BGA
In a package, if semiconductor chips of different sizes can be mounted on the same type of insulating substrate, there is no need to prepare an insulating substrate for each chip size, and there is an advantage that the manufacturing cost can be greatly reduced. A semiconductor chip mounting method using wire bonding can cope with this by adjusting the length of the conductor wire.

[0006]

However, when a semiconductor chip having a size smaller than the size of the insulating substrate is mounted, one problem occurs. As the size of the semiconductor chip decreases, the distance from the electrode pad to the bond region increases, and therefore, the length of the conductor wire connecting them increases. At the time of molding, each conductor wire is deformed under pressure by the flow of the molten mold resin. If the length of the conductor wire is long, the amount of deformation due to pressure increases, and the risk of short-circuiting increases due to contact between adjacent conductor wires. Further, since a long conductor wire deteriorates its electrical characteristics, it is preferable to shorten the distance between the electrode pad and the bond region as much as possible.

SUMMARY OF THE INVENTION An object of the present invention is to provide a BG that can be mounted on a plurality of semiconductor chips.
An object of the present invention is to provide a substrate for an A package.

Another object of the present invention is to provide a substrate for a BGA package capable of keeping the length of a conductor wire constant or less irrespective of the size of a semiconductor chip to be mounted.

[0009]

SUMMARY OF THE INVENTION The present invention is directed to a first or second embodiment.
The present invention relates to a substrate for a BGA package on which a semiconductor chip having a size of 2.times. A substrate according to the present invention is an insulating base material having a first surface on which the semiconductor chip is mounted and a second surface on which a plurality of solder balls are two-dimensionally mounted, wherein the mounting of the solder ball is performed. It has a via hole corresponding to a position, and a pattern formed on a first surface of the base material and formed of a plurality of electrically separated conductor lines. In the present invention, each of the conductor lines is disposed on the via hole and electrically connected to the solder ball via the via hole, and is disposed outside a region on the substrate on which the via hole is formed. A first bond area for wire bonding the semiconductor chip of the first size, wherein the first bond area is arranged along a side of the base material, and a first bond area is formed on the base material in which the via hole is formed. A second bond region for wire bonding the semiconductor chip of the second size disposed therein.
Ones arranged along the sides of the base material with each other.

According to the present invention, each of the conductor lines is a third bond region for wire bonding a semiconductor chip of a third size disposed further inside than the row of the second bond region. In addition, it is possible to further include ones that are mutually arranged along the side of the base material.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows one embodiment of the present invention.
FIG. 3 is a plan view of a substrate used for a 4-pin compatible BGA package. In the figure, on the surface of a rectangular insulating substrate 10,
Conductor patterns 11 made of copper or another metal are regularly arranged. The conductor pattern 11 can be obtained by a general method of laminating a metal foil on the insulating substrate 10 and removing unnecessary portions by a photolithography technique. Although the insulating substrate 10 is made of a flexible material such as a polyimide resin film in one embodiment, it may be made of a hard material such as a glass epoxy resin.

The conductor pattern 11 is basically composed of a large number of lines 12 electrically separated from each other. Each line 12 has a via hole 10 a formed in the insulating substrate 10.
The upper rectangular area, ie ball connection area 12
a. In some lines 12 (especially lines near the center of the substrate), the ball connection area 12a is located at one end of the lines, while in some other lines 12 (especially lines near the periphery of the substrate), It is located on the way. Therefore, from a different point of view, one or two narrow lines extend from the ball connection region 12a.

One narrow line extending from the ball connection region 12a passes between the other ball connection regions 12a and reaches four sides of the insulating substrate 10, and a first bond region 12b is formed on the line. Is formed. The first bond regions 12b are arranged in a line outside the row of the outermost ball connection areas 12a. The portion of the line extending outside the first bond region 12b is used for contacting a probe at the time of an electrical characteristic test of a semiconductor chip mounted on a substrate. In one embodiment,
The first bonding region 12 is placed at a position 0.625 mm from the side of the substrate (5.375 mm from the center of the substrate) with respect to the 12 mm square insulating substrate.
b. In order to realize good wire bonding, the distance from the side of the semiconductor chip mounted on the substrate to the first bond region 12b needs to be at least 0.3 mm. Therefore, when wire bonding is performed using the first bond region 12b, a semiconductor chip up to about 10.15 mm square can be mounted.

In the present invention, each line 12 further includes a second
Has a bonding region 12c. Second bond region 12c
Are ball connection areas 12a in the second and third rows from the outside
Are arranged side by side in a row. In one embodiment, the second bond region 12c is arranged at a position 3.6 mm from the center of the substrate. In this case, the second bond region 12c can be used for bonding a semiconductor chip having a size of about 6.6 mm square or less. In some lines, the second bond region 12c is disposed on the line on which the first bond region 12b extending from the ball connection region 12a is disposed, that is, between the ball connection region 12a and the first bond region 12b. In some other lines, it is arranged at the tip of the other line extending from the ball connection area 12a. In the embodiment, the width of each line 12 is 30 μm, and the size of the ball connection region 12a is 0.475 × 0.47.
5 mm, the size of the first and second bond regions 12b and 12c is 0.1 × 0.15 mm.

FIGS. 2 and 3 show a semiconductor chip 1 using an outer bond region, that is, a first bond region 12b.
3 shows an example in which the device 3 is mounted on an insulating substrate 10.
In the figure, the semiconductor chip 13 is in the second bond region 1
It has a larger planar size than the area surrounded by 2c. Each electrode pad 13a of the semiconductor chip 13 is electrically connected to the first bond region 12b by a conductor wire 14.

FIGS. 4 and 5 show an example in which the semiconductor chip 13 is mounted on the insulating substrate 10 using the inner bond region, that is, the second bond region 12c. In the figure, the semiconductor chip 13
Has a smaller planar size than the region surrounded by the bond region 12c. Each electrode pad 13a of the semiconductor chip 13 is electrically connected to the second bond region 12c by a conductor wire 14.

The embodiment of the present invention has been described with reference to the drawings. Obviously, the scope of application of the present invention is not limited to the items shown in the above embodiment. In the embodiment, the substrate having the inside and outside, that is, the substrate having the first and second bond regions is shown.
By forming the bond region of the above, the substrate can be configured so that a semiconductor chip of a smaller size can be mounted. Further, the arrangement, shape, dimensions, and the like of the conductor patterns shown in the above embodiment are merely embodiments of the present invention, and can be variously changed depending on the number and arrangement of the solder balls. For example, the ball connection region 12a is formed in the vicinity of the via hole 10a on the surface of the insulating substrate 10 on which the solder balls are mounted, that is, on the side opposite to the surface on which the bond regions 12b and 12c are formed, and the solder balls are mounted thereon. Is also good. In this case, the ball connection region 12a and each bond region are electrically connected via the via hole 10a.

[0018]

As described above, according to the present invention, a semiconductor chip of a plurality of sizes can be mounted on a substrate for a BGA package. By using a common substrate for multiple types of semiconductor chips,
The mass production cost of the semiconductor device can be reduced.

In this case, by properly using the first or second bond region according to the size of the semiconductor chip, the length of the conductor wire can be kept to a certain value or less, and the problem of short-circuit between wires during mold injection is avoided. Is done. Also,
Short conductor wires are preferred because they have better electrical properties than long conductor wires.

[Brief description of the drawings]

FIG. 1 is a plan view of a substrate used for a BGA package according to an embodiment of the present invention.

FIG. 2 is a plan view showing an example in which a semiconductor chip is mounted on an insulating substrate using an outer bond region.

FIG. 3 is a sectional view of the semiconductor package corresponding to FIG. 2;

FIG. 4 is a plan view showing an example in which a semiconductor chip is mounted on an insulating substrate using an inner bond region.

FIG. 5 is a sectional view of the semiconductor package corresponding to FIG. 4;

FIG. 6 is a cross-sectional view of a conventional general BGA package semiconductor device.

FIG. 7 shows a state where a resin package material is removed;
3 is a plan view of the semiconductor device of FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Insulating substrate 10a Via hole 11 Conductor pattern 12 Line 12a Ball connection region 12b First bond region 12c Second bond region 13 Semiconductor chip 13a Electrode pad 14 Conductor wire

Claims (5)

[Claims] 1. A BGA package substrate on which a semiconductor chip of a first or second size can be mounted, wherein a first surface on which the semiconductor chip is mounted and a plurality of solder balls are two-dimensionally mounted. An insulating base material having a second surface and a via hole corresponding to the solder ball, and a pattern comprising a plurality of electrically separated conductor lines, A first line for wire-bonding a semiconductor chip of the first size, in which a line is disposed outside a region on the substrate on which the via hole is formed, and a ball connection region electrically connected to the solder ball. A first bond region, which is arranged along the side of the base material and a second size semiconductor chip disposed in the region on the base material where the via hole is formed; A second bonding area for loading a substrate for a BGA package which includes a those arranged along the sides of each other on the substrate, the. 2. The semiconductor device according to claim 1, wherein each of the conductor lines is a third bond region for wire bonding a semiconductor chip of a third size disposed further inside than a row of the second bond region. 2. The substrate for a BGA package according to claim 1, further comprising a substrate arranged along a side of said base material. 3. The ball connection region is a substantially rectangular region covering the via hole, and each of the bond regions is connected to the ball connection region by a thin line.
Or the substrate for a BGA package according to 2. 4. The substrate for a BGA package according to claim 3, wherein the rows of the second bond areas are arranged between rows of adjacent ball connection areas. 5. A BGA package comprising the substrate according to claim 1, 2, 3 or 4.