JP2000067599A - Two-pass multiple state parallel test for semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To dispense with an output driver having three states by supplying one pair of test result values fed from a parallel data testing circuit,which is included in a semiconductor memory device, to an open-drain output driver and driving the output of the driver with a sequential method in two states. SOLUTION: In a test mode, a compression circuit 318 to which a line I/O0 to a line I/O7 are connected provides two compared output signals by comparing data on I/O lines with predetermined logical values. One of these two signals is inputted to a test data state circuit 320, which provides a DATA-TEST signal. Moreover, the two signals are inputted to a passing/failure circuit 322, which provides a PASS signal, The DATA-TEST signal and the PASS signal are inputted to a two-bit register 312 respectively. An open-drain out-put driver 314 drives an output DQ based on a DATA-TEST value and a PASS value which are outputted in series.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to a test circuit for a semiconductor device, and more particularly to a circuit for providing internal test result data on an output pin of the semiconductor device.

[0002]

2. Description of the Related Art Semiconductor memory devices typically include one or more memory arrays, each of which includes a number of memory cells. In the standard mode, a selected memory cell is accessed in response to an applied address, and a specified arithmetic operation can be performed (eg, a read, write, program or erase operation). The memory cells are typically logically arranged in input / output (I / O) groups such that the applied address is one memory cell accessed from each I / O group. . For example, if the memory element includes 128 I / O groups, the applied address will access one memory cell from each of the 128 I / O groups. The selected 128 memory cells are then selected depending on the data width of the memory element. That is, when the memory element has a data width of 8 bits, the output data path is prepared for only 8 bits out of 128 bits. Such an arrangement may also enable a "prefetch" architecture. In a prefetch architecture, all 128 memory cells are accessed simultaneously and the datapath is applied sequentially according to the data width of the device. For example, in a read operation of a memory device having a 32-bit data width, data from 128 memory cells is accessed in a single cycle and output 32 bits at a time in the following four clock cycles.

[0003] While the process of manufacturing semiconductor devices continues to improve, the size and the operating speed continue to decrease at the same time. Accordingly, manufacturing defects are more likely to occur during attempts to manufacture smaller and faster devices. To ensure that defective devices are not provided to consumers, semiconductor devices are usually tested to ensure their function. Many such tests involve writing data to and reading data from each memory cell in a semiconductor memory device. Due to the large number of memory cells in a semiconductor memory device, if such tests were performed using conventional access operations, a very long time would be required to test each memory cell in the memory device. Time is needed.

[0004] To reduce the time required to test semiconductor memory devices, many memory devices include "on-chip" test circuits. That is, instead of having a test device, which generates all possible addresses and compares the result data with the test data, the circuit on the memory element itself can test the memory cell and provide a data output reflecting the test result I do. A prior art on-chip test structure for a semiconductor memory device is shown in FIG.

Referring now to FIG. 1, a prior art semiconductor memory device having an on-chip test circuit is indicated generally by the reference numeral 100. Memory device 100 includes a core array 102, which has a number of memory cells arranged in one or more arrays. The prior art memory device 100 of FIG. 1 is a synchronous dynamic random access memory (DRAM) that receives a conventional input signal, which is a system clock signal (CLK),
A row address strobe signal (RAS_), a column address strobe signal (CAS_), a write enable signal W_, and an address signal (ADD) are included. The input signal is received by the instruction decoder 104. Instruction decoder 104 generates an internal control signal, which is an internal row address strobe signal (I
NT_RAS), an internal column address strobe signal (IN
T_CAS) and an internal address signal (INT_AD)
D). In addition, the instruction decoder 104 outputs a test mode signal (TEST_MODE), an output enable signal (OE0),
And an internal clock signal (INT_CLK).

In accordance with the applied control signals, core array 102 provides access to the selected memory cell via a number of data I / O lines (I / O0-I / O7). In the configuration of FIG. 1, the specific memory cell is INT
It is accessed by the INT_ADD signal according to the timing established by the _RAS and INT_CAS signals. The data I / O lines (I / O0-I / O7) are coupled to a standard data path 106 and a test data path 108. To avoid excessive congestion in FIG. 1, the standard data path 106 shows only the data path to line I / O0. The standard data path 106 is the data state circuit 1
10 are shown. Data state circuit 110
Receives the standard enable signal STD_EN signal and the I / O0 line as inputs and outputs the standard data signal output DATA
_STD. When the OE0 signal is high, the data state circuit 110 drives its output DATA_STD based on the I / O0 line signal. When the OE0 signal is low, the data state driver is set to a high impedance (hi-Z) state.

The output of data state circuit 110 is connected to the input of a complementary metal oxide semiconductor (CMOS) switch gate 112. Switch gate 112 provides a data input (DATA) to output driver circuit 114 when enabled. The switch gate 112 is enabled by the READ_CLK signal and its complementary READ_CLK_.

[0008] Output driver circuit 114 also receives a driver output enable signal (OE). When the OE signal is high, output driver circuit 114 drives the data output (DQ) according to the value of the DATA signal. When the OE signal is low, output driver circuit 114 is set to the hi-Z state. The output driver 114 shown in FIG. 1 is shown to include a CMOS driver stage, which includes a p-channel MOS transistor P100 and an n-channel MOS transistor N100. Two transistors (P1
00 and N100) are performed by the NAND gate G100, N
It is controlled by an OR gate G102 and an inverter I100. The DATA signal is applied as an input to gates G100 and G100.
The OE signal received at 102 is connected directly to gate G100 as a second input and through inverter I100 as the second input of gate G102. With this configuration,
When the OE signal is low, the output of G100 goes high and gate G
The output of 102 is low, resulting in transistor P1
00 and N100 become non-conductive. When the OE signal is high, D
When the ATA signal is high, transistor P100 conducts,
Further, the transistor N100 is turned off. When the DATA signal is low, transistor P100 is non-conductive and transistor N100 is non-conductive.

The STD_EN signal, READ_CLK and READ_CLK_ signal are provided from a control circuit 116. In standard operation mode (for example, reading operation), STD
_EN signal is high, READ_CLK and READ_C
The LK_ signal should be pulsed high and low, respectively. As a result, since the data is located on the I / O0 line, data state circuit 110 drives its output according to the logic of line I / O0. The switch gate 112 becomes conductive so that a DATA signal is generated from the logic on line I / O0. The DATA signal results in a DQ signal, which has the same logic as the DATA signal.

STD_EN, READ_CLK and RE
The AD_CLK_ signal is a TEST_MODE signal, OE
0 signal and the control circuit 11 according to the INT_CLK signal.
6 is generated. The control circuit 116 includes an inverter I10
It is shown to include a two- and three-input AND gate G104, a two-input AND gate G106, and a two-input NAND gate G108. The outputs of gates G104 and G106 provide an input to a two-input OR gate G110. Gate G104 receives the OE0 and TEST_MODE signals as inputs, plus a pass / fail indication (PASS).
Is received from the test data path 108. In a non-test operation (eg, a standard read operation), the TEST_MODE signal is low, so gate G104 provides a low output signal regardless of the state of the other inputs. TEST_MOD
The E signal is inverted by inverter I102 and provided as one input of gate G106. The other input of gate G106 is the OE0 signal. Thus, in the non-test mode, gate G106 provides an output that reflects the value of the OE0 signal. The output of gate G106 is the STD_EN signal.

The outputs of gates G104 and G106 are further provided as inputs to gate G110. Gate G11
The output of 0 is the OE signal. As a result of this structure, in the non-test mode, the OE signal reflects the OE0 value.

The OE0 signal is also one input of gate G108. The other input of the gate G108 is INT
_CLK signal. The output of gate G108 is READ
_CLK_ signal, which is further inverted at inverter I104 to produce the READ_CLK signal. INT_
Since the CLK signal is activated (transitioned high) in synchronization with the CLK signal, READ_CLK and READ_C
The LK_ signal can synchronize the switching circuit 116 with the CLK signal (when the OE0 signal is high).

Having described the operation of DRAM 100 in the "standard" mode of operation, the parallel test mode of DRAM 100, particularly FIG. 1, will now be described. In the test mode, the standard data path 106 is disabled to prevent I / O line data from reaching the switch gate 112. In particular,
When the TEST_MODE signal is high, the low input is gate G
106, and the output of the gate G106 (STD_E
N signal) is forced low. As a result of the STD_EN signal going low, the data state circuit 110 is set to the hi-Z state, essentially isolating line I / O0 from the switch gate 112.

In test mode, test data path 108 provides data to switch gate 112 as compared to standard data path 106. Test data path 108 is shown to include a "compression" circuit 118, which receives all of the I / O lines (I / O0-I / O7) as inputs,
Two comparison output signals, CMPB and CMPT, are provided as outputs. The compression circuit 118 has a line I / O0-I /
The test data is "compressed" by reducing the output value of O7 to two signals, CMPB and CMPT. This is performed by comparing the data of lines I / O0-I / O7 with a predetermined value. In particular, in the case of FIG. 1, if all of the lines I / O0-I / O7 are low, the CMPT signal goes high and the CMPB signal goes low. Conversely, line I /
When all of O0-I / O7 are high, the CMPT signal goes low and the CMPB signal goes high. Compression circuit 118 also indicates whether a test fail condition exists (ie, if not all of the I / O lines have the same logical value).
In such a case, both the CMPT and CMPB signals will be high.

In test data path 108, CMPT and C
The MPB signal is received by test data status circuit 120 and pass / fail circuit 122. Test data status circuit 120
And the pass / fail circuit 122 are both enabled by the TEST_MODE signal. When the TEST_MODE signal is low, test data status circuit 120 and pass / fail circuit 1
22 is set to the hi-Z state. TEST_MODE
When the signal is high, the test data status circuit 120 outputs DATA_
Provides a TST output signal, which is connected to the I / O line (I / O
0-I / O7). In particular, when the I / O lines (I / O0-I / O7) are all high (or when the test data indicates a fail condition), DATA_TS
The T signal goes high. I / O line (I / O0-I / O
When 7) are all low (and no test failure condition exists), the DATA_TST signal will be low.

The pass / fail circuit 122 includes CMPB and C
Using the MPT signal, the I / O line (I / O0-I / O
7) Determine if there is an error condition above. If a pass condition exists, the CMPB or CMPT signal will have a different logic value (correct test data has been received) and the output of pass / fail circuit 122 (PASS signal).
Is high. Conversely, when the CMPB and CMPT signals are both high (indicating test failure), the PASS signal is low.

The DATA_TST and PASS signals are used to provide an output data signal (DQ) reflecting a test result. As shown in FIG. 1, DATA_T
The ST signal is provided as one input of switch gate 112. Therefore, during the test operation, the output driver 114
Instead of following the data on line I / O0,
Drive is performed based on all logical values of the / O line (I / O0-I / O7). At the same time, the PASS signal is
6 which is used to enable the output driver 114. Thus, when the data test passes (PASS is high), output driver 114 is enabled and output DQ is on the I / O line (I / O0-I / O).
7) is driven high if all are high, or driven low if all of the I / O lines (I / O0-I / O7) are low. The data test may include one or more I / O lines (I / O0-I / O
7) When indicating above (PASS is low), output driver 114 is set to the hi-Z state. As shown in FIG. 1, the PASS signal is
16 is provided as one input to gate G104. Therefore, when the PASS signal is low, the output of gate G104 is forced low. At the same time, TEST_MODE
If the signal is high, the output of gate G106 is forced low. When the two inputs go low, the output of gate G110 (OE signal) goes low. When the low-level OE signal is supplied to the output driver 114, the output driver 114 is set to hi.
Set to -Z state.

Referring to FIG. 2, the DRAM 100 of FIG.
FIG. 2 is a timing diagram illustrating a test operation based on. At time t0, DRAM 100 sets RAS_, C
The test mode is entered by a predetermined combination of AS_, W_, and the ADD value. As a result, TES
The T_MODE signal is driven high. The INT_CLK signal follows the CLK signal. INT_RAS and INT_C
The AS signal remains low, but it is
This is because the S_ and CAS_ signals are mode establishment signals rather than timing signals. Since the access operation is not performed at time t0, the OE0 and OE signals are both low. The low OE0 signal holds the READ_CLK signal low. Since the test data has not yet been generated, both the PASS and DATA signals are low.

At time t1, DRAM 100 is in a test mode, so that a test row address (ADD) is supplied along with a low RAS_ signal. The INT_RAS signal is driven high, so that the selected memory cell is coupled to a bit line in core array 102. Subsequently, the data on the bit line is amplified.

At time t2, when the test data is successfully generated on the bit line, the test column address (AD
D) is provided with the CAS_ signal low. INT
The _CAS signal is driven high, thereby coupling the selected bit line to the I / O line (I / O0-I / O7). The resulting I / O line test data is compared to a predetermined data value in compression circuit 118 and the results (CMPB and CMPT signals) are provided to test data status circuit 120 and pass / fail circuit 122. You.

At time t3, test data state circuit 1
20 and the pass / fail circuit 122 is DATA_TST
And PASS values are provided as outputs. As described above, the DATA_TST signal is applied to the I / O line (I / O0-
I / O7) high or low depending on the value of PASS
The signal goes high or low depending on whether the data passed the test.

At time t4, the instruction decoder 104 causes the OE0 signal to transition high. As a result, OE and REA
The D_CLK signal goes high. If switch gate 112 is enabled and the PASS signal is high (I / O line data passed the test), the DQ output will be DATA_TST
Driven based on the value. If the PASS signal is low, output driver 114 will be in a hi-Z state.

At time t5, RAS_, CAS_,
A particular combination of W_ and ADD signals is provided;
The DRAM 100 is released from the test mode and returned to the standard mode.

In the method described above, the DRAM 100
Three DQ states are provided to display the test results: a high logic value indicates that all successfully read the high value, a low logic value indicates that all have successfully read the low value, and hi-
The Z state indicates that the I / O line data has failed the test.

The problems associated with the parallel test setup of FIG. 1 arise when different data transfer techniques are used. For example, some system bus structures require an "open drain" output driver (as opposed to the CMOS output driver of FIG. 1). In systems requiring an open drain output driver, rather than relying on a semiconductor device output driver driving the output between a high logic level and a low logic level, the open drain output driver has a low logic state and hi Drive output to and from -Z state. Thus, a high logic state is established on the bus, which includes a termination resistor connected between the data output and the termination voltage.
When the open drain output driver is in the hi-Z state,
The terminating resistor raises the output to a high logic level.

[0026]

[Problems to be solved by the invention] Open drain
Prior art parallel test circuits present test results (ie, pass or fail) as well as read test data values (ie, high or low) with one signal because the driver provides only two states instead of three. I can't do that. Open with semiconductor memory and other devices
In view of the use of a drain driver, some method will be needed to provide test data from a semiconductor device without the need for an output driver having three different states.

[0027]

According to a disclosed embodiment, a semiconductor memory device includes a parallel data test circuit, which generates a pair of test result values. This test result value is provided to one output of the semiconductor memory device. Instead of presenting test result data with one of the three states (ie, high, low or high impedance) set at the output, the present embodiment switches the output between the two states sequentially based on the test result value. Drive in a simple way.

As one feature of this embodiment, the output of the semiconductor memory device is driven by an open-drain output driver.

As another feature of this embodiment, the output of the semiconductor memory device is driven by a complementary metal oxide semiconductor (CMOS) output driver.

As another feature of the present embodiment, the semiconductor memory device includes a register for storing a test result value.

[0031]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First and second embodiments will be described.
Both embodiments provide test mode operation, wherein the results of the parallel data test are provided by generating two consecutive signals on the same data output. The first embodiment includes an output driver having an "open drain" structure. In the second embodiment, a complementary oxide (insulator) metal (conductor) semiconductor (CM)
OS) including an output driver. In both the first and second embodiments, the two successive output signals have first and second logical values, and the logical value of the data under test, as well as whether the data passed the parallel test. Indicate whether or not.

Referring now to FIG. 3, a first embodiment is shown as a schematic block diagram. The first embodiment is a dynamic random access memory (DRAM), indicated generally by the reference numeral 300. First embodiment 300
Includes a core array 302 having a number of DRAM cells arranged in a plurality of rows and columns. The DRAM cells are accessed with an external control signal application. The first embodiment 300 is a synchronous DRAM (SDRAM),
AM typical timing and control signals are received, including a system clock signal (CLK), a row address strobe signal (RAS_), a column address strobe signal (CAS_), and a write enable signal W_. A memory address (ADD) is provided along with timing and control signals to select a specified set of DRAM cells in the core array 302.

Timing and control signals (CLK, RA
S_, CAS_ and W_) as well as the address (ADD)
Are processed in the instruction decoder 304 to obtain a number of internal timing and control signals and one internal address (INT_
ADD). The internal timing and control signals are one internal row address strobe signal (INT_RA).
S) One internal column address strobe signal (INT
_CAS), one test mode signal (TEST_MOD)
E) One output enable signal (OE0) and one internal clock signal (INT_CLK). The core array 302 functions in a conventional manner, coupling rows of memory cells to bit lines in response to an active (high) INT_RAS signal and a supplied row address (INT_ADD). The selected bit line then receives the data I /
Active INT is connected to the O line (I / O0-I / O7).
_CAS signal and the supplied column address (INT_AD
D).

The I / O lines (I / O0-I / O7) are coupled to a standard data path 306 and a test data path 308. For simplicity, standard datapath 306 includes only datapaths for lines I / O0 and I / O1. Standard data path 306 is shown to include a first data state circuit 310a coupled to the I / O0 line and a second data state circuit 310b coupled to the I / O1 line. Each data state circuit (310a and 310b) receives a respective I / O line (I / O0 or I / O1) as one input and receives a standard enable signal STD_.
An EN signal is received as a second input. When the STD_EN signal is active (high), it is connected to lines I / O0 and I / O
It reflects the logic state of O1. When the STD_EN signal is low, the first and second state circuits (310a and 3)
10b) is set to a high impedance (hi-Z) state.

The DATA0 and DATA1 signals are provided as inputs to a 2-bit register 312. Two bit register 312 also receives the READ_CLK signal.
The output of the 2-bit register 312 is a register output signal DA
TA_OUT. 2 bit register 312 is DAT
A0 and DATA1 values are stored, and they are sequentially output based on the READ_CLK signal to generate DATA_OUT
Generate a signal. Therefore, DATA0 and DATA1 are received in a parallel fashion and are essentially two-bit registers 312
Is output in serial form.

The DATA_OUT signal is provided to an open drain output driver 314. Open drain output driver 314 is a single n-channel M in FIG.
Expressed as an OS transistor (N300),
One drain, DATA_OU, coupled to output DQ
It has one gate for receiving the T signal and one source coupled to the low power supply voltage (VSS). FIG.
Also includes a representation of the data bus termination structure.
The termination structure includes a termination resistor Rterm, which couples the DQ output to a termination voltage Vterm. As will be appreciated, the termination structure is external to the DRAM in the particular configuration of FIG. Open-drain output driver 314 can result in only two data states. DATA_
When the OUT signal is high, the DQ output is pulled low (VS
S). When the DATA_OUT signal is low, the open drain output driver 314 provides a hi-Z state, and the termination structure pulls the DQ output towards the Vterm voltage.

During a standard (non-test) read operation, the core array 302 is accessed with conventional RAS_, CAS_ and address sequence applications, resulting in data being set on lines I / O0-I / O7. ST
The D_EN signal is driven high, enabling the first and second data state circuits (310a and 310b) and the DAT
The values of A0 and DATA1 are respectively I / O lines I / O
It is driven according to the logical values of 0 and I / O1.
The values of DATA0 and DATA1 are stored in the 2-bit register 3
12 is stored. Then, when the READ_CLK signal pulse goes high, the DATA_OUT signal
It is driven at the TA0 value and then at the DATA1 value.

The STD_EN and READ_CLK signals are the TEST_MODE signal, the OE0 signal, and the INT signal.
Generated by the control circuit 316 in response to the _CLK signal.
The control circuit 316 includes one inverter I300, one two-input AND gate G300, and another two-input AND gate G300.
302 is shown. TEST_MODE
The signal is inverted by inverter I300 and G is input as one input.
300. Another input to gate G300 is O
This is the E0 signal. The resulting output from gate G300 is the STD_EN signal. Gate G302 is OE
0 signal and the INT_CLK signal as inputs,
Provide the EAD_CLK signal as an output. In standard mode, the TEST_MODE signal is low;
The _EN signal goes high in response to the OE0 signal going high.

The various circuits used during the standard reading operation have been described so far. Next, the circuits used in the parallel test mode will be described. In the test mode, the standard data path 306 is disabled, preventing data from lines I / O0 and I / O1 from reaching the 2-bit register 312. In particular, when the TEST_MODE signal transitions high, gate G300 should drive the STD_EN signal low. This forces the first and second data state circuits (310a and 310b) to hi.
-Z state.

In the test mode, test data path 308 provides test data to 2-bit register 312 instead of I / O line (I / O0 and I / O1) output data. In the test data path 308, the line I / O0-I
/ O7 is coupled to compression circuit 318. I / O0-
In response to the logic of the I / O7 logic value, compression circuit 318 provides two compare output signals CMPB and CMPT. C
The MPB and CMPT signals are supplied to I / O lines (I / O0-
I / O7) represents a result of comparison between the data on I / O 7) and a predetermined logical value. In the first embodiment 300, it is assumed that the I / O lines (I / O0-I / O7) all have the same logical value (either high or low) in a test operation. Therefore, the line I / I is supplied to the compression circuit 318 in FIG.
When all of O0-I / O7 are low, the CMPT signal is high and the CMPB signal is low. Conversely, line I / O0-I /
If all of O7 are high, CMPT signal is low and CMPB
The signal goes high. Finally, if an error condition exists,
Since the I / O line (I / O0-I / O7) values are different,
Both the CMPB and CMPT signals will be high.

Returning to FIG. 3, test data path 308 further includes a test data status circuit 320 and a pass / fail circuit 322.
Are included. Test data status circuit 320
Receives the CMPB signal and the TEST_MODE signal as inputs. Pass / fail circuit 322 includes CMPT, CM
The PB and TEST_MODE signals are received as inputs. The test data status circuit 320 and the pass / fail circuit 322 are both enabled by the TEST_MODE signal. When the TEST_MODE signal is low, it indicates a non-test mode (eg, a standard read operation), and the test data status circuit 320 and the pass / fail circuit 322 are set to the hi-Z state. However, when the TEST_MODE signal is high, test data is provided by the test data status circuit 320 and the pass / fail circuit 322. In particular,
Test data circuit 320 provides a DATA_TST signal, which reflects the logic value of the I / O lines (I / O0-I / O7). I / O line (I / O0-I / O
If 7) are all high (or if the test data indicates a fail condition), the DATA_TST signal will be high. I / O
The lines (I / O0-I / O7) are all low (and if no test fail condition exists), the DATA_TST signal will be low. Pass / fail circuit 322 provides a PASS signal, which reflects whether the I / O line (I / O0-I / O7) data has passed the test. If the PASS signal is high, the test is successful. If the PASS signal is low, the data has failed the test.

As shown in FIG. 3, in the test mode, D
The ATA_TST and PASS values are provided as inputs to a 2-bit register 312 instead of the I / O line data from the first and second data state circuits (310a and 310b). The READ_CLK signal functions in the same manner as a conventional read operation. Thus, in test mode, open drain output driver 314 outputs the DQ output to DA rather than the I / O0 and I / O1 line values.
Drive based on TA_TST and PASS value. In this manner, the first embodiment 300 provides two serial test data bits (DATA_TST and PASS) as outputs in the test mode, which the prior art circuit of FIG. This is an alternative to setting one of these. The test mode configuration of FIG. 3 is particularly advantageous because many DRAMs already include an output register, such as a 2-bit register 312, for standard data output operation.

Referring now to FIG. 4, a first embodiment 300
A timing diagram illustrating the test operation of FIG. This timing diagram shows the timing and test signals (CLK,
RAS_, CAS_, W_ and ADD), which are provided to the first embodiment 300. Instruction decoder 304
(INT_RAS, INT_CA)
S, INT_ADD, TEST_MODE, OE0 and INT_CLK) are also shown. The other signals shown are READ signals provided from control circuit 316.
_CLK signal, also PA from test datapath 308
Includes the SS and DATA_TST signals, and the DQ output signal. Finally, FIG. 4 also includes a LOAD signal. In the first embodiment 300, the LOAD signal is an internal signal of the 2-bit register 312, and includes PASS and DATA.
The result is that the _TST signal is loaded into the 2-bit register 312.

At time t0, the input signals (RAS_,
CAS_, W_ and ADD) are provided to the first embodiment 300 to set the test mode. RAS_, CAS_, W_ and ADD are shown hatched since the combinations can be any number of combinations. The signal combination is interpreted by the instruction decoder 304, which activates the TEST_MODE signal and forces it high. TEST_MOD in high state
The E signal enables the test data status circuit 320 and the pass / fail circuit 322. T at high time at the same time
The EST_MODE signal is received at control circuit 316, which drives the STD_EN signal low. This causes the first and second data state circuits (310a and 310b) to
Set to i-Z state.

When the first embodiment 300 is in the test mode, at time t1, the test row address (ADD) is set to RAS_
Received with the signal. The INT_RAS signal is driven high so that one row of memory cells is coupled to a bit line in core array 302.

At time t2, the test column address (AD
D) is provided together with the column CAS_ signal in a multiplexed address manner. The INT_CAS signal is driven high, and the selected bit line determined by the supplied column address is coupled to the I / O line (I / O0-I / O7). The test data on the I / O line is compared with a predetermined data value in the compression circuit 318. Based on the comparison result, the compression circuit 318 determines whether the CMPB and the CMPT
Drive the signal high or low.

At time t3, the DATA_TST and PASS signals are driven according to the result of the data test operation. Although the DATA_TST and PASS signals are indicated by hatching, their values depend on test results.

At time t4, the instruction decoder 304
Drive the E0 signal high. The high state OE0 signal is
When the T_CAS signal transitions high, REA
Drive the D_CLK signal high. READ_CLK
When the signal is driven high, the LOAD signal also goes high, loading the PASS and DATA_TST values into the 2-bit register 312. Next, the READ_CLK signal is a PASS value followed by a DATA_TST value that causes the two-bit register 312 to output two values in order.

The open drain output driver 314 is essentially an inverting driver (ie, it receives the received D
The ATA_OUT value is inverted), so the two-bit register 312 of FIG. 3 provides an inverted output value. In particular, if all I / O lines (I / O0-I / O7) are high and the comparison test passes, two consecutive low values are output from the 2-bit register 312. If all I / O lines (I / O0-I / O7) are low and the comparison test passes,
Following the two low values, the high value is the 2-bit register 312
Output from If the comparison test fails (regardless of the I / O line value), two consecutive high values are output from the 2-bit register 312.

At time t5, another RAS_, CAS
The combination of _, W_ and ADD signals is the third embodiment.
00, which results in switching the first embodiment 300 from the test mode to the standard mode. As a result, T
The EST_MODE signal is driven low. TEST_M
When the ODE signal goes low, the pass / fail circuit 322 and the test data state circuit 320 are set to the hi-Z state. At the same time, the first and second data state circuits (310a
And 310b) are enabled to allow subsequent standard read operations to set the I / O line data from I / O0 and I / O1 into the 2-bit register 312.

Referring now to FIG. 5A, the first embodiment 30
The two bit register used in the 0 is shown in the schematic. The two-bit register is indicated generally by the reference numeral 500 and is shown to include a timing circuit 502, a load gate circuit 504, a first bit latch 506, a second bit latch 508, and a phase output gate 510. In addition, the two-bit register 500 also
Reset p-channel MOS transistors (P50
0 and P502). Timing circuit 502 provides timing signals for controlling various other portions of 2-bit register 500. In the embodiment of FIG. 5A, timing circuit 502 receives the READ_CLK signal and inverts the signal with inverter
Generate the D_CLK_ signal. The READ_CLK and READ_CLK_ signals are output to the phased output gate circuit 51.
0, also the first and second bit latches (506 and 5)
08). In addition, the timing circuit 502 generates a LOAD signal, which was previously described in conjunction with the timing diagram of FIG. LOAD of FIG. 5A
The signal is generated by a falling delay circuit including a delay circuit 512 and a two-input NOR gate G500. READ_C
The LK signal is provided without delay as one input to gate G500 and is provided with a delay to another input of gate G500. The delay is established in delay circuit 512. The output of gate G500 is an inverted load data signal LOAD_. The LOAD_ signal is output from the inverter I502.
And a LOAD signal is generated. This configuration results in a LOAD signal having a rising edge following the rising edge of the READ_CLK signal and having a falling edge delayed with respect to the falling edge of the READ_CLK signal.

The load gate circuit 504 has LOAD and L
It is activated by the OAD_ signal. In the embodiment of FIG. 5A, load gate circuit 504 includes two CMOS switching gates T500 and T502. When the LOAD signal is low (and LOAD_ is high), gates T500 and T502 are non-conductive and the test data signals (PASS,
DATA_TST) or I / O data signal (DATA
0 and DATA1) are prevented from being stored in the 2-bit register 500. However, the LOAD signal is pulsed high (and LOAD_ is pulsed low)
, The pair of input signals (PASS / DATA_TST or DATA0 / DATA1) are
Loaded into 0.

The output of gate T500 is coupled to first bit latch 506. The first bit latch 506 is 2
And two inverters (I504 and I506) and a CMOS switching gate T504. The output of inverter I506 is coupled to the input of inverter I504. The output of inverter I504 is coupled to the input of inverter I506 at switch gate T504. The switching gate T504 is READ_CLK
Non-conducting when the signal is high. Therefore, READ_CLK
When the signal is high, inverters I504 and I506 form a latch.

The output of gate T502 is coupled to second bit latch 508. The second bit latch 508 is similar to the first bit latch 506, with two inverters (I508 and I510) and a CMOS switch gate T5.
06 has the same schematic configuration as the first bit latch 506.
The second bit latch 508 differs from the first bit latch 506 in that the switching gate T506 conducts when the READ_CLK signal is low.

The phased output gate circuit 510 is the first CMO
It is shown to include an S output switching gate T508 and a second CMOS output switching gate T510. Switching gate T
508 couples the output of first bit latch 506 to register output 514, and switch gate T510 couples the output of second bit latch 508 to register output 514. Although the phased output gate circuit 510 is considered "phased",
That is, switch gate T508 is conductive when the READ_CLK signal is high, while switch gate T510 is
This is because conduction occurs when the D_CLK signal is low.

FIG. 5B shows READ_CLK and READ_C.
FIG. 4 is a timing diagram illustrating the relationship between LK_, LOAD and LOAD_ signals. In addition, the values provided at the register output DATA_OUT during the test operation are also shown. The operation of the Ak2-bit register 500 in FIG.
This will be described together with B. At time t0, READ_CL
The K signal is driven high and PASS and DATA_TS
The output of the T value is started. When the READ_CLK signal transitions high, the READ_CLK_ signal is driven low. As a result, switching gates T504 and T508 become conductive, enabling first bit latch 506 and coupling first bit latch 506 to register output 514.
At the same time, the READ_CLK, READ_CLK_ value turns off the switching gates T506 and T510, disables the second bit latch 508, and isolates the second bit latch 508 from the register output 514.

Further, at time t0, the RE
In response to the AD_CLK signal, the timing circuit 502 drives the LOAD signal high and the LOAD_ signal low. The switching gates T500 and T502 are both conducting,
The load gate circuit 504 is enabled. This allows the PASS value to be coupled to the first bit latch 506 and latched. Since the switching gate T508 is conducting, the latched PASS value is output from the register output 51.
4 (in inverted form). In this way, REA
At the beginning of the D_CLK pulse, the DATA_OUT signal provides a PASS value.

At time t1, the READ_CLK signal returns low, driving the READ_CLK_ signal high.
The LOAD signal stays high (and the LOAD_ signal stays low), so that the load gate circuit 504
And continue to provide the DATA_TST value to the 2-bit register 500. The switching gate T504 becomes non-conductive, disabling the first bit latch 506 and isolating the first bit latch 506 from the register output 514. At the same time, the switching gates T506 and T510 become conductive,
The DATA_TST signal is latched by second bit latch 508 and output on register output 514 (in inverted form). Thus, following the end of the READ_CLK pulse, the DATA_OUT signal provides the DATA_TST value.

At time t2, the LOAD signal returns low and the LOAD_ signal returns high after a specified delay after the end of the READ_CLK pulse. This delay is caused by delay circuit 5
It is established at 12. LOAD and L at time t2
The value of the OAD_ signal establishes the reset condition. LOAD
When the signal is low and the LOAD_ signal is high, load gate circuit 504 is disabled and PASS and DA
This prevents the TA_TST signal from being loaded into the 2-bit register 500. In addition, if the LOAD signal is low, transistors P500 and P502
Becomes conductive, pulling the inputs of the first and second bit latches (506 and 508) to a high (VCC) level. Since switch gate T510 remains conductive, the high input to second bit latch 508 is inverted by inverter I508,
As a result, a low is input to register output 514. Thus, in the reset state, the DATA_OUT signal is low.

Note that in the proposed two-bit register 500, inverters I504 and I510 are CMOS inverters. p-channel transistor P500
The gate lengths of the n-channel transistors in inverters I504 and I510 are non-standard to ensure a reset condition without data contention between P502 and P502 and their associated latch inverters (I504 and I510, respectively). .

Referring now to FIG. 6, a schematic diagram is shown, which is a compression circuit used in the first embodiment 500. The compression circuit is indicated generally by the reference numeral 600 and includes a "high" comparison pass and a "low" comparison pass. The high compare path has four two-input NAND gates (G600, G600, each receiving two different I / O lines as inputs).
G602, G604 and G606), two two-input N
OR gates (G608 and G610), and one two-input NAND gate G612. NOR gate G
608 receives the outputs of NAND gates G600 and G602 as inputs, and NOR gate G610 receives the outputs of NAND gates G604 and G606 as inputs. The outputs of gates G608 and G610 are provided as inputs to gate G612.

In the high comparison path configuration, the I / O line (I / O
0-I / O7) are high, the gates G600, G
The outputs of 602, G604 and G606 are all low. Since the inputs of gates G608 and G610 are all low, the outputs of gates G608 and G610 are high. Since the two inputs are high, the output of gate G612 (and thus CM
PT signal) is low. Thus, a low CMPT indicates that all values on the I / O line are high. In contrast, the I / O lines (I / O0-
I / O7) is low, the gate G60
0, at least one of G602, G604 and G606
One output will be high. This is the gate G608 or G6
Let at least one output of 10 be low. At least one
Since the two inputs are low, the output of gate G612 (CM
PT signal) goes high. In this manner, a high CMPT signal indicates that at least one of the I / O lines (I / O0-I / O7) is low, failing all high output tests. It means that some or all outputs are low.

The low compare path has two different I / Os each
Includes four two-input NOR gates (G614, G616, G618 and G620) that receive lines as inputs. NAND gate G622 receives as inputs the outputs of NOR gates G614 and G616. Another NAND gate G624 receives as inputs the outputs of NOR gates G618 and G620. The outputs of gates G622 and G624 are provided as inputs to a two-input NOR gate G626. The output of gate G626 is inverted by inverter I600 to generate a CMPB signal.

In the low comparison path configuration, I / O lines (I / O
0-I / O7) are low, the gates G614, G614
The outputs of 616, G618 and G620 are all high. Since the inputs of gates G622 and G624 are all high, the outputs of gates G622 and G624 are low. Since the two inputs are low, the output of gate G626 is driven high. This high value is inverted by inverter I600 to produce a low CMP
Generate a B signal. Thus, a low CMPB signal indicates that all values on the I / O line are low. In contrast, the I / O lines (I / O0-
I / O7) is high when at least one of the gates G61
4, G616, G618 and G620
One output will be low. This is the gate G622 or G6
24 at least one output is high. At least one
Since one input is high, the output of gate G626 is low. This low value is inverted by inverter I600 to produce a high CMP
Generate a B value. In this way, a high CMPB signal indicates that at least one of the I / O lines (I / O0-I / O7) is high, failing all low output tests. It means that some or all I / O lines are high.

Referring now to FIG. 7, a schematic diagram is presented which illustrates the pass / fail used as the pass / fail circuit shown as item 322 in the first embodiment 300.
4 shows a reject circuit. The pass / fail circuit is indicated generally by the reference numeral 700 and includes two p-channel MOS transistors (P700 and P702) and two n-channel MOS transistors (N700 and N702) connected in series. It is shown. The two-input NAND gate G700 receives the CMPT and CMPB signals as inputs, and
0 and the output coupled from the gate of N702. T
The EST_MODE signal is sent directly to the gate of transistor N700 and to transistor P702 via inverter I700.
Is supplied to the gate. Transistor P702 and N
A drain-drain connection at 700 is provided as an input to inverter I702. The output of inverter I702 is P
ASS signal.

In operation, the pass / fail circuit 700 is enabled by the TEST_MODE signal going high. Once enabled, the PASS signal is driven high or low depending on the configuration of the CMPB and CMPT signals. In particular, if the CMPB and CMPT signals are different (one high and one low), the output of gate G500 will be high, resulting in a high PASS signal. However, if the CMPB and CMPT signals are both high, the output of gate G500 will be low, resulting in PAS
The S signal transitions low.

FIG. 8 presents one example of a data state circuit used in the first embodiment 300. 8 is the first data state circuit 310a, the second data state circuit 310b, or the test data state circuit 32.
Can be used as 0. Therefore, if the data state driver is 2
Two input signals, DATA_IN and EN, and the resulting output signal DATAx will be described. For the first data state circuit 310a, the DATA_IN input, the EN input, and the DATAx output are considered to correspond to the I / O line, the STD_EN signal, and the DATA1 signal, respectively. Similarly, for the second data state circuit 310b, D
The ATA_IN input, EN input and DATAx output are I
/ O line, STD_EN signal, and DATA0 signal, respectively. For the test data state circuit 320, the DATA_IN input, EN input and DATAx output are the CMPB signal, TEST_MODE
Signal and the DATA_TST signal, respectively.

In FIG. 8, the data state circuit is designated generally by the reference numeral 800 and includes two serially connected data states.
It is shown to include two p-channel MOS transistors (P800 and P802) and two n-channel MOS transistors (N800 and N802). Inverter I800 receives the DATA_IN input and a 1 coupled to the gates of transistors P800 and N802.
Has two outputs. The EN input is connected directly to the gate of transistor N800 and through transistor I802 to transistor P
802. Transistor P80
2 and the drain-drain connection of N800 provide a DATAx output.

In operation, data state circuit 800 provides E
The N input is enabled by being high, which makes transistors P802 and N800 conductive. When enabled, the DATAx logic level is either high or low D
It is driven depending on the value of the ATA_IN input. For example,
When the DATA_IN signal is high, transistor P800 is conducting and transistor N802 is non-conducting and DA
Drive the TAx output high. Conversely, when the DATA_IN signal is low, transistor P800 is non-conductive and transistor N802 is conductive, driving the DATAx output low.

While the first embodiment 300 can be effectively used for an open drain type output driver, the first embodiment 300
The teaching of 00 can also be applied to semiconductor devices using other types of output drivers. As one example, a second embodiment is presented in FIG.
A semiconductor memory device having a MOS output driver is shown. This second embodiment provides test result data as a serial configuration of test data bits, rather than setting the output (DQ) to one of three states.

The second embodiment is indicated generally by the reference numeral 900 and is shown to include many circuit configurations similar to the first embodiment 300. In that regard, similar circuit configurations are indicated by the same reference numbers as in FIG. 3, except that the first number is “9” instead of “3”. Accordingly, referring to FIG. 9, the second embodiment 900 has the same configuration as the first embodiment 300, but instead of the open drain output driver, the second embodiment includes a CMOS output driver 924.

The second embodiment 900 differs from the first embodiment 300 in that it also includes a two-bit register 926.
As in the first embodiment 300, the two-bit register 926 of the second embodiment 900 has a value 2 depending on the operation mode.
Receive a combination of two bits. In normal mode of operation, DATA0 and DATA1 signals are received, each reflecting the value of two I / O lines. When the operation is in the test mode, the PASS and DATA_TST values are received, which reflects the result of the test operation. However, unlike the 2-bit register 312 of FIG.
Does not invert the value. This is the open drain output driver 31 of the first embodiment 300.
4 functions as an inverting driver, while the CMOS output driver 924 functions as a non-inverting driver. In response to the READ_CLK pulse, 2-bit register 926 stores its two input values (DATA0 / DATA1).
Or PASS / DATA_TST) in serial form.

The CMOS output driver 924 receives the OE0 signal in the same manner as the register output (DATA_OUT). When the OE0 signal is high, the CMOS output driver 924
Drives the data output (DQ) based on the value of the DATA_OUT signal. When the OE0 signal is low, the output driver 9
24 is set to the hi-Z state. In this way CMO
The S output driver 924 can provide three states; a logic high, a logic low, or a hi-Z state. Note, however, that not all three states are used to indicate test results.

The CMOS output driver 924 of FIG. 9 is shown to include a CMOS driver stage having one p-channel MOS transistor P900 and one n-channel MOS transistor N900 with a source-drain path connected in series. I have. Transistor P9
The gate of 00 is driven by a two-input NAND gate G904. NAND gate G904 receives the DATA_OUT signal as one input and the OE0 signal as another input. The gate of the transistor N900 is driven by a two-input NOR gate G906. NOR gate G
906 receives the DATA_OUT signal as one input. As a second input, the gate G906 inverts OE0 with the inverter I902 and receives it.

The compression circuit 600 shown in FIG. 6, the pass / fail circuit 700 shown in FIG. 7, and the data state circuit 800 shown in FIG. 8 are used in the second embodiment 900. Please be careful.

Referring now to FIG. 10, a two-bit register is presented as a schematic diagram. The two-bit register is used in the second embodiment 900. The two-bit register is indicated generally by the reference numeral 1000 and is shown to include many of the circuitry of FIG. 5A. In this regard, similar circuit configurations are referenced with the same reference numbers, except that the first number is "10" instead of "5". Thus, as presented in FIG. 10, the two-bit register 1000 has the READ_CLK
Signal and a pair of input values (DATA0 / DATA1 or P
ASS / DATA_TST). The timing circuit 1002 has the same general timing pulse (READ_CLK,
READ_CLK, LOAD and LOAD_). The load gate circuit 1004 is LOAD and LOAD
Load a data value in response to the _ signal. The phased output gate circuit 1010 outputs one data value (DATA or PASS) when the READ_CLK signal is high and R
Provide another value (DATA1 or DATA_TST) when the EAD_CLK signal is low.

The 2-bit register 1000 shown in FIG.
The difference from A is that it includes a first bit latch 1016 and a second bit latch 1018, but does not invert their received values. In particular, the first bit latch 1016
Is connected in series from the output of the switching gate T1000.
It includes two inverters I1012 and I1014. Inverter I1
012 is output by a latch switching gate T1012.
It is connected back to the output of the switching gate T1000.
Similarly, the second bit latch 1018 is connected to the switching gate T100
It has the same general structure for two outputs and includes two inverters (I1016 and I1018) and a latch switch gate T1014. Further, the second embodiment 900 is OE0
CMOS output driver 92 set to hi-Z state at
4, the 2-bit register 1000 does not need to be set to the reset state. Therefore, 2-bit register 1000 is a p-channel MOS transistor (eg, P500 and P500 in FIG.
502) is not included.

The 2-bit register 1000 shown in FIG.
A and similar to those shown in FIG. 5B. READ
When the _CLK signal pulse is high, the LOAD signal goes high and the data value is coupled into the 2-bit register 1000. Switch gate T1008 is conductive, and the resulting data is latched in first bit latch 1016 and output on register output 1014. Switching gate circuit 10
10 is non-conductive, isolating the value in the second bit latch 1018 from the register output 1014. READ_CL
When K returns low, the LOAD signal remains high due to the delay established in delay circuit 1012. Switching gate T10
08 is non-conductive, isolating the first bit latch 1016 from the register output 1014. However, at the same time,
The second bit latch 1018 is enabled and the second bit latch 1018 latches this value. The switching gate T1010 becomes conductive, and outputs the value of the second bit latch 1018.

Although the present invention has been described with reference to a detailed dynamic random access memory (DRAM) embodiment, the teachings presented herein provide a test arrangement for compressing test data and providing the test data to an output. The present invention is also applicable to other types of semiconductor devices having Further, while the two embodiments have two bits of test data, the teachings presented herein could have a larger number of test data bits by increasing the size of the registers. Therefore, it should be understood that various changes, substitutions, and alterations can be made without departing from the spirit and scope of the invention as defined in the appended claims.

The following items are further disclosed with respect to the above description. (1) a test circuit for a semiconductor device: a test circuit for receiving a plurality of data signals and comparing the data signals with a predetermined value to generate a plurality of test data values;
A register for receiving the test data values in parallel and providing the test data values to the register output in a sequential format; coupled to the output node, receiving the sequential test data values, and outputting the test data values to the output node unit based on the test values. An output driver for establishing a logical value in a simple format.

(2) In the test circuit according to item 1, the output driver establishes two logical values at the output node, and the first logical value is established by representing a high impedance state to the output node. , The second logic value being established by driving the output node to a first logic potential.

(3) In the test circuit of paragraph 1, the output driver establishes two logical values at the output node, the first logical value is established by driving the output to the first voltage,
The test circuit, wherein the second logic value is established by driving the output node to a second voltage.

(4) A parallel test circuit in a semiconductor memory device having an open drain driver circuit, comprising: a memory cell array; a plurality of input / output (I / O) lines coupled to the memory cell array; A plurality of I /
A test circuit coupled to the O line and including comparison logic for comparing a logic value on the I / O line to a predetermined logic value to generate at least one first test value and one second test value; An output driver coupled to the output node, having a controllable impedance path coupled between the output node and the first logic voltage, the controllable impedance when a first logic value is received at the driver input; An output driver for setting the path to a high impedance state and setting to a low impedance state when a second logical value is received at the driver input; and a register for receiving a control clock, the register being coupled to the first test value. A first latch, a second latch coupled to the second test value, a first latch coupled to the driver input with the first control clock value, and a second latch coupled to the driver input. Binds with your clock value, and a phase of an output circuit, and a said register, the parallel test circuit.

(5) In the parallel test circuit according to item 4, the first test value indicates the polarity of the I / O line, and the second test value indicates the predetermined logical value of the I / O line. The parallel test circuit, which indicates whether or not the parallel test is performed.

(6) In the parallel test circuit according to item 4, the register is further coupled to a first test value during the test mode and to one of the I / O lines during the standard mode. The parallel test circuit including a latch and a second latch coupled to a second test value during a test mode and coupled to another I / O line during a standard mode.

(7) A semiconductor memory device 300 having a parallel test circuit is disclosed. The test data path is parallel I
/ O line (I / O0-I / O7) values and receive test result data values (PASS and DATA_TST) therefrom
Generate Test result data value (PASS and DATA
_TST) are coupled to a two-bit register 312 and are sequentially connected to the open-drain output driver 3
14 is output. In this manner, the test result data value is not a method of setting the output to one of three states at a time (eg, a logic high state, a logic low state, or a high impedance state), but rather the output (DQ) at a high speed. To be driven in a sequential manner.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram illustrating a prior art DRAM having a parallel test function and a CMOS output driver.

FIG. 2 is a timing diagram illustrating a test operation of the DRAM according to the prior art shown in FIG. 1;

FIG. 3 is a schematic block diagram of the first embodiment.

FIG. 4 is a timing chart illustrating the operation of the first embodiment.

FIG. 5 shows details of the first embodiment, wherein A is a schematic diagram illustrating a 2-bit register used in the first embodiment, and B is a timing selected by the 2-bit register of FIG. 5A. FIG. 4 is a timing chart illustrating signals.

FIG. 6 is a schematic diagram illustrating a compression circuit used in an embodiment.

FIG. 7 is a schematic diagram illustrating a pass / fail circuit used in an embodiment.

FIG. 8 is a schematic diagram illustrating a data state circuit used in an embodiment.

FIG. 9 is a schematic block diagram of a second embodiment.

FIG. 10 is a schematic diagram illustrating a 2-bit register used in the second embodiment.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 memory element 102 core array 104 instruction decoder 106 standard data path 108 test data path 110 data state circuit 112 switching gate 114 output driver circuit 116 control circuit 120 test data state circuit 122 pass / fail circuit 300 first embodiment 302 core array 304 Instruction decoder 306 Standard data path 308 Test data path 310a First data state circuit 310b Second data state circuit 312 2-bit register 314 Open / drain output driver 316 Control circuit 318 Compression circuit 320 Test data state circuit 322 Pass / fail circuit 500 2-bit register 502 Timing circuit 504 Load gate circuit 506 First bit latch 508 Second bit latch 510 Phased output gate circuit 512 Delay circuit 514 Register output 700 Pass / fail circuit 800 Data status circuit 924 CMOS output driver 926 2-bit register 1000 2-bit register 1002 Timing circuit 1014 Register output 1016 First bit latch 1018 Second bit latch

Continuation of the front page (72) Inventor Ronald Jay. Addison Place, Texas, Sugar Land, Texas 114 (72) Inventor Pow Chair Chang Singapore, Bendemir Road 990

Claims (2)

[Claims] A test circuit for receiving a plurality of data signals and comparing the data signals with a predetermined value to generate a plurality of test data values; A register for receiving the data values in parallel and providing the test data values to the register output in a sequential format; coupled to the output node, receiving the sequential test data values, and outputting to the output node unit a sequential test data value. An output driver for establishing a logical value in a format. 2. A parallel test circuit in a semiconductor memory device having an open drain driver circuit, comprising: a memory cell array; a plurality of input / output (I / O) lines coupled to the memory cell array; Multiple I / O
A test circuit coupled to the I / O line and comparing the logical value on the I / O line with a predetermined logical value to generate at least one first test value and one second test site; An output driver coupled to the output node, having a controllable impedance path coupled between the output node and the first logic voltage, the controllable impedance path when a first logic value is received at the driver input; A high impedance state, said output driver setting a low impedance state when a second logic value is received at the driver input; and a register for receiving a control clock, said register being coupled to the first test value. A first latch, a second latch coupled to the second test value, a first latch coupled to the driver input with the first control clock value, and a second latch coupled to the driver input. Binds with your clock value, and a phase of an output circuit, and a said register, the parallel test circuit.