JP2000067584A - Mode register and non-volatile semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a mode register and a non-volatile semiconductor memory which can set various default values in accordance with request of a user without burden of an additional process. SOLUTION: An element 110 permitting a first program is connected between a PMOS transistor MP100 connected to power source voltage VCC and a node N10. An element 120 permitting a second program is connected between a NOMOS transistor MN100 connected to ground VSS and the node N10. A default value of a signal MDST can be set to a high level or a low level by setting one side and the other side of these programmable elements to a on-state and off-state utilizing a program and the like of a memory element.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit device, and more particularly, to a programmable mode register of a synchronous memory device. Further, the present invention relates to a nonvolatile semiconductor memory device having a programmable mode register.

[0002]

2. Description of the Related Art As is well known in the art, in order for a synchronous memory device to operate in synchronization with a clock signal, the synchronous memory device has a default value of a mode register provided by the synchronous memory device. Must be set before entering the steady mode of operation. If the default value of the mode register is not set, the synchronous memory device cannot perform a steady operation.

To ensure steady operation of the memory device, first, a user supplies an address having mode information to a mode register after power-up and before operation in a steady operation mode. In general, the RAS wait time (latency), CAS wait time, burst type, burst length, and the like are programmed in the mode register. However, generally, the value of the mode register set after power-up is continuously used.

Referring to FIG. 1, a circuit diagram showing a conventional general mode register 10 is shown. In FIG. 1, the signal PVCCH indicates a power level. The signal PVCCH has a logic low level when the power supply voltage is lower than a predetermined level, and has a logic high level when the power supply voltage is higher than the predetermined level. The signal nPVCH is a complementary signal of the signal PVCCH.

When the signal PVCCH is at a logic low level, the PMOS and NMOS transistors MP1 and MN
1 is turned on, with the result that node N1 goes to a logic high level and node N2 goes to a logic low level. The logic levels of nodes N1 and N2 are
And 14 respectively, and each latch 12, 14 has 2
Inverters INV1, INV2 or INV3, I
It is composed of NV4. Therefore, the default value of signal MDST1 is set to low, and the default value of signal MDST2 is set to high. Signals MDST1 and MDST2
Can be changed by the corresponding mode register address signals MRA1 and MRA2.
When the signal PVCCH is set at a logic high level,
The PMOS and NMOS transistors MP1 and MN1 are turned off.

Referring to FIG. 2, a circuit diagram showing another conventional mode register 10 is shown. FIG.
Here, the same components as those in FIG. 1 are denoted by the same reference numerals. The mode register 10 of FIG. 2 includes a diode-connected NMOS and PMOS transistor M.
It differs from FIG. 1 in that N2 and MP2 have been added.
NMOS and PMOS transistors MN2 and MP2 function with a metal option. That is, the transistor MN
2 and MP2 are selectively formed.
Therefore, each of the nodes N1 and N2 can be set to low or high depending on whether or not the transistors MN2 and MP2 are formed.

[0007]

However, the conventional general mode register structure described above cannot satisfy various demands of users. A synchronous semiconductor memory device including a mode register set set with different default values must be manufactured separately. As a result, various mode register default configurations of each memory device may cause an additional processing burden.

It is an object of the present invention to provide a programmable mode register in which various default values can be set according to a user's request without burdening an additional process, and a nonvolatile semiconductor memory device using the same. .

[0009]

A mode register according to the present invention is used in a semiconductor memory device having a memory cell array for storing data, and the mode register stores data for controlling various operation modes of the memory device. A first transistor having a first current electrode connected to the power supply voltage and a gate electrode for receiving a first control signal, and a first programmable element connected between the second current electrode of the first transistor and a node; A second transistor having a grounded first current electrode and a gate electrode for receiving a second control signal complementary to the first control signal; and a connection between the node and a second current electrode of the second transistor. A second programmable element.

A nonvolatile semiconductor memory device according to the present invention has a plurality of memory cells, each of which has a memory cell array having a data storage element and data for controlling a plurality of operation modes of the memory device. A mode register for storing, the mode register having a plurality of programmable elements, wherein a default value of the mode register is set depending on whether the programmable element is programmed, and wherein the programmable element is The data storage device may include a data storage device having the same form as the data storage device of the memory cell.

[0011]

Preferred embodiments of the present invention will be described below in detail with reference to the accompanying drawings. In the embodiment, the nonvolatile semiconductor memory device operates in synchronization with a clock signal. Specifically, the memory device is a synchronous mask R
OM device. The mode register of the synchronous mask ROM device stores data for controlling various operation modes. For example, RAS latency, CAS latency, burst length, and burst type are programmed. If the user wishes to change such a value, the mode register is set before exiting the power down mode and entering the steady operation mode. Synchronous mask ROM device
KM23V32205T "in Samsung Electronics specifications.

As described in KM23V32205T, the mode register stores a 7-bit address (for example, A0
To A7). Address signal A
0 and A1 set the burst length, address signal A2 sets the burst type, address signals A3-A5 set the CAS latency, and address signal A6 sets the RAS latency. Used to

FIG. 3 is a circuit diagram showing an embodiment of the mode register of the nonvolatile semiconductor memory device according to the present invention, and FIG. 4 is a preferred embodiment of the mode register shown in FIG. FIG. 3 shows a part of the mode register 100. According to the above-described conditions, the mode register address signal MRA has the 7-bit address signal A0
This corresponds to one of A7. Therefore, the same circuit configuration as that shown in FIG. 3 is added to mode register 100 in FIG. 3 corresponding to each of the other 6-bit address signals.

Referring to FIG. 3, the mode register 100
Are PMOS and NMOS transistors MP100 and M
Latch 130 having N100, first and second programmable elements 110 and 120, and two inverters INV100 and INV101 connected in reverse parallel
including. The PMOS transistor MP100 has the power supply voltage V
It has a source connected to CC and a gate electrode for receiving the signal PVCCH. First programmable element 110
Is connected between the drain of the transistor MP100 and the node N10, and the node N10 is used as an input terminal for receiving an externally applied mode register address signal MRA. Second programmable element 1
20 is a node N10 and an NMOS transistor MN100
Of the transistor MN100
Has a source grounded and a gate electrode for receiving the signal nPVCH. The node N10 has a latch 130
Is connected.

In this embodiment, the signal PVCCH
Indicates the power supply voltage level. The signal PVCCH has a logic low level when the power supply voltage is lower than a predetermined level, and has a logic high level when the power supply voltage is higher than the predetermined level. The signal nPVCH is complementary to the signal PVCCH.

As shown in FIG. 4, the first and second programmable devices 110 and 120 are each implemented using a depletion transistor. That is, the first programmable element 1
The depletion-type transistor D100 used as 10 has a grounded gate electrode, a first current electrode connected to the drain of the transistor MP100, and a second current electrode connected to the node N10. Depletion transistor D10 used as second programmable element 120
1 has a grounded gate electrode and a channel connected between node N10 and the drain of transistor MN100.

The mode register 100 has a synchronous mask RO.
M device, so that the depletion type transistor D10
0 and D101 are formed by the same process as the memory cells of the mask ROM device. When the memory cell is programmed by ion implantation, transistors D100 and D10
1 can be programmed. As a result, the transistor D10
0 and D101 have an ON state or an OFF state depending on whether or not they are programmed by ion implantation. When transistor D100 or D101 is programmed, its threshold voltage is higher than the gate voltage. Unprogrammed transistors have a threshold voltage lower than the gate voltage and are turned on. In addition, node N1
The default value of 0 is the mode register address signal MRA.
Can be set to different values.

According to the mode register 100 of the present invention,
The voltage level of the register output signal MDST can be set by programming the depletion type transistor D100 or D101. For example, when the depletion type transistor D100 is programmed, the transistor D100 is kept off while the transistor D101 is on. Conversely, when the depletion transistor D101 is programmed, it is kept off while the transistor D100 has an on state. In the former case, the signal PV
When CCH and nPVCH go low and high respectively,
Node N10 is grounded, and the default value of signal MDST is set to a logic high level. In the latter case, when signals PVCCH and nPVCH go low and high, respectively, node N10 is charged to power supply voltage VCC and the default value of signal MDST is set to a logic low level.

In the case of a synchronous flash memory device, the programmable elements 110 and 120 of FIG. 3 are transistors having floating gates, for example, EE.
Each is replaced by a PROM or EPROM transistor. The transistor having the floating gate is programmed in the same manner as the memory cell of the synchronous flash memory device is programmed. Also, the programmable elements 110 and 120 can be realized by a fuse element such as a laser fuse.

[0020]

As described in detail above, according to the present invention,
Unlike the conventional general mode register configuration, various default values for the mode register can be set according to a user's request without additional process burden.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a conventional general mode register.

FIG. 2 is a circuit diagram showing another conventional general mode register.

FIG. 3 is a circuit diagram showing an embodiment of a mode register according to the present invention.

FIG. 4 is a circuit diagram showing a preferred embodiment of the mode register shown in FIG. 3;

[Explanation of symbols]

 Reference Signs List 100 Mode register 110 First programmable element 120 Second programmable element 130 Latch MP100 PMOS transistor MN100 NMOS transistor

Claims (14)

[Claims] 1. A mode register for storing data for controlling various operation modes of the memory device, wherein the first current electrode is connected to a power supply voltage, and is used in a semiconductor memory device having a memory cell array for storing data. A first transistor having a gate electrode for receiving a first control signal; a first programmable element connected between a second current electrode of the first transistor and a node; a first current electrode grounded; A second transistor having a gate electrode for receiving a second control signal complementary to the first control signal; and a second programmable element connected between the node and a second current electrode of the second transistor. A mode register. 2. The mode register according to claim 1, further comprising a latch connected to the node. 3. The mode register of claim 1, wherein each of the first and second programmable elements has a first programmed state in a conductive state and a second programmed state in a non-conductive state. . 4. The mode register according to claim 3, wherein the semiconductor memory device includes a mask ROM device that operates in synchronization with a clock signal. 5. Each of the first and second programmable elements is formed of a depletion transistor, and one of the depletion transistors is used in the first ion implantation process for a memory cell of the mask ROM device. 5. The mode register according to claim 4, wherein the mode register is programmed to a second program state. 6. The mode register according to claim 1, wherein each of the first and second programmable elements comprises a fuse. 7. The mode register according to claim 1, wherein the semiconductor memory device is a flash memory device that operates in synchronization with a clock signal. 8. The mode register according to claim 7, wherein the first and second programmable elements comprise a transistor having a floating gate. 9. The mode according to claim 1, wherein the node is set to one of a logic low level and a logic high level in response to an externally applied mode register address signal. register. 10. The first control signal has a logic low level when the power supply voltage is lower than a predetermined level, and has a logic high level when the power supply voltage is higher than the predetermined level. Item 2. The mode register according to item 1. 11. A non-volatile semiconductor memory device, comprising: a plurality of memory cells; each of the memory cells stores a memory cell array having a data storage element; and data for controlling a plurality of operation modes of the memory device. A mode register, wherein the mode register has a plurality of programmable elements, a default value of the mode register is set according to whether the programmable elements are programmed, and the programmable elements are A nonvolatile semiconductor memory device comprising a data storage element having the same form as a data storage element of a memory cell. 12. The nonvolatile semiconductor memory device according to claim 1, wherein the nonvolatile semiconductor memory device operates in synchronization with a clock signal.
2. The nonvolatile semiconductor memory device according to claim 1. 13. The non-volatile semiconductor memory device according to claim 12, wherein the non-volatile semiconductor memory device comprises one of a mask ROM device and a flash memory device. 14. A mode transistor, comprising: a PMOS transistor having a first current electrode connected to a power supply voltage and a gate electrode receiving a first control signal; and a mode transistor connected between a second current electrode of the PMOS transistor and a node. An NMO having a first programmable element of the programmable elements, a first current electrode grounded, and a gate electrode receiving a second control signal complementary to the first control signal.
An S transistor; a second programmable element among the programmable elements connected between the node and a second current electrode of the NMOS transistor; and a latch connected to the node. The nonvolatile semiconductor memory device according to claim 11, wherein: