JP2000067581A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To establish compatibility of high speed at the time of operation and low power consumption at the time of standby of a circuit consisting of two CMOS inverters cross-linked at the time of low operation voltage. SOLUTION: Threshold voltage of a MOS transistor included in a CMOS inverter is made relatively low ((b), (f) point) at the time of operation and relatively high ((b), (g) point) at the time of standby. One means for varying threshold voltage can be realized by varying the potential of a well in which a transistor is formed. Thereby, compatibility of high speed at the time of operation and low power consumption at the time of standby of a circuit consisting of cross-linked two CMOS inverters can be established.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a highly integrated semiconductor integrated circuit which operates at high speed and with low power consumption.

[0002]

2. Description of the Related Art As a semiconductor integrated circuit becomes more highly integrated, power consumption due to charging and discharging of a load capacitance tends to increase. For this reason, semiconductor integrated circuit technology that operates at high speed and with low power consumption is important. In recent years, demand for portable electronic information devices such as laptop personal computers and electronic organizers, portable electronic media devices such as audio recording devices not using magnetic media, and electronic still cameras has been increasing. In order to store a large amount of information in these portable electronic devices and hold the information, a low-power-consumption ultra-high-integration semiconductor circuit (ULSI) that enables a battery operation or an information holding operation (battery backup) using a battery. )Is required. This ULSI
In order to reduce the power consumption, it is effective to reduce the operating voltage of the main circuit block and the amplitude of a signal that transmits information between circuits. DRAM on behalf of ULSI
(Dynamic random access memory). In order to reduce the power consumption of a DRAM, it is important to reduce the data line charge / discharge power, which accounts for about half of the power consumption. Conventionally, regarding the reduction of power consumption of DRAMs, N.C.Lu and Et.H.
VIDEO BITLINE SENSING IN SIMOS MOS DELAM "IEE JE, Solid State Circuit, Vol S1
9, 451-454, 1984 (NC Lu and H.
H. Chao, “Half-VDDbit-Line sensing scheme in CMO
S DRAM's ”, IEEE J. Solid-State Circuits, Vol. S
C-19, pp. 451-454, 1984. ). The feature of the half VDD precharge method is that the VDD precharge method (for details, see JP-A-51-74).
535, USP 3514765 etc.)
Since the signal amplitude of the data line is halved, (1) the charge consumed in one cycle may be halved, (2) the noise in the memory array is small, and (3) the charge / discharge time of the data line is short, so the cycle time is short. The point is that the speed can be increased. However,
When the signal amplitude of the data line is reduced along with the high integration of the memory, one type of M is used regardless of the signal amplitude in the conventional LSI.
Since the circuit is constituted by the OS-FET, there is a problem that when the amplitude is close to the threshold voltage of the MOS-FET of the sense amplifier, the circuit malfunctions or the speed performance is significantly impaired. Therefore, even if the signal amplitude is reduced by half, the lower limit of the operating voltage is VDD.
This is about twice that of the precharge method, and the advantage of low power consumption cannot be enjoyed. The above is an example in the case of a DRAM. In addition, in a conventional logic LSI,
Since the lower limit of the signal amplitude is limited by the threshold power of the MOS-FET, the high-speed and ultra-low power consumption ULS
There is a problem that I cannot be realized.

[0003]

As described above, in the prior art, there is a problem that the element characteristics of the MOS-FET define the lower limit of the reduction in power consumption of the ULSI including the DRAM, and the battery operation and the operation of the device are difficult. There is a problem that it is impossible to provide a high-speed and low-power-consumption ULSI required for a battery backup device.

It is an object of the present invention to provide a semiconductor integrated circuit which can solve such a conventional problem and can operate at a high speed with low power consumption and can perform battery operation or battery backup.

[0005]

SUMMARY OF THE INVENTION It is an object of the present invention to reduce the signal amplitude of a main circuit block for defining power consumption and the threshold voltage of a MOS-FET constituting the circuit block, or to configure the circuit block. MOS-
The voltage between the gate and the source (drain) or the voltage between the drain and the source of the FET is dynamically or statically set to the MO
This is achieved by driving with a large voltage value sufficiently higher than the threshold voltage of the S-FET.

By the above means, it is possible to provide a ULSI that can reduce only the signal amplitude of the main circuit and achieve both high speed and low power consumption at the same time.

[0007]

Embodiments of the present invention will be described below in detail with reference to the drawings. In the following embodiment, an example in which the present invention is applied to a DRAM will be described. However, a random access memory (RA
M) or a read-only memory (ROM), and may be applied to any type of LSI such as a logic LSI such as a microcomputer. The constituent element may be a bipolar transistor, a MOS transistor, a combination of these elements, or a GaAs transistor using a material other than Si, for example.

FIGS. 1 to 4 show a first embodiment of the present invention. FIG. 1 shows a circuit configuration of the present embodiment. This circuit is provided in a conventional sense amplifier with a low VthMO having a low threshold voltage Vth.
It uses S transistors (Q1 ', Q2', Q3 ', Q4'). The case where the data line of this circuit is operated at a low voltage amplitude (1.0 V) will be described with reference to the operation waveform of FIG. When the voltage of the word line W0 is set to VSS (0
When the voltage is changed from V) to VDH (1.5 V), the information stored in the storage capacitor CS is read out to the data line D. Next, P1
When P is changed from VDL (1.0 V) to VSS (0 V) and P1N is changed from VSS (0 V) to VDL (1.0 V), the sense amplifier driving transistors QP and QN are turned on, and the sense amplifier driving line CSP is connected to HVC ( 0.5V) to VDL
(1.0V), CSN is changed from HVC (0.5V) to VSS
(0 V). At this time, the sense amplifier of the present invention uses transistors (Q1 ', Q1) having a low threshold voltage.
2 ', Q3', Q4 '), the voltage between the gate and the source (drain) sufficiently exceeds the threshold voltage, the transistor of the sense amplifier is sufficiently turned on, and the signal voltage of the data line is sufficiently amplified. it can. However, in the conventional sense amplifier, since the voltage between the gate and the source (drain) is close to the threshold voltage, the transistor of the sense amplifier is not sufficiently turned on, and the signal voltage of the data line cannot be sufficiently amplified. The operation of the data lines thereafter is the same as that of the conventional D line.
Same as RAM. FIG. 2A shows a case where the data line is operated at a normal voltage amplitude (for example, 1.5 V). In this case, the use of the sense amplifier of the present invention slightly increases the charge / discharge speed of the data line. FIG.
Shows the effect of the present embodiment. VDLmin is a data line charging voltage when the sense amplifier reaches the operation limit. IDSmax assumes a 64-Mbit DRAM (Q1, Q2, Q3, Q4: W / L = 2 μm / 0.5 μ)
m, operation of 16000 sense amplifiers), and the sum of the currents flowing between the drains and sources of all the sense amplifiers when the voltage between the gate and the source (drain) of the sense amplifier is set to 0V. When the voltage between the gate and the source (drain) of the MOS transistor is set to 0 V, the current flowing between the drain and the source is described in RM SWANSON and
JD MEINDL, “Ion-Implanted Complementary MO
S Transistorsin Low-Voltage Circuits ", IEEE J.
Solid-State Circuits, Vol.SC-7, No.2, pp.1
46-153, April 1972. VT
O is a voltage V between the gate and the source of the MOS transistor.
Assuming that the relationship between GS and the square root of the current between the drain and the source ソ ー ス ID is simplified as √ID = A · VGS + B,
This is the value of VGS when と き ID = 0. FIG. 4 (a)
FIG. 4B shows an example of the relationship between VTO and the channel length Lg of the transistor. The sense amplifiers (Q1 ', Q2', Q3 ', Q4') of this embodiment are low VthMOS transistors, the other circuits are standard VthMOS transistors,
Conventional sense amplifiers (Q1, Q2, Q3, Q4) have high V
thMOS transistor. Thus, a transistor having a large channel length Lg (Lg = 0.
5 μm) is used because of the processing variation of Lg.
This is to prevent the threshold voltage of the transistor of the sense amplifier from varying and the sensitivity of the sense amplifier from lowering. For transistors other than the sense amplifier, a small value of Lg (for example, 0.3 μm) is used in order to obtain high driving capability. The operation of the present embodiment is different from the conventional operation when VDL becomes a low voltage of about 1.0 V. For example, in the case of the conventional system using the high Vth MOS transistor (VTO = 0.5 V) shown in FIGS. 4A and 4B for the sense amplifier, as shown in FIG. Does not operate (the worst value of VTO is 0.6 V). The low Vth MOS transistor (V
When TO = 0.3V) is used for the sense amplifier, VDL
Is 1.2 V, the sense amplifier can operate sufficiently. This is because VTO is 0.4 V (worst value) for a voltage of 0.6 V between the gate and the source (drain) of the sense amplifier.
Is low enough. In this embodiment, VDL> 0.8
Operable up to V. At this time, the current IDSmax flowing between the drain and the source of the sense amplifier is 100 μA.
(Operation of 16000 sense amplifiers), which is a value that can be ignored sufficiently compared with the charging current of the data line, and is not a problem. FIG.
The low Vth MOS transistor as shown in FIG. 4A and FIG. 4B is manufactured by masking the sense amplifier and changing the ion implantation amount. In addition to the sense amplifier, the low-voltage operation of the sense amplifier can be achieved by using a low-Vth MOS transistor in a portion where the voltage between the drain and the source of the transistor is low (for example, a transistor for switching input / output lines when a memory array is shared). The same effect can be obtained. The same effect can be obtained by using a depletion type MOS transistor instead of the low Vth MOS transistor. In this case, at the time of precharge without driving the sense amplifier, the substrate potential of the N-channel MOS transistor of the sense amplifier is lowered (the substrate potential of the P-channel MOS transistor is raised) so that no current flows between the data lines. I do. As described above, according to the present embodiment, it is possible to provide a memory circuit that operates even at a lower power supply voltage without significantly impairing the speed performance. Also, not limited to sense amplifiers,
A high-speed and low-power-consumption LSI can be provided by selectively using the circuit according to the purpose of the circuit. Furthermore, not only in the memory but also in other LSIs such as a logic LSI (for example, a pass gate), an LSI operating at a lower voltage
Can be provided.

FIGS. 7 to 12 show second and third embodiments of the present invention.
This is an embodiment of the invention. FIG. 7 shows a circuit configuration of the second embodiment. In this circuit, two conventional sense amplifier driving transistors are connected in parallel, respectively (QP1, QP2, QN1, QN).
N2), boost capacitors CBP and CBN are added to the sense amplifier drive lines CSP and CSN. Substrate potentials of P channel MOS transistors Q3, Q4 constituting the sense amplifier are the same as those of sense amplifier drive lines CSP, CSN.

The operation of this circuit will be described with reference to the operation waveforms shown in FIG. The potential of the word line W0 is changed from VSS (0 V) to VDH
When the voltage is set to (1.5 V), information stored in the storage capacitor CS is read out to the data line D. Next, P1P is connected to VSS (0
V) to VDH (1.5 V) and P1N to VDL (1.0
V) to VDB (-0.5V), the sense amplifier driving transistors QP1 and QN1 are turned on, and the sense amplifier driving line CSP changes from HVC (0.5V) to VDL (1.V).
0V), the CSN changes from HVC (0.5V) to VSS (0V).
V). Next, PBP is changed from VSS (0 V) to V
PBN from VDL (1.0 V) to V (DL)
When it is set to SS (0 V), the sense amplifier drive line is boosted, and the CSP is changed from VDL (1.0 V) to VDH (1.5 V).
V), CSN changes from VSS (0V) to VDB (-
0.5V). At this time, P1P is set to VDH
(1.5 V) to VSS (0 V) and P1N to VDB (-
By changing the voltage from 0.5 V) to VDL (1.0 V), the charge injected into the sense amplifier drive line does not discharge through the sense amplifier drive transistor. As a result, the transistors (Q1,
Since the voltage between the gate and the source (drain) of Q2, Q3, Q4) can be set to about VDL / 2 + 0.5 V, the sense amplifier is sufficiently turned on and the data lines D, D are connected to VDL (1.0).
V) and VSS (0 V). After boosting the sense amplifier drive line, P2P is changed from VSS (0 V) to VDH.
(1.5V), P2N from VDL (1.0V) to VDB
(-0.5 V), and the sense amplifier driving transistors QP2 and QN2 are turned on so that the amplification of the sense amplifier can be sufficiently performed. The operation of the data lines thereafter is the same as in the conventional case.

In order to obtain a boost voltage as shown in FIG. 8, the boost capacitances CBP and CBN should be set to about 150 pF (the data line capacitance is about 3 pF in the sense amplifier drive line).
Assume that 1000 sense amplifiers of 00fF are connected). The voltage value of each terminal may not be as shown in FIG.
It is sufficient that the voltage amplitude between the sense amplifier drive lines CSP and CSN is larger than the voltage amplitude between the data lines D and D #. VDH
May be generated by boosting VDL or by lowering the external power supply. CSP only or CS
A boost with only N may be used. A boost capacitor CBP may be provided on the VDL wiring to boost the VDL.
At this time, the sense amplifier driving transistors QP1 and QP
The substrate voltage of P2 is set to the same potential as VDL. Sense amplifier driving transistors QP1, QP2, QN1, QN2
Is a P-channel MOS transistor and an N-channel MO
The transistor may be an S transistor or a bipolar transistor, and the potential of the sense amplifier drive line may be HVC to VDL on the CSP side and HVC to VSS on the CSN side. When boosting the sense amplifier drive line, latch-up and the like can be prevented by preventing the substrate potential of each transistor from becoming forward biased. Sense amplifier Q
By increasing the substrate potential of Q3 and Q4 to the same potential as the sense amplifier drive line CSP or by setting the substrate potentials of the sense amplifiers Q1 and Q2 to the same potential as the sense amplifier drive line CSN, an increase in the threshold voltage due to the body effect can be prevented. Since this can be prevented, the operation of the sense amplifier can be further improved. In order to make the substrate potential of the sense amplifier the same as the sense amplifier drive line, a triple well structure of the substrate may be used.

The triple well structure of the substrate is disclosed in Japanese Patent Application Laid-Open No. 62-119958.
1, Q2, Q3, Q4), the low VthM of the first embodiment.
By using an OS transistor, operation can be performed at a lower voltage. As described above, according to the present embodiment, it is possible to provide a memory circuit that operates even at a lower power supply voltage without significantly impairing the speed performance. In addition, a high-speed and low-power-consumption LSI can be provided by selectively using not only the sense amplifier but also the application of the circuit. Furthermore, not only a memory but also other LSIs such as a logic LSI can be provided with an LSI operating at a lower voltage.

FIGS. 9 and 10 show the concept of the third embodiment. In FIG. 9, the constant voltage generation circuit LVDH,
LVDL and LVDBL are provided, and constant voltages VDH, VDL,
VDBL is being generated. Constant voltage VDH, VDL, V
DBL and VDBH (= VSS) are connected to the switches SP1,
Sense amplifier drive line C via SP2, SN2, SN1
Connect to SP, CSN. Each voltage relationship is VDH ≧
VDL> VDP (precharge voltage)> VDBL ≧ VD
BH (= ground voltage VSS) ≧ VBB (substrate voltage).

The operation of this circuit is as follows. First, the voltages of the data lines D and D # and the voltages of the sense amplifier drive lines CSP and CSN are set to the precharge voltage VDP. Next, the switches SP1 and SN1 are turned on, the sense amplifier drive line CSP is set to VDH, and the CSN is set to VDBH (VS
S). As a result, the voltage between the gate and the source (drain) of the transistor constituting the sense amplifier is set to V
Since it can be larger than DP, the sense amplifier is sufficiently turned on, and the data lines D and D # can be amplified to about VDL and VDDL. Next, the switches SP1 and SN1 are turned off, and SP
2. Turn on SN2. Thus, the sense amplifier drive line CSP becomes VDL and CSN becomes VDDL, and the data lines D and D # can be fixed to VDL and VDDL. The timing of turning off the switches SP1 and SN1 and turning on the switches SP2 and SN2 is set when the data lines D and D # become about VDL and VDDL. This can prevent data line D # from going above VDL and data line D from going below VDDL.

The values of VDH and VDL and the external power supply voltage VCC
May be any relationship. (For example, VDH
= VCC or VDL = VCC. The voltage VDH may be generated by boosting VDL. Substrate voltage VB
B need not be smaller than VDBH. (For example, VD
BH (= VSS) may be equal to VBB. ) Substrate voltage VBB
May be applied to the memory array section and the sense amplifier section, or only one of them, and the other portions may be ground voltage. This can be realized by using a triple well structure of the substrate. For a triple well structure of a substrate, see JP-A-62-1.
19958. As described above, according to the present embodiment, it is possible to provide a memory circuit that operates even at a lower power supply voltage without significantly impairing the speed performance. In addition, a high-speed and low-power-consumption LSI can be provided by selectively using not only the sense amplifier but also the application of the circuit.
Furthermore, not only the memory but also other LSs such as a logic LSI
As for I, an LSI that operates at a lower voltage can be provided.

In FIG. 10, a constant voltage generating circuit LV is provided in the chip.
DH, LVDL, LVDBH are provided, and constant voltages VDH, VDH
DL and VDBH are generated. Constant voltage VDH, VD
L, VDBH and VDDL (= VSS) are switches S
It is connected to sense amplifier drive lines CSP and CSN via P1, SP2, SN1 and SN2. Each voltage relationship is V
DH ≧ VDL> VDP (precharge voltage)> VDDL
≧ VDBH (= ground voltage VSS) ≧ VBB (substrate voltage)
It is.

The operation of this circuit is as follows. First, the voltages of the data lines D and D # and the voltages of the sense amplifier drive lines CSP and CSN are set to the precharge voltage VDP. Next, the switches SP1 and SN1 are turned on, and the sense amplifier drive line CSP is set at VDH and the CSN is set at VDBH.
As a result, the voltage between the gate and the source (drain) of the transistor constituting the sense amplifier can be made higher than VDP, so that the sense amplifier is sufficiently turned on and the data lines D and D can be amplified to about VDL and VDDL (VSS). Next, the switches SP1 and SN1 are turned off, and the switches SP2 and SP2 are turned off.
Turn on SN2. As a result, the sense amplifier drive line CSP becomes VDL and CSN becomes VDDL (VSS),
The data lines D and D # can be fixed to VDL and VDDL (VSS). Switches SP1 and SN1 are turned off, and SP2 and S1
N2 is turned on when the data lines D and D # are at VD.
Set when L, VDBL or so. As a result, the data line D is higher than VDL and the data line D # is higher than VDDL.
The following can be prevented.

The values of VDH and VDL and the external power supply voltage VCC
May be any relationship. (For example, VDH
= VCC or VDL = VCC. The voltage VDH may be generated by boosting VDL. Substrate voltage VB
B need not be smaller than VDBH. (For example, VD
BH may be equal to VBB. ) The substrate voltage VBB may be applied to only one of the memory array section and the sense amplifier section, or the other may be the ground voltage. This can be realized by using a triple well structure of the substrate. The triple well structure of the substrate is specified in JP-A-62-119958. As described above, according to the present embodiment, it is possible to provide a memory circuit that operates even at a lower power supply voltage without significantly impairing the speed performance. In addition, a high-speed and low-power-consumption LSI can be provided by selectively using not only the sense amplifier but also the application of the circuit. Further, not only in the memory but also in other LSIs such as a logic LSI,
An LSI that operates at a lower voltage can be provided.

FIG. 11 shows an example of a specific circuit configuration of the third embodiment. This circuit shows a case where only the CSP side of the sense amplifier drive line in FIG. 10 is used. Two conventional sense amplifier driving transistors are connected in parallel (QP
1, QP2, QN1, QN2) and the drain of the P-channel MOS transistor QP1 are connected to VDH (for example, 1.5).
V), the drain of QP2 is set to VDL (for example, 1.0 V). The substrate potential of QP1 and QP2 is VDH.

The operation of this circuit will be described with reference to the operation waveforms shown in FIG. The voltage of the word line W0 is changed from VSS (0 V) to VDH
When the voltage is set to (1.5 V), information stored in the storage capacitor CS is read out to the data line D. Next, P1P is converted to VDH
(1.5V) to VSS (0V) and P1N to VSS (0
V) to VDL (1.0 V), the sense amplifier drive transistors QP1 and QN1 turn on, and the sense amplifier drive line CSP changes from HVC (0.5 V) to VDH (1.5 V).
V), the CSN changes from HVC (0.5V) to VSS (0V).
V). As a result, the voltage between the gate and the source (drain) of the transistors Q3 and Q4 constituting the sense amplifier can be set to about VDL / 2 + 0.5 V, so that the sense amplifier is sufficiently turned on and the data line D is connected to the VDL.
(1.0 V). As a result, the voltage between the gate and the source (drain) of transistors Q1 and Q2 constituting the sense amplifier also increases, and data line D #
Can be amplified to VSS (0 V). When the voltage of the data line D is V
When DL (1.0V) is exceeded, P1P is set to VSS
(0 V) to VDH (1.5 V), and P2P to VDH (1.
5V) to VSS (0V), the sense amplifier drive transistor QP1 turns off, QP2 turns on, and the sense amplifier drive line CSP changes from VDH (1.5V) to VDL.
(1.0 V). As a result, the voltage of the data line D becomes constant at VDL (1.0 V). At this time, P2N
Is changed from VSS (0 V) to VDL (1.0 V), and the sense amplifier driving transistor QN2 is turned on so that the sense amplifier can be sufficiently amplified. The operation of the data lines thereafter is the same as in the conventional case.

The voltage value of each terminal does not have to be as shown in FIG. 12, and it is sufficient that the voltage of the sense amplifier drive line CSP is higher than the charging voltage VDL of the data line. The voltage of VDH is
The VDL may be generated by raising the voltage or the external power supply may be generated by lowering the voltage. Transistor QP for driving sense amplifier
1, QP2, QN1, and QN2 may be P-channel MOS transistors, N-channel MOS transistors, or bipolar transistors, and the potential of the sense amplifier drive line is changed from HVC to VDL, VDH, and CSN on the CSP side.
It is sufficient if the voltage is changed from HVC to VSS on the side. Sense amplifier Q
By increasing the substrate potential of Q3 and Q4 to the same potential as the sense amplifier drive line CSP or by setting the substrate potentials of the sense amplifiers Q1 and Q2 to the same potential as the sense amplifier drive line CSN, an increase in the threshold voltage due to the body effect can be prevented. Since this can be prevented, the operation of the sense amplifier can be further improved. In order to make the substrate potential of the sense amplifier the same as the sense amplifier drive line, a triple well structure of the substrate may be used. The triple well structure of the substrate is specified in JP-A-62-119958. The first sense amplifier (Q1, Q2, Q3, Q4)
By using the low Vth MOS transistor of the embodiment, it is possible to operate at a lower voltage. As described above, according to the present embodiment, it is possible to provide a memory circuit that operates even at a lower power supply voltage without significantly impairing the speed performance. In addition to high-speed and low-power consumption LSIs, not only sense amplifiers but
Can be provided. Furthermore, not only memory, but also logic LSI
For example, it is possible to provide an LSI that operates at a lower voltage.

The voltage relationships described with reference to FIGS. 9 to 12 are not limited to those described above.
A similar effect can be obtained by making the gate / source voltage sufficiently exceed the threshold voltage for a certain period during operation.

FIGS. 13 to 16 show a fourth embodiment of the present invention. FIG. 13 shows the circuit configuration of this embodiment. This circuit can drive the plate terminal CSB of the storage capacitor connected to the reference data line D # at a time. Precharge circuit (Q5 ', Q6', Q7 ', Q5, Q6, Q
The low voltage VDP is used as the precharge voltage supplied to 7). This constant voltage VDP is the same as that shown in FIG.
The characteristics are as shown in FIG. The operation of this circuit will be described with reference to the operation waveform of FIG. When the voltage of the word line W0 is changed from VSS (0 V) to VDH (1.5 V), the information stored in the storage capacitor CS is read out to the data line D #. In the case of “1” read, CD / (CD + CS) ×
(VDL−VDP) = 0.25 CD / (CD + CS) volts, and in the case of “0” read, CD / (CD + CS) ×
(VDP-VSS) = 0.75CD / (CD + CS) volts (CD is the data line capacity) is read out to the data line. At this time, the voltage of the dummy word line DW0 is set to VSS
(0V) to VDH (1.5V). At this time, the voltage of the reference data line D is the precharge voltage VDP (0.
75V). Next, the voltage of the plate CSB of the storage capacitor CS ′ connected to the reference data line is changed to VDP.
(0.75V) to HVC (0.5V). As a result, the reference data line voltage is CD / (CD + CS) ×
(VDP-HVC) = 0.25CD / (CD + CS) volts, and the signal voltage difference between the data lines D and D # becomes
In both “1” read and “0” read, VDL /
2 × CD / (CD + CS) = 0.5CD / (CD + C
S) It becomes a bolt. Next, P1P is converted to VDL (1.0 V).
To VSS (0V) and P1N from VSS (0V) to VD
When it is set to L (1.0 V), the sense amplifier driving transistors QP1 and QN1 turn on, and the sense amplifier driving line CS
P goes from VDP (0.75V) to VDL (1.0V),
CSN changes from VDP (0.75V) to VSS (0V). As a result, the voltage between the gate and the source (drain) of the transistors Q1 and Q2 constituting the sense amplifier can be set to VDP (0.75V), so that the sense amplifier is sufficiently turned on and the data line D # is set to VSS (0V). Can be amplified. As a result, the voltage between the gate and the source (drain) of the transistors Q3 and Q4 constituting the sense amplifier also increases, and the data line D can be amplified to VDL (1.0 V). Next, P2P is changed from VDL (1.0 V) to VSS
(0V), P2N is changed from VSS (0V) to VDL (1.
0V) and the sense amplifier driving transistors QP2,
By turning on QN2, the sense amplifier can be sufficiently amplified. The operation of the data lines thereafter is the same as in the conventional case. The voltage of the plate CSB is changed from HVC (0.5 V) to VDP (0.75 V) before precharging the data line. Dummy word line DW0
Means that the data line voltage after precharge is VDP (0.75
V) (from VDH (1.5V) to VS
S (0V). The above shows the characteristics of VDP in FIG.
It was explained as. A similar effect can be obtained even when the VDP characteristic is as shown in FIG. The voltage relationship of each terminal may not be as shown in FIGS. 14A, 16A and 16B, and VDP> VDL / 2 = HVC (FIG.
(A)) or VDP <VDL / 2 = HVC (FIG. 16)
(B)) is acceptable. As shown in FIGS. 16A and 16B, when VDL becomes a high voltage, VDL = 1.5 V
Thus, VDP = HVC. The operation in this case is shown in FIG.
As shown in FIG. 4 (b), the operation is the same as the conventional operation. A method for driving the plate voltage is disclosed in Japanese Patent Application No. 62-2223.
17, Japanese Patent Application No. 63-148104. In order to drive the plate voltage for the dummy word line at high speed, as shown in FIG.
21 are provided, and the dummy word lines DW0 and DW1 are preferably used as switching signals. Q20, Q21, Q23, Q
24, NAD1 and NAD2 are periodically arranged in the memory array. NAD1 and NAD2 in the figure may be collectively arranged outside the memory array. Q20 in the figure,
Q21, Q23 and Q24 may also be collectively arranged outside the memory array. NAD1 and NAD2 in the figure are OR
Although the circuit is constituted, it may be constituted by a NOR circuit and an inverter. The dummy cell may be of any type, and the plate voltage for the dummy word line is maintained at a constant voltage (V
P), the dummy word line DW0 is set to VVC when the data line voltage immediately after precharge becomes HVC (0.5 V).
The voltage may be changed from DH (1.5 V) to VSS (0 V). Alternatively, a write MOS transistor may be provided between CS and QW0 to write HVC (0.5 V).
Even if the voltage of VDP is generated by stepping down VDL, HV
C may be generated by increasing (lowering) C. The sense amplifier driving transistors QP1, QP2, QN1, and QN2 may be P-channel MOS transistors or N-channel MOS transistors.
It may be a transistor or a bipolar transistor,
The potential of the sense amplifier drive line is changed from VDP to VD on the CSP side.
What is necessary is that L and CSN go from VDP to VSS. The substrate potentials of sense amplifiers Q3 and Q4 are connected to sense amplifier drive line CS
By setting the same potential as P or setting the substrate potentials of the sense amplifiers Q1 and Q2 to the same potential as the sense amplifier drive line CSN, it is possible to prevent the threshold voltage from increasing due to the body effect, thereby further improving the operation of the sense amplifier. it can. In order to make the substrate potential of the sense amplifier the same as the sense amplifier drive line, a triple well structure of the substrate may be used. The triple well structure of the substrate is specified in JP-A-62-119958. Sense amplifier drive line CSP or CS
By sharing the precharge wiring with N, the precharge speed can be increased without increasing the wiring area. Sense amplifier (Q1, Q2, Q3, Q
4) By using the low-Vth MOS transistor of the first embodiment, it is possible to operate at a lower voltage. As described above, according to the present embodiment, by changing the operation amplitude of the circuit in accordance with the power supply voltage, it is possible to provide a memory circuit that operates at a lower power supply voltage without significantly impairing the speed performance. Also, not limited to sense amplifiers,
A high-speed and low-power-consumption LSI can be provided by selectively using the circuit according to the purpose of the circuit. Furthermore, not only a memory but also other LSIs such as a logic LSI can be provided with an LSI operating at a lower voltage.

FIGS. 17 and 18 show a fifth embodiment of the present invention. FIG. 17 shows the circuit configuration of this embodiment. This circuit adds a boost capacitance CB to each conventional data line. The operation of this circuit will be described with reference to operation waveforms in FIG. The voltage of the word line W0 is changed from VSS (0 V) to VDH
When the voltage is set to (1.5 V), information stored in the storage capacitor CS is read out to the data line D. Next, boost terminal PCB
Is changed from VSS (0 V) to VDL (1.0 V), both data lines D and D are about 0.2 V (CB is about 70 V).
(at fF). Next, P1P is converted to VDL (1.0
V) to VSS (0 V) and P1N from VSS (0 V) to VDL (1.0 V), the sense amplifier drive transistors QP and QN turn on, and the sense amplifier drive line CS
P changes from HVC (0.5V) to VDL (1.0V), CS
N changes from HVC (0.5V) to VSS (0V). At this time, the transistor Q constituting the sense amplifier
1, the voltage between the gate and source (drain) of Q2 is V
Since the voltage can be set to about DL / 2 + 0.2 V, the sense amplifier is sufficiently turned on, and the data line D # can be amplified to VSS (0 V). Thereby, the voltage between the gate and the source (drain) of the transistors Q3 and Q4 constituting the sense amplifier also increases, and the data line D can be amplified to VDL (1.0 V). The operation of the data lines thereafter is the same as in the conventional case. The voltage of the boost terminal PCB is changed from VDL (1.0 V) to VSS (0 V) before the data line is precharged. The voltage value of each terminal may not be as shown in FIG.
At the time of driving the sense amplifier, the potential difference between the data line voltage and VSS may be VDL / 2 or more. Boost voltages may be applied in opposite phases so that the voltages of data lines D and D # both drop. Also in this case, it is sufficient that the potential difference between the data line voltage and VDL is VDL / 2 or more when the sense amplifier is driven. The boost line CBL and the sense amplifier drive line CSP (or CSN) may be shared. The sense amplifier driving transistors QP and QN may be P-channel MOS transistors, N-channel MOS transistors, or bipolar transistors, and the potential of the sense amplifier driving line may be from HVC to VDL on the CSP side and from HVC to VSS on the CSN side. . The substrate potential of sense amplifiers Q3 and Q4 is set to the same potential as sense amplifier drive line CSP, or the substrate potential of sense amplifiers Q1 and Q2 is set to sense amplifier drive line CS.
By setting the same potential as N, it is possible to prevent the threshold voltage from increasing due to the body effect, so that the operation of the sense amplifier can be further improved. In order to make the substrate potential of the sense amplifier the same as the sense amplifier drive line, a triple well structure of the substrate may be used. The triple well structure of the substrate is specified in JP-A-62-119958. The sense amplifiers (Q1, Q2, Q3, Q4) are connected to the low V of the first embodiment.
By using the thMOS transistor, it is possible to operate at a lower voltage. As described above, according to the present embodiment, it is possible to provide a memory circuit that operates even at a lower power supply voltage without significantly impairing the speed performance. In addition, a high-speed and low-power-consumption LSI can be provided by selectively using not only the sense amplifier but also the application of the circuit.
Furthermore, not only the memory but also other LSs such as a logic LSI
As for I, an LSI that operates at a lower voltage can be provided.

FIGS. 19 and 20 show a sixth embodiment of the present invention. FIG. 19 shows the circuit configuration of this embodiment. This circuit adds the data line boost capacitance CB of FIG. 17 to the gates of transistors Q1 and Q2 forming a sense amplifier,
Further, the gate and CB can be separated from the data line by QA and QB. The operation of this circuit is shown in FIG.
The operation waveform will be described with reference to FIG. As described above, the word line W0
Becomes high potential, information is read out to the data line D by CS. At this time, the gate voltages CG of QA and QB in FIG.
A is maintained at substantially the same potential VDH as the word line. Therefore, information on the data line D is also transmitted to the gate of Q1 via QA. It should be noted that the voltage CGA only needs to be a value such that QA and QB are sufficiently turned on during precharge. Similarly, the reference potential of D # is transmitted to the gate of Q2. Next, the sense amplifier driving transistors QP,
QN is turned on, and the sense amplifier drive line CSP is
(0.5V) to VDC (1.0V), CSN to HVC
To VSS (0 V). At this time, QA, QB
Gate voltage CGA is the capacitance C between CSN
Since it is lowered to the potential of VDL by the PC, Q
A and QB are in a high resistance state, and data lines D, D # and Q1,
The gate of Q2 is electrically isolated. As a result, the boost capacitance CB boosts only the gates of Q1 and Q2, so that a sufficient gate voltage can be obtained even with a small capacitance according to the fifth embodiment. Next, when the voltage of the boost terminal PCB is changed from VSS to VDL, the gate voltages of Q1 and Q2 both rise and become VDL / 2 + 0.2 or more. As a result, Q1 and Q2 are sufficiently turned on, and the data lines are quickly switched to VS.
Amplify to S. In addition, this allows the gate of Q3
The source-to-source voltage also increases, and the data line can be amplified to VDL at high speed. Subsequent data lines and boost terminal P
The operation of the CB is the same as in the fifth embodiment. The precharging of the CGA is performed via the QPC2 while the sense amplifier drive transistor QN is on. The precharge voltage is VDL (1.0 V). Thereby, C
When precharging SN, CGA is boosted to almost VDH due to capacitive coupling with CPC. in this way,
According to the present embodiment, it is possible to provide a memory circuit that operates even at a lower power supply voltage without significantly impairing the speed performance. In addition, a high-speed and low-power-consumption LSI can be provided by selectively using not only the sense amplifier but also the application of the circuit. Further, not only the memory but also other LSIs such as a logic LSI operate at a lower voltage.
SI can be provided.

FIG. 21 shows a seventh embodiment of the present invention.
FIG. 21A shows a circuit configuration of the present embodiment. The sense amplifier of this circuit includes a Q connected to a data line and a capacitor CC.
12 to Q15 sense amplifier and conventional Q1 to Q4
And two stages of sense amplifiers. Among them, the former has a higher voltage V than the conventional VDL (1.0 V).
Operates at DH (1.5V). CHP and CHN are the common drive lines. The operation of this circuit will be described with reference to the operation waveform of FIG. As described above, when the word line W0 becomes high potential, information is read out to the data line D from CS. This change in the data line potential is caused by Q12 to Q
15 is transmitted to the sense amplifier. Next, CHP
From VPH (0.75V) to VDH (1.5V), CH
When N is changed from VPH (0.75V) to VSS, Q
The sense amplifiers 12 to Q15 start amplifying according to the signal on the data line. At this time, the voltage between the gate and the source of Q12 to Q15 is a precharge voltage of 0.7.
5V is applied. This voltage is sufficiently higher than the threshold voltage 0.6V of the MOS transistor, and the capacity of the output of the sense amplifier is about 1/10 of the data line (only the capacity of the gate and CC). Therefore, the sense amplifier can perform amplification at high speed. And the output voltage is VS
S (0 V) and VDH (1.5 V). Next, CS
If P and CSN are VDL and VSS as before, then Q
The input terminals of the sense amplifier consisting of Q1 to Q4 are connected to Q12 to Q4.
Since they are connected to the output terminals of the sense amplifier 15, the voltage between their gate and source is 1.5 V for NMOS Q 2 and −1.0 V for PMOS Q 3, and is sufficiently higher than the threshold voltage. Therefore, the data lines can be charged and discharged at high speed. In principle, the minimum value of the data line voltage amplitude in this embodiment is 0.6 V at which the maximum value of the gate-source voltage of the PMOS (Q3, Q4) becomes equal to the threshold value. Therefore, considering the operating speed, the practical voltage is about 0.8.
V. According to this embodiment, since the low level of CHN can be made negative, the voltage between the gate and the source of the PMOS can be further increased, and the operation can be performed at a lower voltage. For example, the low level of CHN
If the voltage is set to 0.5 V, the voltage between the gate and the source that can operate normally is set to 0.8 V, and the data line voltage amplitude can be set to 0.3 V. This is lower than the threshold voltage of the sense amplifier transistor. At the time of precharging, the data line is short-circuited and precharged by the signal PC as in the first embodiment and the like.
Also, the output terminal of the sense amplifier 15 is short-circuited and precharged. Q16, Q17 and Q18 are transistors for that purpose. This precharge voltage is VDH
It is 0.75V which is half of (1.5V). Therefore, the PC amplitude of the precharge signal may be set to 1.35 V or more. As described above, in this embodiment, even when the voltage amplitude of the data line is smaller than the threshold voltage of the sense amplifier transistor driving the data line, the voltage between the gate and the source at the time of startup can be made sufficiently higher than the threshold voltage. So faster,
Low power consumption can be achieved. Therefore, according to the present embodiment, it is possible to provide a memory circuit that operates even at a lower power supply voltage without significantly impairing the speed performance. The essence of the present invention is that the voltage amplitude of a signal line (here, a data line) having a large load capacitance is reduced, and the signal line is driven with a large voltage amplitude sufficiently exceeding an operation threshold voltage of an element constituting a drive circuit of the signal line. It is to drive a circuit. Therefore, a high-speed and low-power-consumption LSI can be provided by selectively using not only the sense amplifier but also the circuit application. Furthermore, other LSIs such as a logic LSI are not limited to the memory.
Also, it is possible to provide an LSI that operates at a high speed even at a lower voltage. Further, by optimizing the combination of the large / small voltage amplitude and the threshold voltage, it is possible to provide an LSI with higher speed and lower power consumption. For example, in FIG. 21A, a part of Q1 to Q4 is replaced with a depletion type MOS.
-The speed can be further increased by using an FET.

FIGS. 22 and 23 show an eighth embodiment of the present invention. FIG. 22A is a schematic diagram of a circuit configuration of the present embodiment. This circuit controls the substrate voltage VBB of the sense amplifier transistor to make its threshold voltage an optimal value for operation. Therefore, MO for threshold voltage monitoring
S transistor, reference voltage VR generation circuit, comparison circuit CO
MP and a substrate voltage VBB generation circuit. The operation will be described with reference to FIG. The threshold voltage of the MOS transistor changes by changing the substrate voltage VBB. For example, in the case of NMOS,
As shown in FIG. 22B, when VBB is increased in the negative direction, the threshold voltage increases. Conversely, the smaller the size, the smaller the size. In order to operate the sense amplifier at a low voltage (approximately 1.0 V), high speed operation is achieved by reducing the threshold voltage as described above. Therefore, in the present embodiment, FIG.
As shown in (a), by connecting a MOS transistor with a diode and driving it with a constant current, the threshold voltage is monitored and compared with a reference voltage VR by a comparison circuit COMP. Control the output voltage,
The threshold voltage of the monitoring MOS transistor is set equal to VR. By doing so, even if the threshold voltage of the MOS transistor becomes a voltage at the point b higher than the optimum value indicated by the point a in FIG.
Can be shifted to a point and made equal to VR. Also,
When it becomes lower (point c in the figure), VBB is shifted to point e by raising VBB to VB2, and can also be made equal to VR. Therefore, according to the present embodiment, it is possible to realize a sense amplifier that is stable against manufacturing variations. Also,
By making the VR lower than the standard value (point a) during operation (point f) and higher (point g) during standby, it is possible to achieve both high-speed operation and low power consumption during standby. Furthermore, PMO
A similar circuit is added to the well of S, and the threshold voltage of the transistor is depleted by setting VR to be negative for NMOS and positive for PMOS during operation, and is set to positive and negative during standby, and both are set to normal voltages. The enhancement type can further increase the speed and lower the voltage amplitude. When the operation cycle is short and the substrate voltage needs to be changed at a high speed, the substrate of the sense amplifier section may be separated using the triple well structure described above. As a result, the power consumption of the VBB generation circuit can be reduced.

FIG. 23 embodies FIG. 22 (a). QB1 and QB2 are monitoring MOS transistors, QB3 to QB8 are comparison circuits, OSC is an oscillation circuit of a VBB generation circuit, INV1, INV2, C2, C3, QB
9 to QB12 are VBB generation circuits. The reason why the monitoring MOS transistors are connected in two stages is to obtain the optimum bias of the comparison circuit. Along with this,
VR needs to be twice the target threshold voltage.
Note that the number of stages of the monitoring transistor is not limited to two, and may be any number that optimizes the input voltage to the comparison circuit. In addition, the rectifier circuit (C2, C3,
QB9 to QB12) generate a doubled voltage in this embodiment in order to increase the control range of the threshold voltage. However, this is because the rate of change of the threshold voltage with respect to the operating voltage of the sense amplifier and the substrate voltage. It can be changed accordingly. As described above, according to the present embodiment, the threshold voltage of the sense amplifier can be kept constant irrespective of control variation, and its value can be changed between operation and standby, so that low voltage, high speed, and low power consumption are achieved. DRAM can be realized. Therefore, according to the present embodiment, it is possible to provide a memory circuit that operates even at a lower power supply voltage without significantly impairing the speed performance. In addition, a high-speed and low-power-consumption LSI can be provided by selectively using not only the sense amplifier but also the application of the circuit. Furthermore, not only a memory but also other LSIs such as a logic LSI can be provided with an LSI operating at a lower voltage. The present invention resides in a means for detecting an operation threshold voltage of an element and a control for controlling a threshold voltage to an optimum value for a circuit operation by a detection output thereof. It is not limited.

While the present invention has been described by taking a DRAM as an example, any of a random access memory (RAM) such as a dynamic or static memory, a read only memory (ROM), and a logic LSI such as a microcomputer can be used. It may be applied to an LSI of a type. The constituent elements are a bipolar transistor, a MOS transistor, a combination of these elements,
Alternatively, for example, a GaAs transistor using a material other than Si may be used.

[0030]

As described above, according to the present embodiment, it is possible to provide a memory circuit that can operate even at a lower power supply voltage without significantly impairing the speed performance, and is used as a battery backup memory or a battery operation memory. be able to. In addition, a high-speed and low-power-consumption LSI can be provided by selectively using not only the sense amplifier but also the application of the circuit. Further, not only the memory but also other LSIs such as a logic LSI operate at a lower voltage.
SI can be provided.

[Brief description of the drawings]

FIG. 1 is a diagram showing a circuit configuration of a first embodiment of the present invention.

FIG. 2 is a diagram showing operation waveforms according to the first embodiment of the present invention.

FIG. 3 is a diagram showing the effect of the first embodiment of the present invention.

FIG. 4 is a diagram showing characteristics of the transistor according to the first embodiment of the present invention and a conventional transistor.

FIG. 5 is a diagram showing a conventional circuit configuration.

FIG. 6 is a diagram showing a conventional operation waveform.

FIG. 7 is a diagram showing a circuit configuration according to a second embodiment of the present invention.

FIG. 8 is a diagram showing operation waveforms according to the second embodiment of the present invention.

FIG. 9 is a diagram showing the concept and operation waveforms of a third embodiment of the present invention.

FIG. 10 is a diagram showing another concept and operation waveforms of the third embodiment of the present invention.

FIG. 11 is a diagram showing a circuit configuration according to a third embodiment of the present invention.

FIG. 12 is a diagram showing operation waveforms according to the third embodiment of the present invention.

FIG. 13 is a diagram showing a circuit configuration according to a fourth embodiment of the present invention.

FIG. 14 is a diagram showing operation waveforms according to a fourth embodiment of the present invention.

FIG. 15 is a diagram showing another circuit configuration applied to the fourth embodiment of the present invention.

FIG. 16 is a diagram showing a configuration and effects of a fourth embodiment of the present invention.

FIG. 17 is a diagram showing a circuit configuration according to a fifth embodiment of the present invention.

FIG. 18 is a diagram showing operation waveforms according to the fifth embodiment of the present invention.

FIG. 19 is a diagram showing a circuit configuration of a sixth embodiment of the present invention.

FIG. 20 is a diagram showing operation waveforms according to the sixth embodiment of the present invention.

FIG. 21 is a diagram showing a circuit configuration and operation waveforms according to a seventh embodiment of the present invention.

FIG. 22 is a view showing the concept and effects of an eighth embodiment of the present invention.

FIG. 23 is a diagram showing an eighth specific circuit configuration of the present invention.

[Explanation of symbols]

Q1, Q2, Q3, Q4, Q1 ', Q2', Q3 ', Q
4 ', Q12, Q13, Q14, Q15 ... transistors for sense amplifier, Q5, Q6, Q7, Q5', Q
6 ', Q7', Q16, Q17, Q18 ... transistors for precharge circuit, Q8, Q9 ... Y gate, VP
... Plate voltage terminal, CS ... Storage capacitance, Q10, Q1
1 ... transistor for switching memory cells, PC ... precharge signal input terminal, VDP ... precharge voltage, HVC ... VDD / 2 voltage terminal, VDL ... data line charge voltage terminal, QP, QN, QP1, QP2, QN
1, QN2: sense amplifier driving transistor, VS
S: ground potential, AMP: main amplifier, DIB: Din
Buffer, Dout: Information output terminal, Din: Information input terminal, W / R: Information input / output switching terminal.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hitoshi Tanaka 5-20-1, Josuihonmachi, Kodaira-shi, Tokyo Nippon-Cho S.S.E. Engineerrig Co., Ltd. (72) Inventor Yoshinobu Nakagome 1-280 Higashi-Koigakubo, Kokubunji-shi, Tokyo Inside the Hitachi, Ltd. Central Research Laboratory (72) Inventor Yoshiki Kawajiri 1-280 Higashi-Koikekubo, Kokubunji-shi, Tokyo Inside the Hitachi, Ltd. Central Research Laboratory (72) Inventor Kiyoo Ito Kokubunji, Tokyo 1-280, Higashi Koigabo, Higashi-shi Central Research Laboratory, Hitachi, Ltd.

Claims (5)

[Claims] 1. A semiconductor integrated circuit comprising a plurality of circuits in which a first CMOS inverter and a second CMOS inverter are cross-coupled, wherein the first CMOS inverter is a serially connected P-type first MOS transistor and an N-type first MOS transistor. A second MOS inverter, wherein the second CMOS inverter includes a P-type third MOS transistor and an N-type fourth MOS transistor connected in series, and wherein the first to fourth MOS transistors have a threshold value during standby of the circuit. A semiconductor integrated circuit, wherein a threshold voltage is controlled so that a voltage is higher than a threshold voltage during operation of the circuit. 2. The semiconductor device according to claim 1, wherein the threshold voltages of the first to fourth MOS transistors are of an enhancement type when the circuit is on standby, and are of a depletion type when the circuit is operating. Semiconductor integrated circuit. 3. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is formed monolithically on one semiconductor substrate, and the first and third MOS transistors are formed in a first well formed on the semiconductor substrate. The semiconductor integrated circuit, wherein the second and fourth MOS transistors are formed in a second well formed in the semiconductor substrate. 4. The semiconductor integrated circuit according to claim 3, wherein the semiconductor integrated circuit compares a monitoring MOS transistor formed in the second well with a voltage based on the monitoring MOS transistor and a reference potential, and determines a difference voltage between the two. A comparison circuit for outputting, an output means for outputting an internal power supply voltage corresponding to a difference voltage of the comparison circuit, and a drive circuit for periodically driving a boosting capacitor based on the internal power supply voltage. And a substrate voltage generating circuit for generating a substrate voltage. 5. The circuit according to claim 1, wherein a source and a source of the first and third MOS transistors and a source of the second and fourth MOS transistors are both connected during standby and during operation of the circuit. A predetermined voltage is applied during the period of (i).