JP2000066954A - Replacing method for cache memory and cache memory using the method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a miss ratio and to obtain a high performance cache memory by storing a tag that is subjected to an access request in the past in turn and considering spatial locality belonging to the same tag by referring to the tag stored at the time of replacement. SOLUTION: The tag 11 of a target address 1 that is subjected to an access request from a CPU is inputted to a tag history queue 33. The queue 33 stores some tags which are subjected to an access request in the past and they are referred to for making a virtual victim consider spatial locality at the time of making a victim selection at the time of cache miss. A tag comparison unit 41 compares an address tag read from an address tag memory 21 of a cache memory 2 with the tag 11. When miss occurs in cache, a LRU control unit 32 selects the virtual victim and target data is replaced with this victim.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a set associative cache memory replacement method using an LRU replacement algorithm and a cache memory using the same.

[0002]

2. Description of the Related Art In recent years, in a computer system, in order to operate a CPU at high speed, a cache memory device having a small capacity and capable of high-speed operation is generally arranged between the CPU and a main memory. . The cache memory holds frequently used data in block units. When the CPU accesses the cache memory, a case where an entry including the requested data exists in the cache is called a hit, and a case where it does not exist is called a miss. The missed data is transferred from the main memory to the CPU. At this time, the requested data is simultaneously replaced with an entry existing in the cache. The time spent for this transfer and replacement is called miss penalty.

There are various types of caches, but one of them is a set associative cache using an LRU replacement algorithm. The set associative cache is a method in which a block to be replaced can be placed only in n ways on the cache, and nw
Also referred to as an ay set associative cache. On the other hand, LRU (Least Recently Used)
The algorithm is an algorithm that replaces a data block that has not been used for the longest time. For example, in the memory control circuit disclosed in JP-A-1-173239, when a cache miss occurs, the LRU
A predetermined data block in the cache memory is replaced according to an algorithm.

[0004]

As described above, in the set associative cache using the conventional LRU replacement algorithm, only temporal locality is considered, so an entry having high spatial locality is replaced. There was a problem that could be. Also,
In the method of considering the spatial locality by increasing the block size of the cache memory, there is a problem that the penalty at the time of a miss is increased and the performance is not improved.

An object of the present invention is to provide a high-performance cache memory which can reduce the miss rate.

[0006]

SUMMARY OF THE INVENTION A cache memory replacement method according to the present invention includes a set associative cache memory using an LRU replacement algorithm, in addition to an LRU replacement algorithm that considers temporal locality only by using an index, and also uses a past RRU replacement algorithm. Are sequentially stored, and at the time of replacement, the spatial locality of the same tag is considered by referring to the stored tag.

A cache memory replacement method according to the present invention provides a set associative cache memory using an LRU replacement algorithm.
Some tags accessed in the past are stored in order, and when a victim is selected after a cache miss, the tag and
The method is characterized by comparing the address tag of the temporary victim selected by the LRU replacement algorithm with the address tag of the temporary victim and, when detecting the same address tag having high spatial locality, re-selecting the victim.

Further, the cache memory of the present invention has a LR
In a set associative cache memory using a U-replace algorithm, a storage unit in which each entry is composed of an address tag, a valid bit, and a data block, a target data hit / miss determination unit, and control at the time of replacement. Replacement control means.

Further, in the cache memory according to the present invention, the replacement control means may include means for inputting a target data block transferred from the main memory to the CPU at the time of cache replacement, and It is characterized by having LRU control means for performing calculation for selection and control at the time of replacement, and means for storing some tags for which access requests have been made in the past.

Further, in the cache memory according to the present invention, the hit / miss discriminating means for the target data compares the address tag read from the storage means with the tag of the target address, and determines which way in the set. It is characterized by having a tag comparing means for judging whether a hit or all misses have occurred.

Further, in the cache memory according to the present invention, the replacement control means has a prefetch function.

[0012]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an LRU in which both temporal locality and spatial locality are considered as a first embodiment of the present invention.
FIG. 11 is a diagram illustrating a configuration of an n-way set associative cache memory using a replacement algorithm. The n-way set associative cache memory includes a cache memory 2, a replacement control unit 3, and a data control unit 4.

A target address 1 requested to be accessed by a CPU (not shown) is divided into a tag 11, an index 12, and an offset 13. The index 12 indicates which set in the cache memory 2 may have the target data, and the tag 11
Is used as a key for searching whether the target data exists in the set (n) entries indicated by the index 12, and the offset 13 indicates which data of the data block is requested. It is.

Each entry of the cache memory 2 includes an address tag, a valid bit, and a data block. The address tag memory 21, the valid bit memory 22, and the data block memory 23 are each configured by an entry corresponding to an integer 2 raised to the power of the number of index bits. In the case of the n-way set associative, the memories 21 and 22 are used. , 23 are present every n sheets. In each entry, a data block is stored for each address tag, and the valid bit indicates whether the data block specified by the address tag is valid.

The replacement control unit 3 includes a replacement entry 31, an LRU control unit 32, and a tag history queue 33 in the LRU control unit 32. The LRU control unit 32 performs a calculation for selecting a victim at the time of the next cache miss and a control at the time of replacement for each access. The tag history queue 33 stores a number of tags 11 for which an access request has been made in the past, and is used as spatial locality information when selecting a victim. On the other hand, at the time of cache replacement, the replacement entry 31 stores the CPU from the main memory (not shown).
, A target data block to be transferred to the
The entry of the victim selected by the RU control unit 32 is replaced.

The data control unit 4 includes a tag comparing unit 41
And a data selection unit 42. The tag comparing unit 41 compares the n address tags read from the address tag memory 21 with the tag 11 of the target address 1 and selects which way in the set has been hit or has missed all. Output to the unit 42 and the LRU control unit 32. The data selection unit 42 outputs the wa output from the tag comparison unit 41.
The data indicated by the offset 13 from the data block of the entry y is output to the outside.

Next, the operation of this embodiment will be described with reference to the flowcharts of FIGS. First, the tag 11 of the target address 1 requested to be accessed by the CPU (step A0) is input to the tag history queue 33 in the LRU control unit 32 (step A1). Here, in the tag history queue 33, some tags that have been requested to access in the past are stored, and when a victim is selected at the time of a cache miss, the tags are selected by an LRU replacement algorithm that considers only temporal locality. It is referred to make the temporary victim consider the spatial locality.
However, if the tag 11 is the same as the previous input, the target address 1 is not input to the tag history queue 33.

Next, the cache memory 2 uses the index 12 of the target address 1 to select a set in which the target address 1 may be stored,
An address tag for n entries (in the case of the n-way set associative) and a data block are read (step A2).

Next, the tag comparison unit 41 compares the address tag of the entry read in step A2 with the tag 11 of the target address 1 to determine whether it is a hit or a miss. At this time, if the valid bit indicates that the entry is invalid, the entry is regarded as a miss (step A3, step A4).

When a hit occurs in the cache, the tag comparing unit 41 determines how many hit entries
LRU control unit 3
2 and the data selection unit 42. Based on the way information notified from the tag comparison unit 41, the LR
The U control unit 32 performs a calculation for the next victim selection (step A5). Further, the data selection unit 42
The hit data block is selected based on the way information notified from the tag comparing unit 41 (step A6),
The required data is output from the hit data block with reference to the offset 13 of the target address 1 (step A7).

On the other hand, when a cache miss occurs,
The RU control unit 32 selects a temporary victim based on the information calculated in advance (step A8), and the tag comparison unit 41 compares the address tag of the temporary victim with the tag 11 of the entry in the tag history queue 33. (Step A9). If the address tag of the temporary victim does not match any of the tags 11 in the tag history queue 33, the temporary victim becomes a true victim, and the target data is replaced with the true victim (step A11). ). If a match is found between the true victim and the tag 11 in the tag history queue 33, the LRU control unit 32 reselects the victim again with an entry in the same set other than the temporary victim.

As described above, according to the present embodiment, in the LRU replacement algorithm considering only the temporal locality, the entry having the same address tag with high spatial locality is prevented from being replaced as a victim. Is done.

Next, a second embodiment of the present invention will be described. This embodiment has the same basic configuration as that of the first embodiment, but further devises a miss latency. That is, as shown in FIG. 3, in the present embodiment, an LRU / prefetch control unit 32 ′ is provided instead of the LRU control unit 32 in FIG.
A prefetch entry 31 'is provided, and the replacement control unit 3 is configured to incorporate a prefetch function.

In this embodiment, the LRU /
The prefetch control unit 32 'refers to the tag history queue 33 and transfers an entry that may be requested next time but is not in the cache memory 2 from the main memory to the replace / prefetch entry 31' in advance. Therefore, according to the present embodiment, by prefetching an entry that is likely to be accessed next time, miss latency can be significantly reduced.

[0026]

As described above, according to the present invention, since the spatial locality is considered in addition to the LRU replacement algorithm considering only the temporal locality, an entry having a high spatial locality is replaced. And the cache miss rate can be reduced. Further, since the spatial locality is realized by means other than the enlargement of the block size, the penalty at the time of a mistake does not change and the performance does not decrease. Therefore, according to the present invention, a high-performance cache memory can be provided.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a first exemplary embodiment of the present invention.

FIG. 2 is a diagram illustrating an operation of the first exemplary embodiment of the present invention.

FIG. 3 is a diagram showing a configuration of a second exemplary embodiment of the present invention.

[Explanation of symbols]

 1 Target address 11 Tag 12 Index 13 Offset 2 Cache memory 21 Address tag memory 22 Valid bit memory 23 Data block memory 3 Replacement control unit 31 Replacement entry 32 LRU control unit 33 Tag history queue 4 Data control unit 41 Tag comparison unit 42 Data selection unit

Claims (6)

[Claims] In a set associative cache memory using an LRU replacement algorithm, an LRU considering temporal locality only with an index is used.
In addition to the replacement algorithm, several tags that have been requested for access in the past are stored in order, and at the time of replacement,
A method of replacing a cache memory, wherein a spatial locality of the same tag is considered by referring to the stored tag. 2. A set associative cache memory using an LRU replacement algorithm, in which several tags accessed in the past are sequentially stored, and when a victim is selected after a cache miss occurs, the tag and the LRU replacement algorithm are used. A method for replacing a cache memory, comprising comparing an address tag of a selected temporary victim with an address tag having a high spatial locality and re-selecting the victim. 3. A set associative cache memory using an LRU replacement algorithm, wherein each entry is constituted by an address tag, a valid bit, and a data block; a target data hit / miss determination means; And a replacement control means for controlling time. 4. The replacement control means includes: means for inputting a target data block transferred from the main memory to the CPU at the time of cache replacement; calculation for a victim selection operation at the time of the next cache miss for each access; 4. The cache memory according to claim 3, further comprising LRU control means for performing control, and means for storing some tags for which an access request has been made in the past. 5. The target data hit / miss discriminating means compares the address tag read from the storage means with a tag of a target address, and determines which way in the set has been hit or all of the misses. 5. The cache memory according to claim 3, further comprising a tag comparing unit that determines whether the cache memory has been executed. 6. The cache memory according to claim 3, wherein said replacement control means has a prefetch function.